DE3887862T2 - Cache-Speichervorrichtung. - Google Patents

Cache-Speichervorrichtung.

Info

Publication number
DE3887862T2
DE3887862T2 DE3887862T DE3887862T DE3887862T2 DE 3887862 T2 DE3887862 T2 DE 3887862T2 DE 3887862 T DE3887862 T DE 3887862T DE 3887862 T DE3887862 T DE 3887862T DE 3887862 T2 DE3887862 T2 DE 3887862T2
Authority
DE
Germany
Prior art keywords
memory device
cache memory
cache
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3887862T
Other languages
English (en)
Other versions
DE3887862D1 (de
Inventor
Akio Miyoshi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Publication of DE3887862D1 publication Critical patent/DE3887862D1/de
Application granted granted Critical
Publication of DE3887862T2 publication Critical patent/DE3887862T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0891—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using clearing, invalidating or resetting means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
DE3887862T 1987-12-28 1988-12-28 Cache-Speichervorrichtung. Expired - Fee Related DE3887862T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62332177A JPH01173241A (ja) 1987-12-28 1987-12-28 キャッシュメモリ装置

Publications (2)

Publication Number Publication Date
DE3887862D1 DE3887862D1 (de) 1994-03-24
DE3887862T2 true DE3887862T2 (de) 1994-07-07

Family

ID=18252023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3887862T Expired - Fee Related DE3887862T2 (de) 1987-12-28 1988-12-28 Cache-Speichervorrichtung.

Country Status (4)

Country Link
EP (1) EP0322888B1 (de)
JP (1) JPH01173241A (de)
KR (1) KR910007641B1 (de)
DE (1) DE3887862T2 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2818415B2 (ja) * 1988-05-18 1998-10-30 日本電気株式会社 バッファ記憶装置
EP0541319B1 (de) * 1991-11-04 1997-05-02 Sun Microsystems, Inc. Virtueller Durchschreibcachespeicher Synonym-Adressierung und Cache-Ungültigkeitserklärungen
EP1182566B1 (de) 2000-08-21 2013-05-15 Texas Instruments France Auf Adressenbereich basierender Cache-Speicherbetrieb
JP4753549B2 (ja) 2004-05-31 2011-08-24 パナソニック株式会社 キャッシュメモリおよびシステム
JP5397843B2 (ja) * 2009-08-18 2014-01-22 国立大学法人神戸大学 キャッシュメモリとそのモード切替方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59201287A (ja) * 1983-04-28 1984-11-14 Hitachi Ltd キヤツシユメモリ制御方式
JPS6054057A (ja) * 1983-09-02 1985-03-28 Hitachi Ltd キャッシュメモリ制御装置
US4638431A (en) * 1984-09-17 1987-01-20 Nec Corporation Data processing system for vector processing having a cache invalidation control unit
DE3650021T2 (de) * 1985-10-30 1995-03-09 Ibm Cache-Speicherübereinstimmungsvorrichtung mit Verriegelung.
JPS62145445A (ja) * 1985-12-20 1987-06-29 Fujitsu Ltd キヤツシユメモリシステム
JPS62145342A (ja) * 1985-12-20 1987-06-29 Fujitsu Ltd キヤツシユメモリシステム

Also Published As

Publication number Publication date
EP0322888A2 (de) 1989-07-05
KR910007641B1 (ko) 1991-09-28
DE3887862D1 (de) 1994-03-24
EP0322888A3 (en) 1990-10-10
EP0322888B1 (de) 1994-02-16
KR890010729A (ko) 1989-08-10
JPH01173241A (ja) 1989-07-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee