DE3881929T2 - Verbindungsverfahren für integrierte Schaltungschips. - Google Patents

Verbindungsverfahren für integrierte Schaltungschips.

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Publication number
DE3881929T2
DE3881929T2 DE88104940T DE3881929T DE3881929T2 DE 3881929 T2 DE3881929 T2 DE 3881929T2 DE 88104940 T DE88104940 T DE 88104940T DE 3881929 T DE3881929 T DE 3881929T DE 3881929 T2 DE3881929 T2 DE 3881929T2
Authority
DE
Germany
Prior art keywords
integrated circuit
connection method
circuit chips
solvent
thermoplastic polymer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE88104940T
Other languages
English (en)
Other versions
DE3881929D1 (de
Inventor
William Frank Graham
Mel Augustine Lofurno
Byron Christos Sakiadis
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
EIDP Inc
Original Assignee
EI Du Pont de Nemours and Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by EI Du Pont de Nemours and Co filed Critical EI Du Pont de Nemours and Co
Publication of DE3881929D1 publication Critical patent/DE3881929D1/de
Application granted granted Critical
Publication of DE3881929T2 publication Critical patent/DE3881929T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
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    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
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  • Die Bonding (AREA)
  • Adhesives Or Adhesive Processes (AREA)
DE88104940T 1987-03-30 1988-03-26 Verbindungsverfahren für integrierte Schaltungschips. Expired - Lifetime DE3881929T2 (de)

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US3179387A 1987-03-30 1987-03-30
US8814187A 1987-08-21 1987-08-21

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DE3881929D1 DE3881929D1 (de) 1993-07-29
DE3881929T2 true DE3881929T2 (de) 1993-12-02

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JP (1) JP2515844B2 (de)
KR (1) KR910002828B1 (de)
CA (1) CA1290676C (de)
DE (1) DE3881929T2 (de)
HK (1) HK108393A (de)
IL (1) IL85892A (de)
MY (1) MY103254A (de)

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JP2927982B2 (ja) * 1991-03-18 1999-07-28 ジャパンゴアテックス株式会社 半導体装置
DE4124053A1 (de) * 1991-07-19 1993-01-21 Siemens Ag Verfahren zum herstellen einer haftverbindung zwischen wenigstens einem bauteil und einem metallischen substrat
US5286417A (en) * 1991-12-06 1994-02-15 International Business Machines Corporation Method and composition for making mechanical and electrical contact
CH686325A5 (de) * 1992-11-27 1996-02-29 Esec Sempac Sa Elektronikmodul und Chip-Karte.
US5471017A (en) * 1994-05-31 1995-11-28 Texas Instruments Incorporated No fixture method to cure die attach for bonding IC dies to substrates
KR100450004B1 (ko) 1994-12-26 2004-09-24 히다치 가세고교 가부시끼가이샤 필름 형상의 유기 다이본딩재의 라미네이트 방법,다이본딩 방법, 라미네이트 장치, 다이본딩 장치, 반도체장치 및 반도체 장치의 제조 방법
TW310481B (de) 1995-07-06 1997-07-11 Hitachi Chemical Co Ltd
US7012320B2 (en) 1995-07-06 2006-03-14 Hitachi Chemical Company, Ltd. Semiconductor device and process for fabrication thereof
JP3842362B2 (ja) * 1996-02-28 2006-11-08 株式会社東芝 熱圧着方法および熱圧着装置
JP3928753B2 (ja) 1996-08-06 2007-06-13 日立化成工業株式会社 マルチチップ実装法、および接着剤付チップの製造方法
TW413912B (en) * 1998-04-28 2000-12-01 Lucent Technologies Inc Process for controlling resin bleeding in integrated circuit packaging
JPH11312881A (ja) 1998-04-28 1999-11-09 Matsushita Electric Ind Co Ltd 基板の接合方法、及び高周波回路、アンテナ、導波管、線路変換器、線路分岐回路、並びに通信システム
JP4537555B2 (ja) 2000-09-11 2010-09-01 新日鐵化学株式会社 半導体パッケージの製造方法及び半導体パッケージ
KR100517075B1 (ko) 2003-08-11 2005-09-26 삼성전자주식회사 반도체 소자 제조 방법
JP4743131B2 (ja) * 2007-02-15 2011-08-10 宇部興産株式会社 張合わせウエハ−及びその製造方法、基板
JP5919625B2 (ja) * 2011-02-22 2016-05-18 富士通株式会社 半導体装置及びその製造方法、電源装置
GB201405495D0 (en) * 2014-03-27 2014-05-14 Strip Tinning Ltd Busbars

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Publication number Publication date
IL85892A0 (en) 1988-09-30
EP0285051A3 (en) 1989-05-10
KR910002828B1 (ko) 1991-05-06
DE3881929D1 (de) 1993-07-29
CA1290676C (en) 1991-10-15
EP0285051B1 (de) 1993-06-23
HK108393A (en) 1993-10-22
KR880012129A (ko) 1988-11-03
JPS63289822A (ja) 1988-11-28
MY103254A (en) 1993-05-29
EP0285051A2 (de) 1988-10-05
JP2515844B2 (ja) 1996-07-10
IL85892A (en) 1994-05-30

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