DE3877381D1 - Cmos-flip-flop-speicherzelle. - Google Patents

Cmos-flip-flop-speicherzelle.

Info

Publication number
DE3877381D1
DE3877381D1 DE8888100947T DE3877381T DE3877381D1 DE 3877381 D1 DE3877381 D1 DE 3877381D1 DE 8888100947 T DE8888100947 T DE 8888100947T DE 3877381 T DE3877381 T DE 3877381T DE 3877381 D1 DE3877381 D1 DE 3877381D1
Authority
DE
Germany
Prior art keywords
flip flop
storage cell
cmos flip
flop storage
cmos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888100947T
Other languages
English (en)
Other versions
DE3877381T2 (de
Inventor
Rockett, Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE3877381D1 publication Critical patent/DE3877381D1/de
Application granted granted Critical
Publication of DE3877381T2 publication Critical patent/DE3877381T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G11C11/4125—Cells incorporating circuit means for protecting against loss of information
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE8888100947T 1987-03-09 1988-01-22 Cmos-flip-flop-speicherzelle. Expired - Fee Related DE3877381T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/023,426 US4797804A (en) 1987-03-09 1987-03-09 High density, high performance, single event upset immune data storage cell

Publications (2)

Publication Number Publication Date
DE3877381D1 true DE3877381D1 (de) 1993-02-25
DE3877381T2 DE3877381T2 (de) 1993-07-15

Family

ID=21815023

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888100947T Expired - Fee Related DE3877381T2 (de) 1987-03-09 1988-01-22 Cmos-flip-flop-speicherzelle.

Country Status (4)

Country Link
US (1) US4797804A (de)
EP (1) EP0281741B1 (de)
JP (1) JPS63229748A (de)
DE (1) DE3877381T2 (de)

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4852060A (en) * 1988-03-31 1989-07-25 International Business Machines Corporation Soft error resistant data storage cells
US4912675A (en) * 1988-09-07 1990-03-27 Texas Instruments, Incorporated Single event upset hardened memory cell
US4914629A (en) * 1988-09-07 1990-04-03 Texas Instruments, Incorporated Memory cell including single event upset rate reduction circuitry
US5801396A (en) * 1989-01-18 1998-09-01 Stmicroelectronics, Inc. Inverted field-effect device with polycrystalline silicon/germanium channel
US5770892A (en) * 1989-01-18 1998-06-23 Sgs-Thomson Microelectronics, Inc. Field effect device with polycrystalline silicon channel
JPH0340294A (ja) * 1989-07-05 1991-02-21 Mitsubishi Electric Corp スタティック型半導体記憶装置
US4972391A (en) * 1990-01-31 1990-11-20 Juve Ronald A Breast feeding timer
JPH0799630B2 (ja) * 1990-09-11 1995-10-25 株式会社東芝 スタティック型半導体記憶装置
JPH04155693A (ja) * 1990-10-18 1992-05-28 Nec Ic Microcomput Syst Ltd 半導体記憶装置のデータ出力回路
JP2655765B2 (ja) * 1991-05-29 1997-09-24 ローム株式会社 半導体装置
US5206533A (en) * 1991-06-24 1993-04-27 Texas Instruments Incorporated Transistor device with resistive coupling
US5307142A (en) * 1991-11-15 1994-04-26 The United States Of America As Represented By The United States Department Of Energy High performance static latches with complete single event upset immunity
US5631863A (en) * 1995-02-14 1997-05-20 Honeywell Inc. Random access memory cell resistant to radiation induced upsets
US6140684A (en) * 1997-06-24 2000-10-31 Stmicroelectronic, Inc. SRAM cell structure with dielectric sidewall spacers and drain and channel regions defined along sidewall spacers
US6180984B1 (en) * 1998-12-23 2001-01-30 Honeywell Inc. Integrated circuit impedance device and method of manufacture therefor
US6058041A (en) * 1998-12-23 2000-05-02 Honeywell Inc. SEU hardening circuit
US6252433B1 (en) 1999-05-12 2001-06-26 Southwest Research Institute Single event upset immune comparator
US6369630B1 (en) 1999-11-24 2002-04-09 Bae Systems Information And Electronic Systems Integration Inc. Single-event upset hardened reconfigurable bi-stable CMOS latch
US6573773B2 (en) 2000-02-04 2003-06-03 University Of New Mexico Conflict free radiation tolerant storage cell
US6549443B1 (en) 2001-05-16 2003-04-15 Rockwell Collins, Inc. Single event upset resistant semiconductor circuit element
JP2003060087A (ja) * 2001-08-10 2003-02-28 Mitsubishi Electric Corp 半導体記憶装置
US7071749B2 (en) * 2002-03-25 2006-07-04 Aeroflex Colorado Springs Inc. Error correcting latch
US6573774B1 (en) 2002-03-25 2003-06-03 Aeroflex Utmc Microelectronic Systems, Inc. Error correcting latch
US6735110B1 (en) 2002-04-17 2004-05-11 Xilinx, Inc. Memory cells enhanced for resistance to single event upset
US6624677B1 (en) 2002-07-08 2003-09-23 International Business Machines Corporation Radiation tolerant flip-flop
JP4568471B2 (ja) * 2002-08-30 2010-10-27 三菱重工業株式会社 半導体記憶回路
US8189367B1 (en) * 2007-02-23 2012-05-29 Bae Systems Information And Electronic Systems Integration Inc. Single event upset hardened static random access memory cell
US7876602B2 (en) * 2007-06-18 2011-01-25 Bae Systems Information And Electronic Systems Integration Inc. Single-event upset immune static random access memory cell circuit, system, and method
US7684232B1 (en) 2007-09-11 2010-03-23 Xilinx, Inc. Memory cell for storing a data bit value despite atomic radiation
US8081010B1 (en) 2009-11-24 2011-12-20 Ics, Llc Self restoring logic
US20120032264A1 (en) * 2010-08-09 2012-02-09 Fabio Alessio Marino High density semiconductor latch
RU2541894C1 (ru) * 2013-09-26 2015-02-20 Федеральное государственное бюджетное учреждение науки Российской академии наук Научно-исследовательский институт системных исследований РАН (НИИСИ РАН) Триггер комплементарной металл-оксид-полупроводниковой структуры микросхемы
EP3300254B1 (de) 2016-09-26 2021-07-07 HS Elektronik Systeme GmbH Steuerungsschaltung für festkörperleistungsregler

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4416049A (en) * 1970-05-30 1983-11-22 Texas Instruments Incorporated Semiconductor integrated circuit with vertical implanted polycrystalline silicon resistor
US3786282A (en) * 1970-09-25 1974-01-15 Hughes Aircraft Co Radiation hardened flip flop
JPS5598852A (en) * 1979-01-23 1980-07-28 Nec Corp Memory device
US4425574A (en) * 1979-06-29 1984-01-10 International Business Machines Corporation Buried injector memory cell formed from vertical complementary bipolar transistor circuits and method of fabrication therefor
JPS5847862B2 (ja) * 1979-08-30 1983-10-25 富士通株式会社 半導体記憶装置及びその製造方法
US4441246A (en) * 1980-05-07 1984-04-10 Texas Instruments Incorporated Method of making memory cell by selective oxidation of polysilicon
US4458262A (en) * 1980-05-27 1984-07-03 Supertex, Inc. CMOS Device with ion-implanted channel-stop region and fabrication method therefor
DE3027175A1 (de) * 1980-07-17 1982-02-11 Siemens AG, 1000 Berlin und 8000 München Anordnung zur verringerung der strahlungsempfindlichkeit von in integrierter mos-schaltkreistechnik ausgefuehrten speicherzellen
DE3037744A1 (de) * 1980-10-06 1982-05-19 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen einer monolithisch integrierten zwei-transistor-speicherzelle in mos-technik
US4467519A (en) * 1982-04-01 1984-08-28 International Business Machines Corporation Process for fabricating polycrystalline silicon film resistors
EP0098417A3 (de) * 1982-06-15 1986-12-30 Kabushiki Kaisha Toshiba Halbleiterspeicheranordnung
KR940002772B1 (ko) * 1984-08-31 1994-04-02 가부시기가이샤 히다찌세이사꾸쇼 반도체 집적회로 장치 및 그 제조방법
US4621345A (en) * 1984-12-17 1986-11-04 International Business Machines Corporation Soft error protection circuit for a storage cell
US4638463A (en) * 1985-01-24 1987-01-20 International Business Machines Corporation Fast writing circuit for a soft error protected storage cell
DE3684214D1 (de) * 1985-09-30 1992-04-16 Honeywell Inc Strahlungsfeste speicherzelle.
JPS63166260A (ja) * 1986-12-27 1988-07-09 Mitsubishi Electric Corp 半導体記憶装置
JPH0687499B2 (ja) * 1986-12-27 1994-11-02 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
EP0281741A2 (de) 1988-09-14
US4797804A (en) 1989-01-10
JPS63229748A (ja) 1988-09-26
EP0281741B1 (de) 1993-01-13
JPH0586073B2 (de) 1993-12-09
DE3877381T2 (de) 1993-07-15
EP0281741A3 (en) 1990-05-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee