DE3863797D1 - Dynamische logische anordnung. - Google Patents

Dynamische logische anordnung.

Info

Publication number
DE3863797D1
DE3863797D1 DE8888400303T DE3863797T DE3863797D1 DE 3863797 D1 DE3863797 D1 DE 3863797D1 DE 8888400303 T DE8888400303 T DE 8888400303T DE 3863797 T DE3863797 T DE 3863797T DE 3863797 D1 DE3863797 D1 DE 3863797D1
Authority
DE
Germany
Prior art keywords
logical arrangement
dynamic logical
dynamic
arrangement
logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8888400303T
Other languages
English (en)
Inventor
Francois Anceau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull SA
Original Assignee
Bull SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull SA filed Critical Bull SA
Application granted granted Critical
Publication of DE3863797D1 publication Critical patent/DE3863797D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H03K19/17716—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register
    • H03K19/1772—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register with synchronous operation of at least one of the logical matrixes

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
DE8888400303T 1987-02-12 1988-02-10 Dynamische logische anordnung. Expired - Fee Related DE3863797D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8701741A FR2611099B1 (fr) 1987-02-12 1987-02-12 Reseau logique dynamique

Publications (1)

Publication Number Publication Date
DE3863797D1 true DE3863797D1 (de) 1991-08-29

Family

ID=9347832

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8888400303T Expired - Fee Related DE3863797D1 (de) 1987-02-12 1988-02-10 Dynamische logische anordnung.

Country Status (6)

Country Link
US (1) US4812685A (de)
EP (1) EP0282370B1 (de)
JP (1) JPH01218212A (de)
CA (1) CA1284359C (de)
DE (1) DE3863797D1 (de)
FR (1) FR2611099B1 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2547436B2 (ja) * 1988-04-11 1996-10-23 富士通株式会社 Ｐｌａ制御方式
US4912342A (en) * 1988-05-05 1990-03-27 Altera Corporation Programmable logic device with array blocks with programmable clocking
US5070262A (en) * 1988-10-06 1991-12-03 Texas Instruments Incorporated Signal transmission circuit
JP2515853Y2 (ja) * 1989-04-06 1996-10-30 沖電気工業株式会社 ダイナミック型ｐｌａ回路
US5926038A (en) * 1997-11-10 1999-07-20 The United States Of America As Represented By The Secretary Of The Navy Two-phase dynamic logic circuits for gallium arsenide complementary HIGFET fabrication
US7116131B1 (en) 2004-09-15 2006-10-03 Xilinx, Inc. High performance programmable logic devices utilizing dynamic circuitry

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4381460A (en) * 1980-05-27 1983-04-26 National Semiconductor Corporation Bootstrap driver circuit
US4661922A (en) * 1982-12-08 1987-04-28 American Telephone And Telegraph Company Programmed logic array with two-level control timing
JPS59125125A (ja) * 1982-12-30 1984-07-19 Fujitsu Ltd プログラマブル・ロジツク・アレイ
US4577190A (en) * 1983-04-11 1986-03-18 At&T Bell Laboratories Programmed logic array with auxiliary pull-up means to increase precharging speed
US4611133A (en) * 1983-05-12 1986-09-09 Codex Corporation High speed fully precharged programmable logic array
JPS6169215A (ja) * 1984-09-12 1986-04-09 Nec Corp プログラマブル・ロジツク・アレイ
JPS61101124A (ja) * 1984-10-24 1986-05-20 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
US4740721A (en) * 1985-10-21 1988-04-26 Western Digital Corporation Programmable logic array with single clock dynamic logic
IT1195119B (it) * 1986-08-04 1988-10-12 Cselt Centro Studi Lab Telecom Perfezionamenti alle schiere logi che programmabili dinamiche a struttura nor nor realizzate in tecnolo gia c mos
US4760290A (en) * 1987-05-21 1988-07-26 Vlsi Technology, Inc. Synchronous logic array circuit with dummy signal lines for controlling "AND" array output
JPH11651A (ja) * 1997-06-12 1999-01-06 Hitachi Ltd 懸濁物除去装置

Also Published As

Publication number Publication date
EP0282370B1 (de) 1991-07-24
EP0282370A3 (en) 1988-09-21
JPH01218212A (ja) 1989-08-31
FR2611099A1 (fr) 1988-08-19
FR2611099B1 (fr) 1993-02-12
US4812685A (en) 1989-03-14
CA1284359C (fr) 1991-05-21
EP0282370A2 (de) 1988-09-14

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee