DE3852903T2 - Hohe Durchbruchspannung aufweisende isolierende Schicht, die zwischen Polysilizium-Schichten liegt. - Google Patents

Hohe Durchbruchspannung aufweisende isolierende Schicht, die zwischen Polysilizium-Schichten liegt.

Info

Publication number
DE3852903T2
DE3852903T2 DE3852903T DE3852903T DE3852903T2 DE 3852903 T2 DE3852903 T2 DE 3852903T2 DE 3852903 T DE3852903 T DE 3852903T DE 3852903 T DE3852903 T DE 3852903T DE 3852903 T2 DE3852903 T2 DE 3852903T2
Authority
DE
Germany
Prior art keywords
lies
insulating layer
breakdown voltage
high breakdown
polysilicon layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3852903T
Other languages
English (en)
Other versions
DE3852903D1 (de
Inventor
Yuuichi C O Patent Divi Mikata
Katsunori Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Toshiba Electronic Device Solutions Corp
Original Assignee
Toshiba Corp
Toshiba Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Toshiba Microelectronics Corp filed Critical Toshiba Corp
Publication of DE3852903D1 publication Critical patent/DE3852903D1/de
Application granted granted Critical
Publication of DE3852903T2 publication Critical patent/DE3852903T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C17/00Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40114Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Memories (AREA)
DE3852903T 1987-04-14 1988-04-12 Hohe Durchbruchspannung aufweisende isolierende Schicht, die zwischen Polysilizium-Schichten liegt. Expired - Fee Related DE3852903T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62089773A JPS63255972A (ja) 1987-04-14 1987-04-14 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3852903D1 DE3852903D1 (de) 1995-03-16
DE3852903T2 true DE3852903T2 (de) 1995-06-29

Family

ID=13979997

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3852903T Expired - Fee Related DE3852903T2 (de) 1987-04-14 1988-04-12 Hohe Durchbruchspannung aufweisende isolierende Schicht, die zwischen Polysilizium-Schichten liegt.

Country Status (4)

Country Link
EP (1) EP0287031B1 (de)
JP (1) JPS63255972A (de)
KR (1) KR910006592B1 (de)
DE (1) DE3852903T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6414968A (en) * 1987-07-08 1989-01-19 Nec Corp Formation of gate electrode
EP0434383B1 (de) * 1989-12-20 1994-03-16 Nec Corporation Gatestruktur eines Halbleiterbauelementes mit darin enthaltener Oxidschicht
KR970009976B1 (ko) * 1991-08-26 1997-06-19 아메리칸 텔리폰 앤드 텔레그라프 캄파니 증착된 반도체상에 형성된 개선된 유전체
JP2951082B2 (ja) * 1991-10-24 1999-09-20 株式会社東芝 半導体記憶装置およびその製造方法
JP3548984B2 (ja) * 1991-11-14 2004-08-04 富士通株式会社 半導体装置の製造方法
JP3383140B2 (ja) 1995-10-02 2003-03-04 株式会社東芝 不揮発性半導体記憶装置の製造方法
JP3233217B2 (ja) * 1999-03-16 2001-11-26 日本電気株式会社 半導体装置の製造方法
US8124515B2 (en) * 2009-05-20 2012-02-28 Globalfoundries Inc. Gate etch optimization through silicon dopant profile change

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4441249A (en) * 1982-05-26 1984-04-10 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit capacitor
JPH0638496B2 (ja) * 1983-06-27 1994-05-18 日本電気株式会社 半導体装置

Also Published As

Publication number Publication date
EP0287031A3 (en) 1989-09-20
DE3852903D1 (de) 1995-03-16
EP0287031A2 (de) 1988-10-19
JPH0581193B2 (de) 1993-11-11
KR910006592B1 (ko) 1991-08-28
JPS63255972A (ja) 1988-10-24
EP0287031B1 (de) 1995-02-01
KR880013232A (ko) 1988-11-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee