DE3802066C2 - - Google Patents

Info

Publication number
DE3802066C2
DE3802066C2 DE3802066A DE3802066A DE3802066C2 DE 3802066 C2 DE3802066 C2 DE 3802066C2 DE 3802066 A DE3802066 A DE 3802066A DE 3802066 A DE3802066 A DE 3802066A DE 3802066 C2 DE3802066 C2 DE 3802066C2
Authority
DE
Germany
Prior art keywords
insulating film
semiconductor device
connection structure
connecting line
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE3802066A
Other languages
German (de)
English (en)
Other versions
DE3802066A1 (de
Inventor
Shinichi Satoh
Makoto Hirayama
Masao Nagatomo
Ikuo Ogoh
Yoshikazu Ohno
Masato Itami Hyogo Jp Fujinaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of DE3802066A1 publication Critical patent/DE3802066A1/de
Application granted granted Critical
Publication of DE3802066C2 publication Critical patent/DE3802066C2/de
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Memories (AREA)
DE3802066A 1987-03-10 1988-01-25 Halbleitereinrichtung mit gegenseitigen verbindungsschichten von t-foermigem querschnitt Granted DE3802066A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62055904A JP2584986B2 (ja) 1987-03-10 1987-03-10 半導体装置の配線構造

Publications (2)

Publication Number Publication Date
DE3802066A1 DE3802066A1 (de) 1988-09-22
DE3802066C2 true DE3802066C2 (es) 1992-07-23

Family

ID=13012102

Family Applications (1)

Application Number Title Priority Date Filing Date
DE3802066A Granted DE3802066A1 (de) 1987-03-10 1988-01-25 Halbleitereinrichtung mit gegenseitigen verbindungsschichten von t-foermigem querschnitt

Country Status (3)

Country Link
US (1) US4905068A (es)
JP (1) JP2584986B2 (es)
DE (1) DE3802066A1 (es)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196233A (en) * 1989-01-18 1993-03-23 Sgs-Thomson Microelectronics, Inc. Method for fabricating semiconductor circuits
US5216280A (en) * 1989-12-02 1993-06-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device having pads at periphery of semiconductor chip
US5077595A (en) * 1990-01-25 1991-12-31 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
JPH05152293A (ja) * 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5504375A (en) * 1992-03-02 1996-04-02 International Business Machines Corporation Asymmetric studs and connecting lines to minimize stress
US5486493A (en) * 1994-02-25 1996-01-23 Jeng; Shin-Puu Planarized multi-level interconnect scheme with embedded low-dielectric constant insulators
US5670815A (en) * 1994-07-05 1997-09-23 Motorola, Inc. Layout for noise reduction on a reference voltage
US5691566A (en) * 1996-03-25 1997-11-25 Hughes Electronics Tapered three-wire line vertical connections
US5854515A (en) * 1996-07-23 1998-12-29 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area
US5847462A (en) * 1996-11-14 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
JPH1174480A (ja) * 1997-08-29 1999-03-16 Oki Electric Ind Co Ltd 半導体メモリ及びその製造方法
EP0978875A1 (en) * 1998-08-07 2000-02-09 STMicroelectronics S.r.l. Integrated circuit comprising conductive lines with "negative" profile and related method of fabrication
KR100338775B1 (ko) * 2000-06-20 2002-05-31 윤종용 Ｄｒａｍ을 포함하는 반도체 소자의 콘택 구조체 및 그형성방법
US7227768B2 (en) * 2005-07-01 2007-06-05 Spansion Llc Power interconnect structure for balanced bitline capacitance in a memory array

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488166A (en) * 1980-12-09 1984-12-11 Fairchild Camera & Instrument Corp. Multilayer metal silicide interconnections for integrated circuits
FR2507979B1 (fr) * 1981-06-17 1986-07-11 Manutis Dispositif elevateur d'une plate-forme monte sur un vehicule automobile
JPS58100434A (ja) * 1981-12-10 1983-06-15 Matsushita Electronics Corp リフトオフ用スペ−サ−の形成方法
US4617193A (en) * 1983-06-16 1986-10-14 Digital Equipment Corporation Planar interconnect for integrated circuits
JPS60780A (ja) * 1983-06-17 1985-01-05 Nec Corp 電界効果トランジスタの製造方法
JPS60206164A (ja) * 1984-03-30 1985-10-17 Toshiba Corp 半導体メモリ装置
JPS60229374A (ja) * 1984-04-27 1985-11-14 Toshiba Corp 半導体装置およびその製造方法
JPH0628290B2 (ja) * 1985-10-09 1994-04-13 三菱電機株式会社 回路用ヒューズを備えた半導体装置
JPS6290950A (ja) * 1985-10-16 1987-04-25 Mitsubishi Electric Corp 半導体装置

Also Published As

Publication number Publication date
US4905068A (en) 1990-02-27
JPS63221642A (ja) 1988-09-14
DE3802066A1 (de) 1988-09-22
JP2584986B2 (ja) 1997-02-26

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)
8328 Change in the person/name/address of the agent

Representative=s name: PRUFER & PARTNER GBR, 81545 MUENCHEN

8339 Ceased/non-payment of the annual fee