DE3783608D1 - Planarizierungsverfahren fuer die herstellung von kontaktloechern in siliziumkoerpern. - Google Patents

Planarizierungsverfahren fuer die herstellung von kontaktloechern in siliziumkoerpern.

Info

Publication number
DE3783608D1
DE3783608D1 DE8787904195T DE3783608T DE3783608D1 DE 3783608 D1 DE3783608 D1 DE 3783608D1 DE 8787904195 T DE8787904195 T DE 8787904195T DE 3783608 T DE3783608 T DE 3783608T DE 3783608 D1 DE3783608 D1 DE 3783608D1
Authority
DE
Germany
Prior art keywords
production
contact holes
planarization method
silicon bodies
bodies
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787904195T
Other languages
English (en)
Other versions
DE3783608T2 (de
Inventor
Nicholas F Pasch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
LSI Corp
Original Assignee
LSI Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by LSI Logic Corp filed Critical LSI Logic Corp
Application granted granted Critical
Publication of DE3783608D1 publication Critical patent/DE3783608D1/de
Publication of DE3783608T2 publication Critical patent/DE3783608T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8787904195T 1986-06-19 1987-06-11 Planarizierungsverfahren fuer die herstellung von kontaktloechern in siliziumkoerpern. Expired - Fee Related DE3783608T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/876,019 US4708770A (en) 1986-06-19 1986-06-19 Planarized process for forming vias in silicon wafers
PCT/US1987/001404 WO1987007979A1 (en) 1986-06-19 1987-06-11 Planarized process for forming vias in silicon wafers

Publications (2)

Publication Number Publication Date
DE3783608D1 true DE3783608D1 (de) 1993-02-25
DE3783608T2 DE3783608T2 (de) 1993-05-13

Family

ID=25366808

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787904195T Expired - Fee Related DE3783608T2 (de) 1986-06-19 1987-06-11 Planarizierungsverfahren fuer die herstellung von kontaktloechern in siliziumkoerpern.

Country Status (7)

Country Link
US (1) US4708770A (de)
EP (1) EP0311627B1 (de)
JP (1) JPH0775235B2 (de)
KR (1) KR960011933B1 (de)
AU (1) AU7583487A (de)
DE (1) DE3783608T2 (de)
WO (1) WO1987007979A1 (de)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824521A (en) * 1987-04-01 1989-04-25 Fairchild Semiconductor Corporation Planarization of metal pillars on uneven substrates
US4839311A (en) * 1987-08-14 1989-06-13 National Semiconductor Corporation Etch back detection
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
US5068711A (en) * 1989-03-20 1991-11-26 Fujitsu Limited Semiconductor device having a planarized surface
JP2556138B2 (ja) * 1989-06-30 1996-11-20 日本電気株式会社 半導体装置の製造方法
US5290396A (en) * 1991-06-06 1994-03-01 Lsi Logic Corporation Trench planarization techniques
US5413966A (en) * 1990-12-20 1995-05-09 Lsi Logic Corporation Shallow trench etch
KR920017227A (ko) * 1991-02-05 1992-09-26 김광호 반도체장치의 층간콘택 구조 및 그 제조방법
US5225358A (en) * 1991-06-06 1993-07-06 Lsi Logic Corporation Method of forming late isolation with polishing
US5252503A (en) * 1991-06-06 1993-10-12 Lsi Logic Corporation Techniques for forming isolation structures
US5248625A (en) * 1991-06-06 1993-09-28 Lsi Logic Corporation Techniques for forming isolation structures
US5284804A (en) * 1991-12-31 1994-02-08 Texas Instruments Incorporated Global planarization process
US5265378A (en) * 1992-07-10 1993-11-30 Lsi Logic Corporation Detecting the endpoint of chem-mech polishing and resulting semiconductor device
US5268332A (en) * 1992-11-12 1993-12-07 At&T Bell Laboratories Method of integrated circuit fabrication having planarized dielectrics
US5436411A (en) * 1993-12-20 1995-07-25 Lsi Logic Corporation Fabrication of substrates for multi-chip modules
US5560802A (en) * 1995-03-03 1996-10-01 Texas Instruments Incorporated Selective CMP of in-situ deposited multilayer films to enhance nonplanar step height reduction
US5861673A (en) * 1995-11-16 1999-01-19 Taiwan Semiconductor Manufacturing Company Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations
WO2006075444A1 (ja) * 2005-01-12 2006-07-20 Sharp Kabushiki Kaisha 半導体装置の製造方法、及び半導体装置
DE102005021769A1 (de) * 2005-05-11 2006-11-23 Sms Demag Ag Verfahren und Vorrichtung zur gezielten Beeinflussung der Vorbandgeometrie in einem Vorgerüst
JP5259095B2 (ja) * 2006-06-19 2013-08-07 新光電気工業株式会社 半導体装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3784424A (en) * 1971-09-27 1974-01-08 Gen Electric Process for boron containing glasses useful with semiconductor devices
US4305760A (en) * 1978-12-22 1981-12-15 Ncr Corporation Polysilicon-to-substrate contact processing
NL8004007A (nl) * 1980-07-11 1982-02-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting.
US4451326A (en) * 1983-09-07 1984-05-29 Advanced Micro Devices, Inc. Method for interconnecting metallic layers
US4635347A (en) * 1985-03-29 1987-01-13 Advanced Micro Devices, Inc. Method of fabricating titanium silicide gate electrodes and interconnections

Also Published As

Publication number Publication date
EP0311627A4 (de) 1989-12-13
JPH01503021A (ja) 1989-10-12
KR880701459A (ko) 1988-07-27
WO1987007979A1 (en) 1987-12-30
US4708770A (en) 1987-11-24
DE3783608T2 (de) 1993-05-13
AU7583487A (en) 1988-01-12
EP0311627A1 (de) 1989-04-19
EP0311627B1 (de) 1993-01-13
KR960011933B1 (en) 1996-09-04
JPH0775235B2 (ja) 1995-08-09

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee