DE3780327T2 - Herstellungsverfahren einer halbleiter-kristallschicht. - Google Patents

Herstellungsverfahren einer halbleiter-kristallschicht.

Info

Publication number
DE3780327T2
DE3780327T2 DE8787103147T DE3780327T DE3780327T2 DE 3780327 T2 DE3780327 T2 DE 3780327T2 DE 8787103147 T DE8787103147 T DE 8787103147T DE 3780327 T DE3780327 T DE 3780327T DE 3780327 T2 DE3780327 T2 DE 3780327T2
Authority
DE
Germany
Prior art keywords
producing
crystal layer
semiconductor crystal
semiconductor
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787103147T
Other languages
English (en)
Other versions
DE3780327D1 (de
Inventor
Tadashi Mitsubishi D Nishimura
Yasuo Mitsubishi Denki K Inoue
Kazuyuki Mitsubishi D Sugahara
Shigeru Mitsubishi De Kusunoki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
IIZUKA KOZO TOKIO/TOKYO JP
Original Assignee
IIZUKA KOZO TOKIO/TOKYO JP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by IIZUKA KOZO TOKIO/TOKYO JP filed Critical IIZUKA KOZO TOKIO/TOKYO JP
Application granted granted Critical
Publication of DE3780327D1 publication Critical patent/DE3780327D1/de
Publication of DE3780327T2 publication Critical patent/DE3780327T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H01L21/02683—Continuous wave laser beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02609—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76248—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using lateral overgrowth techniques, i.e. ELO techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/903—Dendrite or web or cage technique
    • Y10S117/904—Laser beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Electromagnetism (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
DE8787103147T 1986-03-07 1987-03-05 Herstellungsverfahren einer halbleiter-kristallschicht. Expired - Fee Related DE3780327T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61048468A JPS62206816A (ja) 1986-03-07 1986-03-07 半導体結晶層の製造方法

Publications (2)

Publication Number Publication Date
DE3780327D1 DE3780327D1 (de) 1992-08-20
DE3780327T2 true DE3780327T2 (de) 1993-03-11

Family

ID=12804203

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787103147T Expired - Fee Related DE3780327T2 (de) 1986-03-07 1987-03-05 Herstellungsverfahren einer halbleiter-kristallschicht.

Country Status (4)

Country Link
US (1) US4861418A (de)
EP (1) EP0236953B1 (de)
JP (1) JPS62206816A (de)
DE (1) DE3780327T2 (de)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
JP2980920B2 (ja) * 1989-08-03 1999-11-22 日本エービーエス株式会社 車両用液圧ブレーキ制御装置
DE69127395T2 (de) * 1990-05-11 1998-01-02 Asahi Glass Co Ltd Verfahren zum Herstellen eines Dünnfilm-Transistors mit polykristallinem Halbleiter
US5155559A (en) * 1991-07-25 1992-10-13 North Carolina State University High temperature refractory silicide rectifying contact
DE4128333A1 (de) * 1991-08-27 1993-03-04 Fischer Armin Verfahren zum gettern von soi-schichten
JP3453436B2 (ja) * 1994-09-08 2003-10-06 三菱電機株式会社 半導体層を溶融再結晶化するための装置
US5893948A (en) * 1996-04-05 1999-04-13 Xerox Corporation Method for forming single silicon crystals using nucleation sites
US6066571A (en) * 1997-01-10 2000-05-23 Kabushiki Kaisha Toshiba Method of preparing semiconductor surface
TWI253179B (en) * 2002-09-18 2006-04-11 Sanyo Electric Co Method for making a semiconductor device
WO2004102647A1 (ja) * 2003-05-14 2004-11-25 Fujitsu Limited 半導体薄膜の結晶化方法
JP4986415B2 (ja) * 2004-06-14 2012-07-25 株式会社半導体エネルギー研究所 半導体装置の作製方法
US8389099B1 (en) 2007-06-01 2013-03-05 Rubicon Technology, Inc. Asymmetrical wafer configurations and method for creating the same
US8348720B1 (en) 2007-06-19 2013-01-08 Rubicon Technology, Inc. Ultra-flat, high throughput wafer lapping process

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4371421A (en) * 1981-04-16 1983-02-01 Massachusetts Institute Of Technology Lateral epitaxial growth by seeded solidification
US4448632A (en) * 1981-05-25 1984-05-15 Mitsubishi Denki Kabushiki Kaisha Method of fabricating semiconductor devices
US4494300A (en) * 1981-06-30 1985-01-22 International Business Machines, Inc. Process for forming transistors using silicon ribbons as substrates
JPS5893221A (ja) * 1981-11-30 1983-06-02 Toshiba Corp 半導体薄膜構造とその製造方法
JPS58130517A (ja) * 1982-01-29 1983-08-04 Hitachi Ltd 単結晶薄膜の製造方法
US4479846A (en) * 1982-06-23 1984-10-30 Massachusetts Institute Of Technology Method of entraining dislocations and other crystalline defects in heated film contacting patterned region
JPS5945996A (ja) * 1982-09-03 1984-03-15 Nec Corp 半導体の気相成長方法
JPS59108313A (ja) * 1982-12-13 1984-06-22 Mitsubishi Electric Corp 半導体単結晶層の製造方法
US4592799A (en) * 1983-05-09 1986-06-03 Sony Corporation Method of recrystallizing a polycrystalline, amorphous or small grain material
US4545823A (en) * 1983-11-14 1985-10-08 Hewlett-Packard Company Grain boundary confinement in silicon-on-insulator films
US4564403A (en) * 1984-01-27 1986-01-14 Sony Corporation Research Center Single-crystal semiconductor devices and method for making them
US4590130A (en) * 1984-03-26 1986-05-20 General Electric Company Solid state zone recrystallization of semiconductor material on an insulator
EP0227076B1 (de) * 1985-12-20 1992-06-17 Agency Of Industrial Science And Technology Verfahren zur Herstellung einer monokristallinen dünnen Schicht
JPS62160712A (ja) * 1986-01-09 1987-07-16 Agency Of Ind Science & Technol 半導体装置の製造方法
EP0235819B1 (de) * 1986-03-07 1992-06-10 Iizuka, Kozo Verfahren zum Herstellen einer monokristallinen Halbleiterschicht

Also Published As

Publication number Publication date
US4861418A (en) 1989-08-29
EP0236953A2 (de) 1987-09-16
JPS62206816A (ja) 1987-09-11
JPH0476490B2 (de) 1992-12-03
EP0236953A3 (en) 1989-07-26
EP0236953B1 (de) 1992-07-15
DE3780327D1 (de) 1992-08-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee