DE3779547D1 - Halbleiteranordnung mit einer epitaktischen schicht auf einem einkristallinen substrat mit nicht angepasstem gitter. - Google Patents

Halbleiteranordnung mit einer epitaktischen schicht auf einem einkristallinen substrat mit nicht angepasstem gitter.

Info

Publication number
DE3779547D1
DE3779547D1 DE8787902923T DE3779547T DE3779547D1 DE 3779547 D1 DE3779547 D1 DE 3779547D1 DE 8787902923 T DE8787902923 T DE 8787902923T DE 3779547 T DE3779547 T DE 3779547T DE 3779547 D1 DE3779547 D1 DE 3779547D1
Authority
DE
Germany
Prior art keywords
unmatched
grid
single crystal
crystal substrate
semiconductor arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787902923T
Other languages
English (en)
Other versions
DE3779547T2 (de
Inventor
Sergey Luryi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of DE3779547D1 publication Critical patent/DE3779547D1/de
Application granted granted Critical
Publication of DE3779547T2 publication Critical patent/DE3779547T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02428—Structure
    • H01L21/0243—Surface structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02441—Group 14 semiconducting materials
    • H01L21/0245—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02513—Microstructure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02647—Lateral overgrowth
    • H01L21/0265—Pendeoepitaxy

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Recrystallisation Techniques (AREA)
DE8787902923T 1986-04-10 1987-03-19 Halbleiteranordnung mit einer epitaktischen schicht auf einem einkristallinen substrat mit nicht angepasstem gitter. Expired - Fee Related DE3779547T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US85048386A 1986-04-10 1986-04-10
PCT/US1987/000612 WO1987006392A1 (en) 1986-04-10 1987-03-19 Semiconductor device including an epitaxial layer on a lattice-mismatched single crystal substrate

Publications (2)

Publication Number Publication Date
DE3779547D1 true DE3779547D1 (de) 1992-07-09
DE3779547T2 DE3779547T2 (de) 1993-01-28

Family

ID=25308247

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787902923T Expired - Fee Related DE3779547T2 (de) 1986-04-10 1987-03-19 Halbleiteranordnung mit einer epitaktischen schicht auf einem einkristallinen substrat mit nicht angepasstem gitter.

Country Status (7)

Country Link
EP (1) EP0263866B1 (de)
JP (1) JP2854302B2 (de)
KR (1) KR910005734B1 (de)
CA (1) CA1272527A (de)
DE (1) DE3779547T2 (de)
ES (1) ES2004276A6 (de)
WO (1) WO1987006392A1 (de)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6428808A (en) * 1987-07-23 1989-01-31 Matsushita Electric Ind Co Ltd Method for growing epitaxial thin film crystal
US5079616A (en) * 1988-02-11 1992-01-07 Gte Laboratories Incorporated Semiconductor structure
GB8905511D0 (en) * 1989-03-10 1989-04-19 British Telecomm Preparing substrates
JP4569026B2 (ja) * 2001-03-30 2010-10-27 信越半導体株式会社 半導体基板及びその製造方法
EP3891779A4 (de) * 2018-12-04 2022-08-10 SRI International Verwendung einer nachgiebigen schicht zur beseitigung von stossverklebungen

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2757470A1 (de) * 1977-12-22 1979-07-05 Siemens Ag Verfahren zum herstellen einer halbleiteranordnung

Also Published As

Publication number Publication date
WO1987006392A1 (en) 1987-10-22
EP0263866B1 (de) 1992-06-03
EP0263866A1 (de) 1988-04-20
KR880701456A (ko) 1988-07-27
KR910005734B1 (ko) 1991-08-02
DE3779547T2 (de) 1993-01-28
CA1272527A (en) 1990-08-07
JP2854302B2 (ja) 1999-02-03
JPS63503104A (ja) 1988-11-10
ES2004276A6 (es) 1988-12-16

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN

8339 Ceased/non-payment of the annual fee