DE3777906D1 - Diagnoseschaltung. - Google Patents

Diagnoseschaltung.

Info

Publication number
DE3777906D1
DE3777906D1 DE8787110308T DE3777906T DE3777906D1 DE 3777906 D1 DE3777906 D1 DE 3777906D1 DE 8787110308 T DE8787110308 T DE 8787110308T DE 3777906 T DE3777906 T DE 3777906T DE 3777906 D1 DE3777906 D1 DE 3777906D1
Authority
DE
Germany
Prior art keywords
diagnostic circuit
diagnostic
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787110308T
Other languages
English (en)
Inventor
Michael J Miller
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Electronics America Inc
Original Assignee
Integrated Device Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Integrated Device Technology Inc filed Critical Integrated Device Technology Inc
Application granted granted Critical
Publication of DE3777906D1 publication Critical patent/DE3777906D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
DE8787110308T 1986-07-24 1987-07-16 Diagnoseschaltung. Expired - Lifetime DE3777906D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/888,701 US4710927A (en) 1986-07-24 1986-07-24 Diagnostic circuit

Publications (1)

Publication Number Publication Date
DE3777906D1 true DE3777906D1 (de) 1992-05-07

Family

ID=25393712

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787110308T Expired - Lifetime DE3777906D1 (de) 1986-07-24 1987-07-16 Diagnoseschaltung.

Country Status (4)

Country Link
US (1) US4710927A (de)
EP (1) EP0254981B1 (de)
JP (1) JPH0786525B2 (de)
DE (1) DE3777906D1 (de)

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL192801C (nl) * 1986-09-10 1998-02-03 Philips Electronics Nv Werkwijze voor het testen van een drager met meerdere digitaal-werkende geïntegreerde schakelingen, geïntegreerde schakeling geschikt voor het aanbrengen op een aldus te testen drager, en drager voorzien van meerdere van zulke geïntegreerde schakelingen.
US5084814A (en) * 1987-10-30 1992-01-28 Motorola, Inc. Data processor with development support features
US4862070A (en) * 1987-10-30 1989-08-29 Teradyne, Inc. Apparatus for testing input pin leakage current of a device under test
JPH01320544A (ja) * 1988-06-22 1989-12-26 Toshiba Corp テスト容易化回路
US4912522A (en) * 1988-08-17 1990-03-27 Asea Brown Boveri Inc. Light driven remote system and power supply therefor
JP2594130B2 (ja) * 1988-09-02 1997-03-26 三菱電機株式会社 半導体回路
US4947395A (en) * 1989-02-10 1990-08-07 Ncr Corporation Bus executed scan testing method and apparatus
US5099481A (en) * 1989-02-28 1992-03-24 Integrated Device Technology, Inc. Registered RAM array with parallel and serial interface
US5053949A (en) * 1989-04-03 1991-10-01 Motorola, Inc. No-chip debug peripheral which uses externally provided instructions to control a core processing unit
US5805792A (en) * 1989-07-31 1998-09-08 Texas Instruments Incorporated Emulation devices, systems, and methods
US5048021A (en) * 1989-08-28 1991-09-10 At&T Bell Laboratories Method and apparatus for generating control signals
NL8902964A (nl) * 1989-12-01 1991-07-01 Philips Nv Op substraat geintegreerd teststelsel.
US5581564A (en) * 1990-12-18 1996-12-03 Integrated Device Technology, Inc. Diagnostic circuit
JPH05302961A (ja) * 1991-03-27 1993-11-16 Nec Corp Ｌｓｉに於けるテスト信号出力回路
US5355369A (en) * 1991-04-26 1994-10-11 At&T Bell Laboratories High-speed integrated circuit testing with JTAG
JP2770617B2 (ja) * 1991-09-05 1998-07-02 日本電気株式会社 テスト回路
US5448576A (en) * 1992-10-29 1995-09-05 Bull Hn Information Systems Inc. Boundary scan architecture extension
US6055658A (en) * 1995-10-02 2000-04-25 International Business Machines Corporation Apparatus and method for testing high speed components using low speed test apparatus
US5898701A (en) * 1995-12-21 1999-04-27 Cypress Semiconductor Corporation Method and apparatus for testing a device
US5793946A (en) * 1996-03-12 1998-08-11 Varis Corporation Run-time diagnostic system
US5835503A (en) * 1996-03-28 1998-11-10 Cypress Semiconductor Corp. Method and apparatus for serially programming a programmable logic device
US5768288A (en) * 1996-03-28 1998-06-16 Cypress Semiconductor Corp. Method and apparatus for programming a programmable logic device having verify logic for comparing verify data read from a memory location with program data
US5815510A (en) * 1996-03-28 1998-09-29 Cypress Semiconductor Corp. Serial programming of instruction codes in different numbers of clock cycles
US5869979A (en) * 1996-04-05 1999-02-09 Altera Corporation Technique for preconditioning I/Os during reconfiguration
US6130842A (en) * 1997-08-08 2000-10-10 Cypress Semiconductor Corporation Adjustable verify and program voltages in programmable devices
US6430718B1 (en) 1999-08-30 2002-08-06 Cypress Semiconductor Corp. Architecture, circuitry and method for testing one or more integrated circuits and/or receiving test information therefrom
US7340596B1 (en) 2000-06-12 2008-03-04 Altera Corporation Embedded processor with watchdog timer for programmable logic
US6803785B1 (en) 2000-06-12 2004-10-12 Altera Corporation I/O circuitry shared between processor and programmable logic portions of an integrated circuit
US6961884B1 (en) 2000-06-12 2005-11-01 Altera Corporation JTAG mirroring circuitry and methods
US6681359B1 (en) 2000-08-07 2004-01-20 Cypress Semiconductor Corp. Semiconductor memory self-test controllable at board level using standard interface
US7076711B1 (en) 2002-06-10 2006-07-11 Cisco Technology, Inc. Automatic testing of microprocessor bus integrity
US6910087B2 (en) * 2002-06-10 2005-06-21 Lsi Logic Corporation Dynamic command buffer for a slave device on a data bus
US7424658B1 (en) 2002-07-01 2008-09-09 Altera Corporation Method and apparatus for testing integrated circuits
US7113749B2 (en) * 2003-07-18 2006-09-26 International Business Machines Corporation System and method for measuring a high speed signal
TWI241492B (en) * 2004-05-13 2005-10-11 Sunplus Technology Co Ltd Method and chips being able to expand I/O pins of chip
US7583087B2 (en) * 2005-02-22 2009-09-01 Integrated Device Technology, Inc. In-situ monitor of process and device parameters in integrated circuits
US7594149B2 (en) * 2005-02-22 2009-09-22 Integrated Device Technology, Inc. In-situ monitor of process and device parameters in integrated circuits
KR101796116B1 (ko) 2010-10-20 2017-11-10 삼성전자 주식회사 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4286173A (en) * 1978-03-27 1981-08-25 Hitachi, Ltd. Logical circuit having bypass circuit
DE3009945A1 (de) * 1979-03-15 1980-09-18 Nippon Electric Co Integrierter, logischer schaltkreis mit funktionspruefung
US4476560A (en) * 1982-09-21 1984-10-09 Advanced Micro Devices, Inc. Diagnostic circuit for digital systems
DE3274910D1 (en) * 1982-09-28 1987-02-05 Ibm Device for loading and reading different chains of bistable circuits in a data processing system
JPS59161744A (ja) * 1983-03-04 1984-09-12 Hitachi Ltd 情報処理装置のスキヤン方式
JPS6068624A (ja) * 1983-09-26 1985-04-19 Toshiba Corp Ｌｓｉの自己検査装置
DE3373730D1 (en) * 1983-12-15 1987-10-22 Ibm Series-parallel/parallel-series device for variable bit length configuration
US4649539A (en) * 1985-11-04 1987-03-10 Honeywell Information Systems Inc. Apparatus providing improved diagnosability

Also Published As

Publication number Publication date
US4710927A (en) 1987-12-01
EP0254981B1 (de) 1992-04-01
EP0254981A2 (de) 1988-02-03
JPS63100386A (ja) 1988-05-02
EP0254981A3 (en) 1989-10-18
JPH0786525B2 (ja) 1995-09-20
US4710927B1 (de) 1993-08-31

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: BLUMBACH, KRAMER & PARTNER, 65193 WIESBADEN