DE3777847D1 - Verfahren zur ablagerung eines halbleitermaterials und nach diesem verfahren hergestellte anordnung. - Google Patents

Verfahren zur ablagerung eines halbleitermaterials und nach diesem verfahren hergestellte anordnung.

Info

Publication number
DE3777847D1
DE3777847D1 DE8787300560T DE3777847T DE3777847D1 DE 3777847 D1 DE3777847 D1 DE 3777847D1 DE 8787300560 T DE8787300560 T DE 8787300560T DE 3777847 T DE3777847 T DE 3777847T DE 3777847 D1 DE3777847 D1 DE 3777847D1
Authority
DE
Germany
Prior art keywords
depositing
semiconductor material
arrangement produced
arrangement
produced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787300560T
Other languages
English (en)
Inventor
Hadis Morkoc
Russ Fischer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
University of Illinois
University of Illinois at Urbana Champaign
Original Assignee
University of Illinois
University of Illinois at Urbana Champaign
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by University of Illinois, University of Illinois at Urbana Champaign filed Critical University of Illinois
Application granted granted Critical
Publication of DE3777847D1 publication Critical patent/DE3777847D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
    • Y10S117/901—Levitation, reduced gravity, microgravity, space
    • Y10S117/902—Specified orientation, shape, crystallography, or size of seed or substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/048—Energy beam assisted EPI growth
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/059—Germanium on silicon or Ge-Si on III-V
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
DE8787300560T 1986-01-24 1987-01-22 Verfahren zur ablagerung eines halbleitermaterials und nach diesem verfahren hergestellte anordnung. Expired - Lifetime DE3777847D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/822,343 US4707216A (en) 1986-01-24 1986-01-24 Semiconductor deposition method and device

Publications (1)

Publication Number Publication Date
DE3777847D1 true DE3777847D1 (de) 1992-05-07

Family

ID=25235768

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787300560T Expired - Lifetime DE3777847D1 (de) 1986-01-24 1987-01-22 Verfahren zur ablagerung eines halbleitermaterials und nach diesem verfahren hergestellte anordnung.

Country Status (5)

Country Link
US (1) US4707216A (de)
EP (1) EP0232082B1 (de)
JP (1) JP2510859B2 (de)
CA (1) CA1299068C (de)
DE (1) DE3777847D1 (de)

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US4806996A (en) * 1986-04-10 1989-02-21 American Telephone And Telegraph Company, At&T Bell Laboratories Dislocation-free epitaxial layer on a lattice-mismatched porous or otherwise submicron patterned single crystal substrate
JPS63108709A (ja) * 1986-10-25 1988-05-13 Toyota Central Res & Dev Lab Inc 半導体装置およびその製造方法
US5578521A (en) * 1986-11-20 1996-11-26 Nippondenso Co., Ltd. Semiconductor device with vaporphase grown epitaxial
US4952527A (en) * 1988-02-19 1990-08-28 Massachusetts Institute Of Technology Method of making buffer layers for III-V devices using solid phase epitaxy
JP2691721B2 (ja) * 1988-03-04 1997-12-17 富士通株式会社 半導体薄膜の製造方法
JPH01275500A (ja) * 1988-04-25 1989-11-06 Nippon Telegr & Teleph Corp <Ntt> 半導体エピタキシャル成長法
JPH01289108A (ja) * 1988-05-17 1989-11-21 Fujitsu Ltd ヘテロエピタキシャル成長方法
JPH01296612A (ja) * 1988-05-24 1989-11-30 Fujitsu Ltd 半導体結晶の製造方法
US4935385A (en) * 1988-07-22 1990-06-19 Xerox Corporation Method of forming intermediate buffer films with low plastic deformation threshold using lattice mismatched heteroepitaxy
US4994867A (en) * 1988-07-22 1991-02-19 Xerox Corporation Intermediate buffer films with low plastic deformation threshold for lattice mismatched heteroepitaxy
US5238869A (en) * 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
US5221367A (en) * 1988-08-03 1993-06-22 International Business Machines, Corp. Strained defect-free epitaxial mismatched heterostructures and method of fabrication
US5264389A (en) * 1988-09-29 1993-11-23 Sanyo Electric Co., Ltd. Method of manufacturing a semiconductor laser device
US4994408A (en) * 1989-02-06 1991-02-19 Motorola Inc. Epitaxial film growth using low pressure MOCVD
GB8905511D0 (en) * 1989-03-10 1989-04-19 British Telecomm Preparing substrates
FR2647957A1 (fr) * 1989-05-30 1990-12-07 Labo Electronique Physique Procede de realisation de dispositifs semi-conducteurs du groupe iii-v sur un substrat en silicium
US4987094A (en) * 1989-06-02 1991-01-22 Bell Communications Research, Inc. Method of making a macroscopic stepped structure on a vicinally cut crystal
US5091767A (en) * 1991-03-18 1992-02-25 At&T Bell Laboratories Article comprising a lattice-mismatched semiconductor heterostructure
FR2689912A1 (fr) * 1992-04-14 1993-10-15 Centre Nat Rech Scient Procédé de réalisation d'un réseau de discontinuités à une ou deux dimensions à la surface d'un substrat cristallin ou dans une structure complexe comportant un tel substrat.
US5443685A (en) * 1993-11-01 1995-08-22 At&T Corp. Composition and method for off-axis growth sites on nonpolar substrates
US5833749A (en) * 1995-01-19 1998-11-10 Nippon Steel Corporation Compound semiconductor substrate and process of producing same
US6333208B1 (en) * 1999-07-13 2001-12-25 Li Chiung-Tung Robust manufacturing method for making a III-V compound semiconductor device by misaligned wafer bonding
US6273949B1 (en) * 1999-09-10 2001-08-14 The Board Of Trustees Of The Leland Stanford Junior University Method for fabricating orientation-patterned gallium arsenide seeding structures
JP2001217456A (ja) * 2000-02-03 2001-08-10 Sharp Corp 窒化ガリウム系化合物半導体発光素子
US6404027B1 (en) * 2000-02-07 2002-06-11 Agere Systems Guardian Corp. High dielectric constant gate oxides for silicon-based devices
US6872252B2 (en) 2002-03-06 2005-03-29 Agilent Technologies, Inc. Lead-based perovskite buffer for forming indium phosphide on silicon
US20070044832A1 (en) * 2005-08-25 2007-03-01 Fritzemeier Leslie G Photovoltaic template
US8144441B2 (en) 2006-08-30 2012-03-27 Triquint Semiconductor, Inc. Electrostatic discharge protection circuit for compound semiconductor devices and circuits
KR100793336B1 (ko) * 2006-11-17 2008-01-11 삼성전기주식회사 발광 트랜지스터
US20090114274A1 (en) * 2007-11-02 2009-05-07 Fritzemeier Leslie G Crystalline thin-film photovoltaic structures
US8236603B1 (en) 2008-09-04 2012-08-07 Solexant Corp. Polycrystalline semiconductor layers and methods for forming the same
US8415187B2 (en) 2009-01-28 2013-04-09 Solexant Corporation Large-grain crystalline thin-film structures and devices and methods for forming the same
CN113823628A (zh) * 2021-08-27 2021-12-21 深圳市汇芯通信技术有限公司 一种集成芯片及其制作方法
CN113782529A (zh) * 2021-08-27 2021-12-10 深圳市汇芯通信技术有限公司 一种集成芯片及其制作方法和集成电路

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3476592A (en) * 1966-01-14 1969-11-04 Ibm Method for producing improved epitaxial films
NL171309C (nl) * 1970-03-02 1983-03-01 Hitachi Ltd Werkwijze voor de vervaardiging van een halfgeleiderlichaam, waarbij een laag van siliciumdioxyde wordt gevormd op een oppervlak van een monokristallijn lichaam van silicium.
JPS5922320A (ja) * 1982-07-29 1984-02-04 Nec Corp 高純度３−５族半導体の気相成長方法
JPS5922319A (ja) * 1982-07-29 1984-02-04 Nec Corp ３−５族半導体の気相成長方法

Also Published As

Publication number Publication date
CA1299068C (en) 1992-04-21
EP0232082A3 (en) 1988-10-12
EP0232082A2 (de) 1987-08-12
EP0232082B1 (de) 1992-04-01
US4707216A (en) 1987-11-17
JPS62183509A (ja) 1987-08-11
JP2510859B2 (ja) 1996-06-26

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee