DE3718469A1 - Synchrones fifo - register - Google Patents

Synchrones fifo - register

Info

Publication number
DE3718469A1
DE3718469A1 DE19873718469 DE3718469A DE3718469A1 DE 3718469 A1 DE3718469 A1 DE 3718469A1 DE 19873718469 DE19873718469 DE 19873718469 DE 3718469 A DE3718469 A DE 3718469A DE 3718469 A1 DE3718469 A1 DE 3718469A1
Authority
DE
Germany
Prior art keywords
signal
write command
flip
fifo register
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE19873718469
Other languages
German (de)
English (en)
Other versions
DE3718469C2 (enrdf_load_stackoverflow
Inventor
Mathias Hofmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens Schweiz AG
Original Assignee
Siemens Albis AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Albis AG filed Critical Siemens Albis AG
Publication of DE3718469A1 publication Critical patent/DE3718469A1/de
Application granted granted Critical
Publication of DE3718469C2 publication Critical patent/DE3718469C2/de
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/08—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations, the intermediate ones not being accessible for either enqueue or dequeue operations, e.g. using a shift register

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Shift Register Type Memory (AREA)
DE19873718469 1986-06-16 1987-06-02 Synchrones fifo - register Granted DE3718469A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH2418/86A CH671476A5 (enrdf_load_stackoverflow) 1986-06-16 1986-06-16

Publications (2)

Publication Number Publication Date
DE3718469A1 true DE3718469A1 (de) 1988-01-14
DE3718469C2 DE3718469C2 (enrdf_load_stackoverflow) 1989-06-22

Family

ID=4233345

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19873718469 Granted DE3718469A1 (de) 1986-06-16 1987-06-02 Synchrones fifo - register

Country Status (3)

Country Link
CH (1) CH671476A5 (enrdf_load_stackoverflow)
DE (1) DE3718469A1 (enrdf_load_stackoverflow)
NO (1) NO170244C (enrdf_load_stackoverflow)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2515226A1 (en) * 2011-04-21 2012-10-24 STMicroelectronics SA An arrangement

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4314361A (en) * 1977-12-12 1982-02-02 U.S. Philips Corporation Data buffer memory of the first-in, first-out type comprising a fixed input and a variable output

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4314361A (en) * 1977-12-12 1982-02-02 U.S. Philips Corporation Data buffer memory of the first-in, first-out type comprising a fixed input and a variable output

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2515226A1 (en) * 2011-04-21 2012-10-24 STMicroelectronics SA An arrangement

Also Published As

Publication number Publication date
CH671476A5 (enrdf_load_stackoverflow) 1989-08-31
NO170244C (no) 1992-09-23
NO872467L (no) 1987-12-17
NO170244B (no) 1992-06-15
NO872467D0 (no) 1987-06-12
DE3718469C2 (enrdf_load_stackoverflow) 1989-06-22

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
D2 Grant after examination
8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Free format text: DERZEIT KEIN VERTRETER BESTELLT

8328 Change in the person/name/address of the agent

Free format text: FUCHS, F., DR.-ING., PAT.-ANW., 8000 MUENCHEN

8339 Ceased/non-payment of the annual fee