DE3688627T2 - Verfahren zum herstellen eines musters in einer metallschicht. - Google Patents

Verfahren zum herstellen eines musters in einer metallschicht.

Info

Publication number
DE3688627T2
DE3688627T2 DE86105370T DE3688627T DE3688627T2 DE 3688627 T2 DE3688627 T2 DE 3688627T2 DE 86105370 T DE86105370 T DE 86105370T DE 3688627 T DE3688627 T DE 3688627T DE 3688627 T2 DE3688627 T2 DE 3688627T2
Authority
DE
Germany
Prior art keywords
pattern
producing
metal layer
metal
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE86105370T
Other languages
English (en)
Other versions
DE3688627D1 (de
Inventor
Kunihiko Kanazawa
Masaru Kazumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Application granted granted Critical
Publication of DE3688627D1 publication Critical patent/DE3688627D1/de
Publication of DE3688627T2 publication Critical patent/DE3688627T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0137—Materials
    • H05K2201/0175—Inorganic, non-metallic layer, e.g. resist or dielectric for printed capacitor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0317—Thin film conductor layer; Thin film passive component
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05—Patterning and lithography; Masks; Details of resist
    • H05K2203/0562—Details of resist
    • H05K2203/0585—Second resist used as mask for selective stripping of first resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/09—Treatments involving charged particles
    • H05K2203/095—Plasma, e.g. for treating a substrate to improve adhesion with a conductor or for cleaning holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0041—Etching of the substrate by chemical or physical means by plasma etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/388—Improvement of the adhesion between the insulating substrate and the metal by the use of a metallic or inorganic thin film adhesion layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Electrodes Of Semiconductors (AREA)
DE86105370T 1985-04-19 1986-04-18 Verfahren zum herstellen eines musters in einer metallschicht. Expired - Fee Related DE3688627T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60084913A JPS61242044A (ja) 1985-04-19 1985-04-19 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE3688627D1 DE3688627D1 (de) 1993-08-05
DE3688627T2 true DE3688627T2 (de) 1993-11-04

Family

ID=13843962

Family Applications (1)

Application Number Title Priority Date Filing Date
DE86105370T Expired - Fee Related DE3688627T2 (de) 1985-04-19 1986-04-18 Verfahren zum herstellen eines musters in einer metallschicht.

Country Status (4)

Country Link
US (1) US4747909A (de)
EP (1) EP0199300B1 (de)
JP (1) JPS61242044A (de)
DE (1) DE3688627T2 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1184535B (it) * 1985-05-03 1987-10-28 Gte Telecom Spa Processo di ricavo di linee in film sottile
JPS63124446A (ja) * 1986-11-06 1988-05-27 インタ−ナショナル・ビジネス・マシ−ンズ・コ−ポレ−シヨン 接続孔形成方法
US4964945A (en) * 1988-12-09 1990-10-23 Minnesota Mining And Manufacturing Company Lift off patterning process on a flexible substrate
US5169494A (en) * 1989-03-27 1992-12-08 Matsushita Electric Industrial Co., Ltd. Fine pattern forming method
JP3041972B2 (ja) * 1991-01-10 2000-05-15 富士通株式会社 半導体装置の製造方法
KR100272739B1 (ko) * 1994-05-13 2000-11-15 기타지마 요시토시 다층 프린트 배선판과 그 제조방법 및, 전사용 원판과 그 제조방법
US6378199B1 (en) 1994-05-13 2002-04-30 Dai Nippon Printing Co., Ltd. Multi-layer printed-wiring board process for producing
US5888852A (en) * 1996-03-01 1999-03-30 Matsushita Electric Industrial Co., Ltd. Method for forming semiconductor microstructure, semiconductor device fabricated using this method, method for fabricating resonance tunneling device, and resonance tunnel device fabricated by this method
KR100430664B1 (ko) 1997-10-03 2004-06-16 가부시끼가이샤 히다치 세이사꾸쇼 가스방전형표시장치의제조방법
JP2010278333A (ja) * 2009-05-29 2010-12-09 Furukawa Electric Co Ltd:The 半導体装置およびその製造方法
CN107910452B (zh) * 2017-12-06 2021-03-19 京东方科技集团股份有限公司 显示面板的封装方法、显示面板以及显示装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
US4362598A (en) * 1981-10-26 1982-12-07 General Electric Company Method of patterning a thick resist layer of polymeric plastic
DE3275447D1 (en) * 1982-07-03 1987-03-19 Ibm Deutschland Process for the formation of grooves having essentially vertical lateral silicium walls by reactive ion etching
US4428796A (en) * 1982-08-02 1984-01-31 Fairchild Camera And Instrument Corporation Adhesion bond-breaking of lift-off regions on semiconductor structures
US4498952A (en) * 1982-09-17 1985-02-12 Condesin, Inc. Batch fabrication procedure for manufacture of arrays of field emitted electron beams with integral self-aligned optical lense in microguns

Also Published As

Publication number Publication date
EP0199300A2 (de) 1986-10-29
JPS61242044A (ja) 1986-10-28
EP0199300B1 (de) 1993-06-30
DE3688627D1 (de) 1993-08-05
US4747909A (en) 1988-05-31
EP0199300A3 (en) 1988-11-23

Similar Documents

Publication Publication Date Title
DE3768912D1 (de) Verfahren zum herstellen eines verbundwerkstoffgegenstandes.
DE3685970D1 (de) Verfahren zum herstellen eines halbleiterbauelements.
DE3484481D1 (de) Verfahren zum herstellen eines handschuhs.
DE3584071D1 (de) Verfahren zum aufrauhen einer flaeche.
DE69133549D1 (de) Verfahren zum Herstellen eines Metallkontaktes
DE3686453T2 (de) Verfahren zum herstellen einer duennen halbleiterschicht.
DE3671580D1 (de) Verfahren zum herstellen eines mehrschicht-keramiksubstrats.
DE3586732T2 (de) Verfahren zum herstellen einer dreidimentionaler halbleiteranordung.
DE3779672T2 (de) Verfahren zum herstellen einer monokristallinen halbleiterschicht.
DE3581626D1 (de) Photochemisches verfahren zum behandeln einer substratoberflaeche.
DE3674456D1 (de) Verfahren zum schuetzen einer metalloberflaeche.
DE3679758D1 (de) Verfahren zum herstellen eines supraleitenden hohlraumes.
DE3576016D1 (de) Verfahren zum herstellen eines polysilicium-widerstandes in einer "polyzid"-leitung.
DE3578729D1 (de) Verfahren zur bildung eines leitermusters.
DE3484677D1 (de) Verfahren zum herstellen von einem muster mit feinen zwischenraeumen.
DE3675706D1 (de) Verfahren zum spanabhebenden bearbeiten der oberflaeche eines nockens.
DE3579770D1 (de) Verfahren zum herstellen eines eines verstaerkungsbauteils.
DE3684202D1 (de) Verfahren zum herstellen einer passivierungsschicht.
DE3688627T2 (de) Verfahren zum herstellen eines musters in einer metallschicht.
DE3675038D1 (de) Verfahren zum herstellen eines einzelchip-mikrocomputers.
DE3877601T2 (de) Verfahren zum herstellen eines supraleitenden drahtes.
DE3584191D1 (de) Verfahren zum herstellen von durchgangsleitungen in einer planaren struktur.
DE3580335D1 (de) Verfahren zum herstellen einer halbleiterstruktur.
AT388523B (de) Verfahren zum herstellen eines sinterkoerpers mit wenigstens einer molybdaenhaltigen verschleissschicht
DE3668580D1 (de) Verfahren zum herstellen eines lagerteils.

Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD., KADOMA,

8339 Ceased/non-payment of the annual fee