DE3584191D1 - Verfahren zum herstellen von durchgangsleitungen in einer planaren struktur. - Google Patents
Verfahren zum herstellen von durchgangsleitungen in einer planaren struktur.Info
- Publication number
- DE3584191D1 DE3584191D1 DE8585107402T DE3584191T DE3584191D1 DE 3584191 D1 DE3584191 D1 DE 3584191D1 DE 8585107402 T DE8585107402 T DE 8585107402T DE 3584191 T DE3584191 T DE 3584191T DE 3584191 D1 DE3584191 D1 DE 3584191D1
- Authority
- DE
- Germany
- Prior art keywords
- throughpipes
- producing
- planar structure
- planar
- producing throughpipes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0017—Etching of the substrate by chemical or physical means
- H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
- H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/096—Vertically aligned vias, holes or stacked vias
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09845—Stepped hole, via, edge, bump or conductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
- H05K2203/0557—Non-printed masks
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
- H05K3/4667—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Optics & Photonics (AREA)
- Ceramic Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US62358484A | 1984-06-22 | 1984-06-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3584191D1 true DE3584191D1 (de) | 1991-10-31 |
Family
ID=24498630
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8585107402T Expired - Fee Related DE3584191D1 (de) | 1984-06-22 | 1985-06-15 | Verfahren zum herstellen von durchgangsleitungen in einer planaren struktur. |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0165575B1 (de) |
JP (1) | JPS6112054A (de) |
DE (1) | DE3584191D1 (de) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62213147A (ja) * | 1986-03-13 | 1987-09-19 | Fujitsu Ltd | 積層回路基板の製造方法 |
US5038252A (en) * | 1989-01-26 | 1991-08-06 | Teradyne, Inc. | Printed circuit boards with improved electrical current control |
JPH05190356A (ja) * | 1992-01-10 | 1993-07-30 | Toshiba Corp | 高電圧導体を有する電気機器 |
KR0127666B1 (ko) * | 1992-11-25 | 1997-12-30 | 모리시다 요이찌 | 세라믹전자부품 및 그 제조방법 |
US5904499A (en) * | 1994-12-22 | 1999-05-18 | Pace; Benedict G | Package for power semiconductor chips |
JP2001523390A (ja) * | 1994-12-22 | 2001-11-20 | ベネディクト・ジー・ペース | 反転型のチップが接合された高い実装効率を有するモジュール |
US6614110B1 (en) | 1994-12-22 | 2003-09-02 | Benedict G Pace | Module with bumps for connection and support |
US5868950A (en) * | 1996-11-08 | 1999-02-09 | W. L. Gore & Associates, Inc. | Method to correct astigmatism of fourth yag to enable formation of sub 25 micron micro-vias using masking techniques |
US6181219B1 (en) | 1998-12-02 | 2001-01-30 | Teradyne, Inc. | Printed circuit board and method for fabricating such board |
US7608789B2 (en) * | 2004-08-12 | 2009-10-27 | Epcos Ag | Component arrangement provided with a carrier substrate |
US7999192B2 (en) | 2007-03-14 | 2011-08-16 | Amphenol Corporation | Adjacent plated through holes with staggered couplings for crosstalk reduction in high speed printed circuit boards |
DE102009029485A1 (de) | 2009-09-15 | 2011-03-24 | Robert Bosch Gmbh | Verfahren zur Herstellung eines Keramikbauteils, Keramikbauteil und Bauteilanordnung |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3410979A (en) * | 1964-05-28 | 1968-11-12 | Burroughs Corp | Method and apparatus for drilling holes by means of a focused laser beam |
US3726002A (en) * | 1971-08-27 | 1973-04-10 | Ibm | Process for forming a multi-layer glass-metal module adaptable for integral mounting to a dissimilar refractory substrate |
JPS4985557A (de) * | 1972-12-22 | 1974-08-16 | ||
JPS50130370A (de) * | 1974-04-01 | 1975-10-15 | ||
FR2296988A1 (fr) * | 1974-12-31 | 1976-07-30 | Ibm France | Perfectionnement aux procedes de fabrication d'un module de circuits multicouches en ceramique |
JPS545796A (en) * | 1977-06-15 | 1979-01-17 | Hitachi Ltd | Automatic depositing apparatus |
JPS55162296A (en) * | 1979-06-01 | 1980-12-17 | Matsushita Electric Ind Co Ltd | Through hole printing method |
US4430365A (en) * | 1982-07-22 | 1984-02-07 | International Business Machines Corporation | Method for forming conductive lines and vias |
-
1985
- 1985-04-16 JP JP60079457A patent/JPS6112054A/ja active Granted
- 1985-06-15 DE DE8585107402T patent/DE3584191D1/de not_active Expired - Fee Related
- 1985-06-15 EP EP19850107402 patent/EP0165575B1/de not_active Expired
Also Published As
Publication number | Publication date |
---|---|
EP0165575A3 (en) | 1987-01-14 |
JPS6112054A (ja) | 1986-01-20 |
JPH0516185B2 (de) | 1993-03-03 |
EP0165575B1 (de) | 1991-09-25 |
EP0165575A2 (de) | 1985-12-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |