DE3687666T2 - Verzweigungssteuerung in einem dreiphasen-pipeline-signalprozessor. - Google Patents

Verzweigungssteuerung in einem dreiphasen-pipeline-signalprozessor.

Info

Publication number
DE3687666T2
DE3687666T2 DE8686103207T DE3687666T DE3687666T2 DE 3687666 T2 DE3687666 T2 DE 3687666T2 DE 8686103207 T DE8686103207 T DE 8686103207T DE 3687666 T DE3687666 T DE 3687666T DE 3687666 T2 DE3687666 T2 DE 3687666T2
Authority
DE
Germany
Prior art keywords
signal processor
branch control
phase pipeline
pipeline signal
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8686103207T
Other languages
English (en)
Other versions
DE3687666D1 (de
Inventor
Larry Donald Larsen
Daniel J Esteban
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3687666D1 publication Critical patent/DE3687666D1/de
Publication of DE3687666T2 publication Critical patent/DE3687666T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30061—Multi-way branch instructions, e.g. CASE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Mining & Analysis (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Algebra (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
DE8686103207T 1985-04-15 1986-03-11 Verzweigungssteuerung in einem dreiphasen-pipeline-signalprozessor. Expired - Lifetime DE3687666T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US72359485A 1985-04-15 1985-04-15

Publications (2)

Publication Number Publication Date
DE3687666D1 DE3687666D1 (de) 1993-03-18
DE3687666T2 true DE3687666T2 (de) 1993-08-12

Family

ID=24906907

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8686103207T Expired - Lifetime DE3687666T2 (de) 1985-04-15 1986-03-11 Verzweigungssteuerung in einem dreiphasen-pipeline-signalprozessor.

Country Status (5)

Country Link
US (1) US5081574A (de)
EP (1) EP0198214B1 (de)
JP (1) JPS61248135A (de)
CA (1) CA1250667A (de)
DE (1) DE3687666T2 (de)

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DE3856299T2 (de) * 1987-11-12 1999-07-01 Matsushita Electric Ind Co Ltd Verarbeitungssystem für Verzweigungsbefehle
JP2752076B2 (ja) * 1988-02-23 1998-05-18 株式会社東芝 プログラマブル・コントローラ
IL92605A0 (en) * 1988-12-19 1990-08-31 Bull Hn Information Syst Production line method and apparatus for high performance instruction execution
EP0376258B1 (de) * 1988-12-27 1999-03-03 Fujitsu Limited Steuerungssystem und -verfahren zum Instruction Fetch
US5617574A (en) * 1989-05-04 1997-04-01 Texas Instruments Incorporated Devices, systems and methods for conditional instructions
US5652910A (en) * 1989-05-04 1997-07-29 Texas Instruments Incorporated Devices and systems with conditional instructions
US5155809A (en) * 1989-05-17 1992-10-13 International Business Machines Corp. Uncoupling a central processing unit from its associated hardware for interaction with data handling apparatus alien to the operating system controlling said unit and hardware
US5150468A (en) * 1989-06-30 1992-09-22 Bull Hn Information Systems Inc. State controlled instruction logic management apparatus included in a pipelined processing unit
JP2680899B2 (ja) * 1989-08-28 1997-11-19 日本電気株式会社 情報処理装置及びその制御方法
US5471593A (en) * 1989-12-11 1995-11-28 Branigin; Michael H. Computer processor with an efficient means of executing many instructions simultaneously
JPH0437927A (ja) * 1990-06-01 1992-02-07 Sony Corp プロセッサの処理方法
CA2045798A1 (en) * 1990-06-29 1991-12-30 Rebecca L. Stamm Conversion of internal processor register commands to i/o space addresses
JP2834862B2 (ja) * 1990-07-13 1998-12-14 松下電器産業株式会社 プロセッサ
US5175853A (en) * 1990-10-09 1992-12-29 Intel Corporation Transparent system interrupt
JPH04260929A (ja) * 1991-01-21 1992-09-16 Mitsubishi Electric Corp データ処理装置
US5287467A (en) * 1991-04-18 1994-02-15 International Business Machines Corporation Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit
JPH05167395A (ja) * 1991-12-18 1993-07-02 Pioneer Video Corp ディジタル信号プロセッサの係数データ変更処理方式
US5434986A (en) * 1992-01-09 1995-07-18 Unisys Corporation Interdependency control of pipelined instruction processor using comparing result of two index registers of skip instruction and next sequential instruction
US5353419A (en) * 1992-01-09 1994-10-04 Trustees Of The University Of Pennsylvania Memory-side driven anticipatory instruction transfer interface with processor-side instruction selection
US6279116B1 (en) 1992-10-02 2001-08-21 Samsung Electronics Co., Ltd. Synchronous dynamic random access memory devices that utilize clock masking signals to control internal clock signal generation
US5752073A (en) * 1993-01-06 1998-05-12 Cagent Technologies, Inc. Digital signal processor architecture
AU3437293A (en) * 1993-01-06 1994-08-15 3Do Company, The Digital signal processor architecture
JP3452655B2 (ja) * 1993-09-27 2003-09-29 株式会社日立製作所 ディジタル信号処理プロセッサおよびそれを用いて命令を実行する方法
US5706459A (en) * 1994-01-06 1998-01-06 Fujitsu Limited Processor having a variable number of stages in a pipeline
US5701450A (en) * 1994-02-25 1997-12-23 Seagate Technology, Inc. System including ATA sequencer microprocessor which executes sequencer instructions to handle plurality of real-time events allowing to perform all operations without local microprocessor intervention
US5442789A (en) * 1994-03-31 1995-08-15 International Business Machines Corporation System and method for efficiently loading and removing selected functions on digital signal processors without interrupting execution of other functions on the digital signal processors
US5659722A (en) * 1994-04-28 1997-08-19 International Business Machines Corporation Multiple condition code branching system in a multi-processor environment
US5905881A (en) * 1995-11-30 1999-05-18 Unisys Corporation Delayed state writes for an instruction processor
US5924128A (en) * 1996-06-20 1999-07-13 International Business Machines Corporation Pseudo zero cycle address generator and fast memory access
US5867699A (en) * 1996-07-25 1999-02-02 Unisys Corporation Instruction flow control for an instruction processor
JP2000507016A (ja) * 1996-11-04 2000-06-06 フィリップス エレクトロニクス ネムローゼ フェンノートシャップ メモリの命令を読み出す処理装置
US6044460A (en) * 1998-01-16 2000-03-28 Lsi Logic Corporation System and method for PC-relative address generation in a microprocessor with a pipeline architecture
US6314493B1 (en) 1998-02-03 2001-11-06 International Business Machines Corporation Branch history cache
JP3097648B2 (ja) * 1998-02-04 2000-10-10 日本電気株式会社 情報処理装置及び情報処理方法
US7505974B2 (en) 1999-02-12 2009-03-17 Gropper Robert L Auto update utility for digital address books
US6883000B1 (en) * 1999-02-12 2005-04-19 Robert L. Gropper Business card and contact management system
US6633969B1 (en) 2000-08-11 2003-10-14 Lsi Logic Corporation Instruction translation system and method achieving single-cycle translation of variable-length MIPS16 instructions
US7761697B1 (en) * 2005-07-13 2010-07-20 Nvidia Corporation Processing an indirect branch instruction in a SIMD architecture
US7543136B1 (en) 2005-07-13 2009-06-02 Nvidia Corporation System and method for managing divergent threads using synchronization tokens and program instructions that include set-synchronization bits
US8312254B2 (en) 2008-03-24 2012-11-13 Nvidia Corporation Indirect function call instructions in a synchronous parallel thread processor
US9182984B2 (en) * 2012-06-15 2015-11-10 International Business Machines Corporation Local clearing control

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3875391A (en) 1973-11-02 1975-04-01 Raytheon Co Pipeline signal processor
JPS6024985B2 (ja) 1978-08-31 1985-06-15 富士通株式会社 デ−タ処理方式
JPS5840214B2 (ja) 1979-06-26 1983-09-03 株式会社東芝 計算機システム
US4443848A (en) * 1979-09-10 1984-04-17 Nixdorf Computer Corporation Two-level priority circuit
JPS56129950A (en) * 1980-03-07 1981-10-12 Hitachi Ltd Information processor
US4399507A (en) * 1981-06-30 1983-08-16 Ibm Corporation Instruction address stack in the data memory of an instruction-pipelined processor
US4532589A (en) * 1981-12-02 1985-07-30 Hitachi, Ltd. Digital data processor with two operation units
WO1984000833A1 (en) * 1982-08-23 1984-03-01 Western Electric Co Pre-execution next address calculating mechanism
US4604691A (en) * 1982-09-07 1986-08-05 Nippon Electric Co., Ltd. Data processing system having branch instruction prefetching performance
JPS6051948A (ja) * 1983-08-31 1985-03-23 Hitachi Ltd 情報処理装置
BR8407165A (pt) * 1983-11-11 1985-10-08 Fujitsu Ltd Sistema de controle de canalizacao
JPH0789319B2 (ja) * 1985-04-22 1995-09-27 株式会社日立製作所 デ−タ処理装置における先行制御装置
US4777587A (en) * 1985-08-30 1988-10-11 Advanced Micro Devices, Inc. System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses

Also Published As

Publication number Publication date
JPS61248135A (ja) 1986-11-05
EP0198214A3 (en) 1989-12-06
US5081574A (en) 1992-01-14
EP0198214A2 (de) 1986-10-22
DE3687666D1 (de) 1993-03-18
EP0198214B1 (de) 1993-02-03
CA1250667A (en) 1989-02-28

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