DE3681733D1 - Datenprozessorbefehlssystem mit unterbrechungsfaehigkeit, die befehlsvorausholungsneuorientierung verwendet. - Google Patents

Datenprozessorbefehlssystem mit unterbrechungsfaehigkeit, die befehlsvorausholungsneuorientierung verwendet.

Info

Publication number
DE3681733D1
DE3681733D1 DE8787900384T DE3681733T DE3681733D1 DE 3681733 D1 DE3681733 D1 DE 3681733D1 DE 8787900384 T DE8787900384 T DE 8787900384T DE 3681733 T DE3681733 T DE 3681733T DE 3681733 D1 DE3681733 D1 DE 3681733D1
Authority
DE
Germany
Prior art keywords
command
interruptability
preproduction
reorientation
data processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8787900384T
Other languages
German (de)
English (en)
Inventor
L Kloker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE3681733D1 publication Critical patent/DE3681733D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
DE8787900384T 1985-11-27 1986-11-10 Datenprozessorbefehlssystem mit unterbrechungsfaehigkeit, die befehlsvorausholungsneuorientierung verwendet. Expired - Lifetime DE3681733D1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US06/802,491 US4709324A (en) 1985-11-27 1985-11-27 Data processor control unit having an interrupt service using instruction prefetch redirection
PCT/US1986/002466 WO1987003394A1 (en) 1985-11-27 1986-11-10 A data processor control unit having an interrupt service using instruction prefetch redirection

Publications (1)

Publication Number Publication Date
DE3681733D1 true DE3681733D1 (de) 1991-10-31

Family

ID=25183841

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787900384T Expired - Lifetime DE3681733D1 (de) 1985-11-27 1986-11-10 Datenprozessorbefehlssystem mit unterbrechungsfaehigkeit, die befehlsvorausholungsneuorientierung verwendet.

Country Status (13)

Country Link
US (1) US4709324A (zh)
EP (1) EP0247175B1 (zh)
JP (1) JPH083791B2 (zh)
KR (1) KR940009100B1 (zh)
CN (1) CN1009396B (zh)
AU (1) AU6779687A (zh)
CA (1) CA1265873A (zh)
DE (1) DE3681733D1 (zh)
FI (1) FI90804C (zh)
HK (1) HK5294A (zh)
IL (1) IL80499A (zh)
SG (1) SG130093G (zh)
WO (1) WO1987003394A1 (zh)

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JP3230262B2 (ja) * 1992-01-24 2001-11-19 ソニー株式会社 電子装置及びその固定情報修正方法
US5805902A (en) * 1993-07-02 1998-09-08 Elonex I.P. Holdings, Ltd. Structure and method for issuing interrupt requests as addresses and for decoding the addresses issued as interrupt requests
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US5475822A (en) * 1993-11-15 1995-12-12 Motorola, Inc. Data processing system for resuming instruction execution after an interrupt and method therefor
JPH07244649A (ja) * 1994-03-08 1995-09-19 Fujitsu Ltd 割込処理分散方式
US5889973A (en) * 1995-03-31 1999-03-30 Motorola, Inc. Method and apparatus for selectively controlling interrupt latency in a data processing system
US6052801A (en) * 1995-05-10 2000-04-18 Intel Corporation Method and apparatus for providing breakpoints on a selectable address range
US5659679A (en) * 1995-05-30 1997-08-19 Intel Corporation Method and apparatus for providing breakpoints on taken jumps and for providing software profiling in a computer system
US5621886A (en) * 1995-06-19 1997-04-15 Intel Corporation Method and apparatus for providing efficient software debugging
US5740413A (en) * 1995-06-19 1998-04-14 Intel Corporation Method and apparatus for providing address breakpoints, branch breakpoints, and single stepping
US5687339A (en) * 1995-09-14 1997-11-11 Elan Microelectronics Corp. Pre-reading and pre-decoding of instructions of a microprocessor within single cycle
US5954819A (en) * 1996-05-17 1999-09-21 National Semiconductor Corporation Power conservation method and apparatus activated by detecting programmable signals indicative of system inactivity and excluding prefetched signals
US6785803B1 (en) * 1996-11-13 2004-08-31 Intel Corporation Processor including replay queue to break livelocks
US5907712A (en) * 1997-05-30 1999-05-25 International Business Machines Corporation Method for reducing processor interrupt processing time by transferring predetermined interrupt status to a system memory for eliminating PIO reads from the interrupt handler
US5905880A (en) * 1997-09-29 1999-05-18 Microchip Technology Incorporated Robust multiple word instruction and method therefor
US5901309A (en) * 1997-10-07 1999-05-04 Telefonaktiebolaget Lm Ericsson (Publ) Method for improved interrupt handling within a microprocessor
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US6275924B1 (en) * 1998-09-15 2001-08-14 Texas Instruments Incorporated System for buffering instructions in a processor by reissuing instruction fetches during decoder stall time
US7401205B1 (en) * 1999-08-13 2008-07-15 Mips Technologies, Inc. High performance RISC instruction set digital signal processor having circular buffer and looping controls
US6889279B2 (en) * 2000-12-11 2005-05-03 Cadence Design Systems, Inc. Pre-stored vector interrupt handling system and method
US6937084B2 (en) 2001-06-01 2005-08-30 Microchip Technology Incorporated Processor with dual-deadtime pulse width modulation generator
US20020184566A1 (en) 2001-06-01 2002-12-05 Michael Catherwood Register pointer trap
US7003543B2 (en) 2001-06-01 2006-02-21 Microchip Technology Incorporated Sticky z bit
US6952711B2 (en) 2001-06-01 2005-10-04 Microchip Technology Incorporated Maximally negative signed fractional number multiplication
US7467178B2 (en) 2001-06-01 2008-12-16 Microchip Technology Incorporated Dual mode arithmetic saturation processing
US6985986B2 (en) 2001-06-01 2006-01-10 Microchip Technology Incorporated Variable cycle interrupt disabling
US6976158B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Repeat instruction with interrupt
US6934728B2 (en) 2001-06-01 2005-08-23 Microchip Technology Incorporated Euclidean distance instructions
US7007172B2 (en) 2001-06-01 2006-02-28 Microchip Technology Incorporated Modified Harvard architecture processor having data memory space mapped to program memory space with erroneous execution protection
US6975679B2 (en) 2001-06-01 2005-12-13 Microchip Technology Incorporated Configuration fuses for setting PWM options
US7020788B2 (en) 2001-06-01 2006-03-28 Microchip Technology Incorporated Reduced power option
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US7200719B2 (en) * 2003-07-31 2007-04-03 Freescale Semiconductor, Inc. Prefetch control in a data processing system
JP4247132B2 (ja) 2004-01-29 2009-04-02 株式会社ルネサステクノロジ 情報処理装置
CN102141904B (zh) * 2011-03-31 2014-02-12 杭州中天微系统有限公司 支持中断屏蔽指令的数据处理器
WO2013095532A1 (en) * 2011-12-22 2013-06-27 Intel Corporation Interrupt return instruction with embedded interrupt service functionality
CN111190658B (zh) * 2020-01-08 2023-02-28 乐鑫信息科技（上海）股份有限公司 一种基于片内执行且在不具有MMU的SoC片上支持应用程序动态加载的系统

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Also Published As

Publication number Publication date
FI90804B (fi) 1993-12-15
EP0247175A1 (en) 1987-12-02
WO1987003394A1 (en) 1987-06-04
CN86107934A (zh) 1987-08-12
JPH083791B2 (ja) 1996-01-17
JPS63501454A (ja) 1988-06-02
IL80499A0 (en) 1987-02-27
US4709324A (en) 1987-11-24
FI873030A (fi) 1987-07-08
EP0247175A4 (en) 1988-03-22
EP0247175B1 (en) 1991-09-25
SG130093G (en) 1994-02-25
CN1009396B (zh) 1990-08-29
KR880700969A (ko) 1988-04-13
FI90804C (fi) 1994-03-25
FI873030A0 (fi) 1987-07-08
KR940009100B1 (ko) 1994-09-29
CA1265873A (en) 1990-02-13
IL80499A (en) 1990-06-10
AU6779687A (en) 1987-07-01
HK5294A (en) 1994-01-28

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: FREESCALE SEMICONDUCTOR, INC. (N.D.GES.D. STAATES