DE3620982A1 - Ein-befehl, mehrfach-datenstrom (simd) computersystem - Google Patents

Ein-befehl, mehrfach-datenstrom (simd) computersystem

Info

Publication number
DE3620982A1
DE3620982A1 DE19863620982 DE3620982A DE3620982A1 DE 3620982 A1 DE3620982 A1 DE 3620982A1 DE 19863620982 DE19863620982 DE 19863620982 DE 3620982 A DE3620982 A DE 3620982A DE 3620982 A1 DE3620982 A1 DE 3620982A1
Authority
DE
Germany
Prior art keywords
command
processors
instruction
test
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19863620982
Other languages
German (de)
English (en)
Inventor
Adam E Levinthal
Thomas K Porter
Thomas D S Duff
Loren C Carpenter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pixar
Original Assignee
Pixar
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pixar filed Critical Pixar
Publication of DE3620982A1 publication Critical patent/DE3620982A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G06F15/8007—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors single instruction multiple data [SIMD] multiprocessors

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Image Processing (AREA)
DE19863620982 1985-06-24 1986-06-23 Ein-befehl, mehrfach-datenstrom (simd) computersystem Withdrawn DE3620982A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US74840985A 1985-06-24 1985-06-24

Publications (1)

Publication Number Publication Date
DE3620982A1 true DE3620982A1 (de) 1987-01-29

Family

ID=25009327

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19863620982 Withdrawn DE3620982A1 (de) 1985-06-24 1986-06-23 Ein-befehl, mehrfach-datenstrom (simd) computersystem

Country Status (8)

Country Link
EP (1) EP0227811A1 (enExample)
JP (1) JPS6254359A (enExample)
AU (1) AU6128486A (enExample)
CA (1) CA1267230A (enExample)
DE (1) DE3620982A1 (enExample)
FR (1) FR2583904A1 (enExample)
GB (1) GB2177526B (enExample)
WO (1) WO1987000318A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19620263B4 (de) * 1995-06-08 2006-07-27 Hewlett-Packard Development Co., L.P., Houston Datensynchronisation zwischen einer Mehrzahl von asynchronen Datenaufbereitungen

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2211638A (en) * 1987-10-27 1989-07-05 Ibm Simd array processor
GB2201015B (en) * 1987-02-10 1990-10-10 Univ Southampton Parallel processor array and array element
US5262965A (en) * 1988-10-31 1993-11-16 Bts-Broadcast Television Systems, Inc. System and method for high speed computer graphics image computation using a parallel connected, asynchronous multiprocessor ring coupled to a synchronous special purpose video processing ring
JP2578286Y2 (ja) * 1992-03-18 1998-08-06 日本精工株式会社 等速ジョイント
FR2693576B1 (fr) * 1992-07-13 1994-09-30 Texas Instruments France Système multiprocesseur à contrôle local.
AU717336B2 (en) * 1997-04-30 2000-03-23 Canon Kabushiki Kaisha Graphics processor architecture
US6366999B1 (en) * 1998-01-28 2002-04-02 Bops, Inc. Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution
JPH11246581A (ja) * 1998-02-28 1999-09-14 Tonen Corp 亜鉛−モリブデン系ジチオカルバミン酸塩誘導体、その製造方法およびそれを含有する潤滑油組成物
US6732253B1 (en) 2000-11-13 2004-05-04 Chipwrights Design, Inc. Loop handling for single instruction multiple datapath processor architectures
US6931518B1 (en) 2000-11-28 2005-08-16 Chipwrights Design, Inc. Branching around conditional processing if states of all single instruction multiple datapaths are disabled and the computer program is non-deterministic
US6970985B2 (en) 2002-07-09 2005-11-29 Bluerisc Inc. Statically speculative memory accessing
US20050114850A1 (en) 2003-10-29 2005-05-26 Saurabh Chheda Energy-focused re-compilation of executables and hardware mechanisms based on compiler-architecture interaction and compiler-inserted control
US7996671B2 (en) 2003-11-17 2011-08-09 Bluerisc Inc. Security of program executables and microprocessors based on compiler-architecture interaction
US8607209B2 (en) 2004-02-04 2013-12-10 Bluerisc Inc. Energy-focused compiler-assisted branch prediction
US7434028B2 (en) * 2004-12-15 2008-10-07 Intel Corporation Hardware stack having entries with a data portion and associated counter
US20080126766A1 (en) 2006-11-03 2008-05-29 Saurabh Chheda Securing microprocessors against information leakage and physical tampering
JP5452066B2 (ja) * 2009-04-24 2014-03-26 本田技研工業株式会社 並列計算装置
JP5358287B2 (ja) * 2009-05-19 2013-12-04 本田技研工業株式会社 並列計算装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4101960A (en) * 1977-03-29 1978-07-18 Burroughs Corporation Scientific processor
US4435758A (en) * 1980-03-10 1984-03-06 International Business Machines Corporation Method for conditional branch execution in SIMD vector processors
JPS56127266A (en) * 1980-03-10 1981-10-05 Ibm Method of executing and controlling command stream
US4574348A (en) * 1983-06-01 1986-03-04 The Boeing Company High speed digital signal processor architecture

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BARNES, George et al: The ILLIAC IV Computer. In: IEEE Trans. on Computers, Vol. C-17, No. 8, August 1968, S. 746-757 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19620263B4 (de) * 1995-06-08 2006-07-27 Hewlett-Packard Development Co., L.P., Houston Datensynchronisation zwischen einer Mehrzahl von asynchronen Datenaufbereitungen

Also Published As

Publication number Publication date
CA1267230A (en) 1990-03-27
EP0227811A1 (en) 1987-07-08
JPH031699B2 (enExample) 1991-01-11
GB8614907D0 (en) 1986-07-23
GB2177526A (en) 1987-01-21
FR2583904A1 (fr) 1986-12-26
AU6128486A (en) 1987-01-30
JPS6254359A (ja) 1987-03-10
WO1987000318A1 (en) 1987-01-15
GB2177526B (en) 1990-02-14

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Legal Events

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8139 Disposal/non-payment of the annual fee