DE3587797T2 - Transistor mit horizontaler Struktur und Verfahren zu dessen Herstellung. - Google Patents

Transistor mit horizontaler Struktur und Verfahren zu dessen Herstellung.

Info

Publication number
DE3587797T2
DE3587797T2 DE19853587797 DE3587797T DE3587797T2 DE 3587797 T2 DE3587797 T2 DE 3587797T2 DE 19853587797 DE19853587797 DE 19853587797 DE 3587797 T DE3587797 T DE 3587797T DE 3587797 T2 DE3587797 T2 DE 3587797T2
Authority
DE
Germany
Prior art keywords
island
zone
region
epitaxial
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE19853587797
Other languages
German (de)
English (en)
Other versions
DE3587797D1 (de
Inventor
James D Guillory
David B Spratt
Eldon J Zorinsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Texas Instruments Inc
Original Assignee
Texas Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Texas Instruments Inc filed Critical Texas Instruments Inc
Application granted granted Critical
Publication of DE3587797D1 publication Critical patent/DE3587797D1/de
Publication of DE3587797T2 publication Critical patent/DE3587797T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66265—Thin film bipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/735—Lateral transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281—Lateral isolation by selective oxidation of silicon

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Bipolar Integrated Circuits (AREA)
DE19853587797 1984-10-31 1985-10-14 Transistor mit horizontaler Struktur und Verfahren zu dessen Herstellung. Expired - Fee Related DE3587797T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US66694284A 1984-10-31 1984-10-31

Publications (2)

Publication Number Publication Date
DE3587797D1 DE3587797D1 (de) 1994-05-19
DE3587797T2 true DE3587797T2 (de) 1994-07-28

Family

ID=24676160

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19853587797 Expired - Fee Related DE3587797T2 (de) 1984-10-31 1985-10-14 Transistor mit horizontaler Struktur und Verfahren zu dessen Herstellung.

Country Status (4)

Country Link
EP (1) EP0180363B1 (fr)
JP (1) JPS61180481A (fr)
CN (1) CN1004594B (fr)
DE (1) DE3587797T2 (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0812865B2 (ja) * 1989-06-06 1996-02-07 株式会社東芝 バイポーラトランジスタとその製造方法
US5994739A (en) * 1990-07-02 1999-11-30 Kabushiki Kaisha Toshiba Integrated circuit device
JP3190057B2 (ja) * 1990-07-02 2001-07-16 株式会社東芝 複合集積回路装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3174777D1 (en) * 1980-10-23 1986-07-10 Fairchild Camera Instr Co Method of fabricating integrated circuit structure
EP0059264A1 (fr) * 1981-03-02 1982-09-08 Rockwell International Corporation Transistor latéral NPN avec interférence minimum due au substrat et son procédé de fabrication
EP0068073A2 (fr) * 1981-07-01 1983-01-05 Rockwell International Corporation Transistor latérale du type PNP dont le fonctionnement est influancé d'une façon minimale par le substrat et son procédé de fabrication
JPS5852817A (ja) * 1981-09-25 1983-03-29 Hitachi Ltd 半導体装置及びその製造方法
EP0144654A3 (fr) * 1983-11-03 1987-10-07 General Electric Company Dispositif semi-conducteur comportant un transistor à effet de champ à porte isolée, diélectriquement isolé

Also Published As

Publication number Publication date
JPS61180481A (ja) 1986-08-13
CN1004594B (zh) 1989-06-21
JPH0523495B2 (fr) 1993-04-02
EP0180363A2 (fr) 1986-05-07
CN85108008A (zh) 1986-05-10
DE3587797D1 (de) 1994-05-19
EP0180363B1 (fr) 1994-04-13
EP0180363A3 (en) 1987-12-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee