DE3580993D1 - Halbleiterspeicheranordnung. - Google Patents

Halbleiterspeicheranordnung.

Info

Publication number
DE3580993D1
DE3580993D1 DE8585103494T DE3580993T DE3580993D1 DE 3580993 D1 DE3580993 D1 DE 3580993D1 DE 8585103494 T DE8585103494 T DE 8585103494T DE 3580993 T DE3580993 T DE 3580993T DE 3580993 D1 DE3580993 D1 DE 3580993D1
Authority
DE
Germany
Prior art keywords
semiconductor memory
memory arrangement
arrangement
semiconductor
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE8585103494T
Other languages
German (de)
English (en)
Inventor
Kazuo Ooami
Yasuhisa Sugo
Tohru Takeshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3580993D1 publication Critical patent/DE3580993D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/414—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the bipolar type
    • G11C11/416—Read-write [R-W] circuits 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36—Data generation devices, e.g. data inverters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
DE8585103494T 1984-03-30 1985-03-26 Halbleiterspeicheranordnung. Expired - Lifetime DE3580993D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59060600A JPS60205895A (ja) 1984-03-30 1984-03-30 半導体記憶装置

Publications (1)

Publication Number Publication Date
DE3580993D1 true DE3580993D1 (de) 1991-02-07

Family

ID=13146898

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585103494T Expired - Lifetime DE3580993D1 (de) 1984-03-30 1985-03-26 Halbleiterspeicheranordnung.

Country Status (5)

Country Link
US (1) US4692900A (esLanguage)
EP (1) EP0156345B1 (esLanguage)
JP (1) JPS60205895A (esLanguage)
KR (1) KR900006220B1 (esLanguage)
DE (1) DE3580993D1 (esLanguage)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4769785A (en) * 1986-06-02 1988-09-06 Advanced Micro Devices, Inc. Writing speed of SCR-based memory cells
US5053951A (en) * 1986-12-23 1991-10-01 Bull Hn Information Systems Inc. Segment descriptor unit for performing static and dynamic address translation operations
JPH06105548B2 (ja) * 1987-02-02 1994-12-21 三菱電機株式会社 ダイナミツク形半導体記憶装置
US5249159A (en) * 1987-05-27 1993-09-28 Hitachi, Ltd. Semiconductor memory
US4858183A (en) * 1987-06-02 1989-08-15 Texas Instruments Incorporated ECL high speed semiconductor memory and method of accessing stored information therein
US4891789A (en) * 1988-03-03 1990-01-02 Bull Hn Information Systems, Inc. Surface mounted multilayer memory printed circuit board
US4866676A (en) * 1988-03-24 1989-09-12 Motorola, Inc. Testing arrangement for a DRAM with redundancy
US4845669A (en) * 1988-04-27 1989-07-04 International Business Machines Corporation Transporsable memory architecture
US5027326A (en) * 1988-11-10 1991-06-25 Dallas Semiconductor Corporation Self-timed sequential access multiport memory
US5208778A (en) * 1988-11-16 1993-05-04 Mitsubishi Denki Kabushiki Kaisha Dynamic-type semiconductor memory device operable in test mode and method of testing functions thereof
JPH03162800A (ja) * 1989-08-29 1991-07-12 Mitsubishi Electric Corp 半導体メモリ装置
US5117426A (en) * 1990-03-26 1992-05-26 Texas Instruments Incorporated Circuit, device, and method to detect voltage leakage
US5388072A (en) * 1992-04-10 1995-02-07 International Business Machines Corporation Bit line switch array for electronic computer memory
US5719890A (en) * 1995-06-01 1998-02-17 Micron Technology, Inc. Method and circuit for transferring data with dynamic parity generation and checking scheme in multi-port DRAM
US6487207B1 (en) 1997-02-26 2002-11-26 Micron Technology, Inc. Shared buffer memory architecture for asynchronous transfer mode switching and multiplexing technology
JP3110400B2 (ja) * 1998-10-30 2000-11-20 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
US6650561B2 (en) 2002-01-30 2003-11-18 International Business Machines Corporation High reliability content-addressable memory using shadow content-addressable memory
US6992939B2 (en) * 2004-01-26 2006-01-31 Micron Technology, Inc. Method and apparatus for identifying short circuits in an integrated circuit device
JP4954161B2 (ja) * 2008-08-20 2012-06-13 ルネサスエレクトロニクス株式会社 半導体記憶装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55142487A (en) * 1979-04-25 1980-11-07 Hitachi Ltd Bipolar memory circuit
JPS5630754A (en) * 1979-08-23 1981-03-27 Fujitsu Ltd Semiconductor memory device
JPS57105897A (en) * 1980-12-23 1982-07-01 Fujitsu Ltd Semiconductor storage device
JPS6047665B2 (ja) * 1981-01-29 1985-10-23 富士通株式会社 スタティック半導体メモリ

Also Published As

Publication number Publication date
JPS60205895A (ja) 1985-10-17
EP0156345B1 (en) 1991-01-02
KR850007158A (ko) 1985-10-30
US4692900A (en) 1987-09-08
KR900006220B1 (en) 1990-08-25
EP0156345A3 (en) 1988-07-27
JPH0330958B2 (esLanguage) 1991-05-01
EP0156345A2 (en) 1985-10-02

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee