DE3568098D1 - Addressing device for the delivery of address codes to a memory - Google Patents

Addressing device for the delivery of address codes to a memory

Info

Publication number
DE3568098D1
DE3568098D1 DE8585200354T DE3568098T DE3568098D1 DE 3568098 D1 DE3568098 D1 DE 3568098D1 DE 8585200354 T DE8585200354 T DE 8585200354T DE 3568098 T DE3568098 T DE 3568098T DE 3568098 D1 DE3568098 D1 DE 3568098D1
Authority
DE
Germany
Prior art keywords
delivery
memory
address codes
addressing device
addressing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585200354T
Other languages
English (en)
Inventor
Bahman Barazesh
Luc Mary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SIGNAUX PARIS FR Cie
Original Assignee
Telecommunications Radioelectriques et Telephoniques SA TRT
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telecommunications Radioelectriques et Telephoniques SA TRT filed Critical Telecommunications Radioelectriques et Telephoniques SA TRT
Application granted granted Critical
Publication of DE3568098D1 publication Critical patent/DE3568098D1/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G06F9/3552—Indexed addressing using wraparound, e.g. modulo or circular addressing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/04—Arrangements for selecting an address in a digital store using a sequential addressing device, e.g. shift register, counter

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Complex Calculations (AREA)
  • Memory System (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Filters That Use Time-Delay Elements (AREA)
  • Executing Machine-Instructions (AREA)
DE8585200354T 1984-03-13 1985-03-11 Addressing device for the delivery of address codes to a memory Expired DE3568098D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8403813A FR2561429B1 (fr) 1984-03-13 1984-03-13 Dispositif d'adressage pour fournir a une memoire des codes d'adresse

Publications (1)

Publication Number Publication Date
DE3568098D1 true DE3568098D1 (en) 1989-03-09

Family

ID=9301963

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585200354T Expired DE3568098D1 (en) 1984-03-13 1985-03-11 Addressing device for the delivery of address codes to a memory

Country Status (5)

Country Link
US (1) US4787065A (de)
EP (1) EP0155731B1 (de)
JP (1) JPH0812657B2 (de)
DE (1) DE3568098D1 (de)
FR (1) FR2561429B1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5270981A (en) * 1985-07-30 1993-12-14 Kabushiki Kaisha Toshiba Field memory device functioning as a variable stage shift register with gated feedback from its output to its input
JPS6228993A (ja) * 1985-07-30 1987-02-06 Toshiba Corp 記憶装置
CA1270338C (en) * 1985-09-11 1990-06-12 DATA PROCESSING SYSTEM FOR PROCESSING UNITS WITH DIFFERENT RATES
DE3535215A1 (de) * 1985-10-02 1987-04-02 Nixdorf Computer Ag Verfahren und schaltungsanordnung zum lesen von daten aus dem speicher einer datenverarbeitungsanlage
JPS62180427A (ja) * 1986-02-03 1987-08-07 Nec Corp プログラム制御回路
US4935867A (en) * 1986-03-04 1990-06-19 Advanced Micro Devices, Inc. Signal processor memory management unit with indirect addressing using selectable offsets and modulo values for indexed address calculations
US4912636A (en) * 1987-03-13 1990-03-27 Magar Surendar S Data processing device with multiple on chip memory buses
US5179674A (en) * 1988-07-25 1993-01-12 Digital Equipment Corporation Method and apparatus for predicting valid performance of virtual-address to physical-address translations
JPH0795269B2 (ja) * 1988-11-04 1995-10-11 富士通株式会社 命令コードのデコード装置
US5257358A (en) * 1989-04-18 1993-10-26 Nec Electronics, Inc. Method for counting the number of program instruction completed by a microprocessor
JP3046111B2 (ja) * 1991-11-08 2000-05-29 キヤノン株式会社 文字認識方法及びその装置
NL9401301A (nl) * 1994-08-11 1996-03-01 Nederland Ptt Videogeheugeninrichting.
US5825692A (en) * 1994-09-23 1998-10-20 Siemens Nixdorf Informationssysteme Aktiengesellschaft Memory system and method for simultaneously reading and writing data
JP3718046B2 (ja) * 1998-02-18 2005-11-16 ローム株式会社 アドレス発生回路
US8914612B2 (en) * 2007-10-29 2014-12-16 Conversant Intellectual Property Management Inc. Data processing with time-based memory access

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3141151A (en) * 1959-03-23 1964-07-14 Burroughs Corp Magnetic tape storage system for digital computers wherein an indication of the number of bits in a message is stored with the message
US3602901A (en) * 1969-10-31 1971-08-31 Bunko Ramo Corp The Circuit for controlling the loading and editing of information in a recirculating memory
US4016543A (en) * 1975-02-10 1977-04-05 Formation, Inc. Processor address recall system
JPS5247635A (en) * 1975-10-15 1977-04-15 Toshiba Corp Control method for transmitting informat ion
US4241416A (en) * 1977-07-01 1980-12-23 Systron-Donner Corporation Monitoring apparatus for processor controlled equipment
FR2420168B1 (fr) * 1978-03-16 1986-09-26 Ibm Dispositif de pre-traitement d'instructions dans un systeme de traitement de donnees
JPS54135352A (en) * 1978-04-12 1979-10-20 Sumida Electric Method of fixing high frequency coil
US4280199A (en) * 1979-08-03 1981-07-21 Sony Corporation Apparatus for scanning an addressable memory
JPS57114950A (en) * 1981-01-08 1982-07-17 Nippon Telegr & Teleph Corp <Ntt> Loop processing system for program controller
US4422175A (en) * 1981-06-11 1983-12-20 Racal-Vadic, Inc. Constrained adaptive equalizer
DE3123444A1 (de) * 1981-06-12 1983-01-05 Siemens AG, 1000 Berlin und 8000 München Verfahren und anordnung zum nichtfluechtigen speichern des zaehlerstandes einer elektronischen zaehlschaltung
US4462074A (en) * 1981-11-19 1984-07-24 Codex Corporation Do loop circuit
JPS58224497A (ja) * 1982-06-22 1983-12-26 Nec Corp 記憶装置
JPS5956276A (ja) * 1982-09-24 1984-03-31 Hitachi Ltd 半導体記憶装置
US4628532A (en) * 1983-07-14 1986-12-09 Scan Optics, Inc. Alphanumeric handprint recognition

Also Published As

Publication number Publication date
FR2561429B1 (fr) 1986-09-19
JPS60206317A (ja) 1985-10-17
EP0155731A1 (de) 1985-09-25
EP0155731B1 (de) 1989-02-01
US4787065A (en) 1988-11-22
JPH0812657B2 (ja) 1996-02-07
FR2561429A1 (fr) 1985-09-20

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: COMPAGNIE DES SIGNAUX, PARIS, FR

8328 Change in the person/name/address of the agent

Free format text: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUSSER, ANWALTSSOZIETAET, 80538 MUENCHEN

8339 Ceased/non-payment of the annual fee