DE3564889D1 - Process for making electrical isolation zones for components in an integrated circuit - Google Patents

Process for making electrical isolation zones for components in an integrated circuit

Info

Publication number
DE3564889D1
DE3564889D1 DE8585400627T DE3564889T DE3564889D1 DE 3564889 D1 DE3564889 D1 DE 3564889D1 DE 8585400627 T DE8585400627 T DE 8585400627T DE 3564889 T DE3564889 T DE 3564889T DE 3564889 D1 DE3564889 D1 DE 3564889D1
Authority
DE
Germany
Prior art keywords
components
integrated circuit
electrical isolation
making electrical
isolation zones
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8585400627T
Other languages
English (en)
Inventor
Daniel Bois
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Application granted granted Critical
Publication of DE3564889D1 publication Critical patent/DE3564889D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • H01L21/76235—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls trench shape altered by a local oxidation of silicon process step, e.g. trench corner rounding by LOCOS
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Element Separation (AREA)
DE8585400627T 1984-03-30 1985-03-29 Process for making electrical isolation zones for components in an integrated circuit Expired DE3564889D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR8405051A FR2562326B1 (fr) 1984-03-30 1984-03-30 Procede de fabrication de zones d'isolation electrique des composants d'un circuit integre

Publications (1)

Publication Number Publication Date
DE3564889D1 true DE3564889D1 (en) 1988-10-13

Family

ID=9302664

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8585400627T Expired DE3564889D1 (en) 1984-03-30 1985-03-29 Process for making electrical isolation zones for components in an integrated circuit

Country Status (6)

Country Link
US (1) US4679304A (de)
EP (1) EP0159931B1 (de)
JP (1) JPS61501668A (de)
DE (1) DE3564889D1 (de)
FR (1) FR2562326B1 (de)
WO (1) WO1985004516A1 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS639948A (ja) * 1986-06-30 1988-01-16 Nec Corp 半導体装置
JPH01125935A (ja) * 1987-11-11 1989-05-18 Seiko Instr & Electron Ltd 半導体装置の製造方法
US4994407A (en) * 1988-09-20 1991-02-19 Rockwell International Corporation Radiation hardened field oxides for NMOS and CMOS-bulk and process for forming
US4942137A (en) * 1989-08-14 1990-07-17 Motorola, Inc. Self-aligned trench with selective trench fill
US5051795A (en) * 1989-11-21 1991-09-24 Texas Instruments Incorporated EEPROM with trench-isolated bitlines
KR970000533B1 (ko) * 1990-12-20 1997-01-13 후지쓰 가부시끼가이샤 Eprom 및 그 제조방법
US5350941A (en) * 1992-09-23 1994-09-27 Texas Instruments Incorporated Trench isolation structure having a trench formed in a LOCOS structure and a channel stop region on the sidewalls of the trench
US5433794A (en) * 1992-12-10 1995-07-18 Micron Technology, Inc. Spacers used to form isolation trenches with improved corners
JPH07326659A (ja) 1994-06-02 1995-12-12 Hitachi Ltd 半導体集積回路装置の製造方法
US5872044A (en) * 1994-06-15 1999-02-16 Harris Corporation Late process method for trench isolation
US5665633A (en) 1995-04-06 1997-09-09 Motorola, Inc. Process for forming a semiconductor device having field isolation
US5920108A (en) * 1995-06-05 1999-07-06 Harris Corporation Late process method and apparatus for trench isolation
KR100401529B1 (ko) * 1996-06-03 2003-12-31 주식회사 하이닉스반도체 반도체소자의필드산화막형성방법
US6091129A (en) * 1996-06-19 2000-07-18 Cypress Semiconductor Corporation Self-aligned trench isolated structure
US5920787A (en) * 1997-01-16 1999-07-06 Vlsi Technology, Inc. Soft edge induced local oxidation of silicon
US5930647A (en) 1997-02-27 1999-07-27 Micron Technology, Inc. Methods of forming field oxide and active area regions on a semiconductive substrate
US6140156A (en) * 1999-07-13 2000-10-31 United Microelectronics Corp. Fabrication method of isolation structure photodiode
JP2001230390A (ja) * 2000-02-17 2001-08-24 Mitsubishi Electric Corp 半導体不揮発性記憶装置およびその製造法
JP2002134634A (ja) * 2000-10-25 2002-05-10 Nec Corp 半導体装置及びその製造方法
US6902867B2 (en) * 2002-10-02 2005-06-07 Lexmark International, Inc. Ink jet printheads and methods therefor
US7687370B2 (en) * 2006-01-27 2010-03-30 Freescale Semiconductor, Inc. Method of forming a semiconductor isolation trench

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3853633A (en) * 1972-12-04 1974-12-10 Motorola Inc Method of making a semi planar insulated gate field-effect transistor device with implanted field
US4506435A (en) * 1981-07-27 1985-03-26 International Business Machines Corporation Method for forming recessed isolated regions
US4454647A (en) * 1981-08-27 1984-06-19 International Business Machines Corporation Isolation for high density integrated circuits
JPS58132946A (ja) * 1982-02-03 1983-08-08 Toshiba Corp 半導体装置の製造方法
US4502913A (en) * 1982-06-30 1985-03-05 International Business Machines Corporation Total dielectric isolation for integrated circuits
JPS59124141A (ja) * 1982-12-28 1984-07-18 Toshiba Corp 半導体装置の製造方法
US4477310A (en) * 1983-08-12 1984-10-16 Tektronix, Inc. Process for manufacturing MOS integrated circuit with improved method of forming refractory metal silicide areas
US4584763A (en) * 1983-12-15 1986-04-29 International Business Machines Corporation One mask technique for substrate contacting in integrated circuits involving deep dielectric isolation

Also Published As

Publication number Publication date
FR2562326A1 (fr) 1985-10-04
EP0159931B1 (de) 1988-09-07
US4679304A (en) 1987-07-14
JPS61501668A (ja) 1986-08-07
EP0159931A1 (de) 1985-10-30
WO1985004516A1 (fr) 1985-10-10
FR2562326B1 (fr) 1987-01-23

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee