DE3480812D1 - Bericht orientierter unterbrechungsmechanismus fuer mehrprozessorsysteme. - Google Patents

Bericht orientierter unterbrechungsmechanismus fuer mehrprozessorsysteme.

Info

Publication number
DE3480812D1
DE3480812D1 DE8484401881T DE3480812T DE3480812D1 DE 3480812 D1 DE3480812 D1 DE 3480812D1 DE 8484401881 T DE8484401881 T DE 8484401881T DE 3480812 T DE3480812 T DE 3480812T DE 3480812 D1 DE3480812 D1 DE 3480812D1
Authority
DE
Germany
Prior art keywords
report
multiprocessor systems
interruption mechanism
oriented
oriented interruption
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484401881T
Other languages
English (en)
Inventor
Frank C Bomba
Stephen R Jenkins
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Digital Equipment Corp
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Application granted granted Critical
Publication of DE3480812D1 publication Critical patent/DE3480812D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/161—Computing infrastructure, e.g. computer clusters, blade chassis or hardware partitioning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
    • G06F13/26—Handling requests for interconnection or transfer for access to input/output bus using interrupt with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
DE8484401881T 1983-09-22 1984-09-21 Bericht orientierter unterbrechungsmechanismus fuer mehrprozessorsysteme. Expired - Fee Related DE3480812D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US53465283A 1983-09-22 1983-09-22

Publications (1)

Publication Number Publication Date
DE3480812D1 true DE3480812D1 (de) 1990-01-25

Family

ID=24130969

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484401881T Expired - Fee Related DE3480812D1 (de) 1983-09-22 1984-09-21 Bericht orientierter unterbrechungsmechanismus fuer mehrprozessorsysteme.

Country Status (8)

Country Link
EP (1) EP0139568B1 (de)
JP (1) JPH0719242B2 (de)
KR (1) KR910001788B1 (de)
AU (1) AU562975B2 (de)
BR (1) BR8404842A (de)
CA (1) CA1213374A (de)
DE (1) DE3480812D1 (de)
FI (1) FI843713L (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4831518A (en) * 1986-08-26 1989-05-16 Bull Hn Information Systems Inc. Multiprocessor interrupt rerouting mechanism
US5062040A (en) * 1986-12-22 1991-10-29 At&T Bell Laboratories Handling of notification of asynchronous events by user and stub processes of a distributed process executing on a plurality of processors of a multi-processor system
EP0272837A3 (de) * 1986-12-22 1988-09-07 AT&T Corp. Inter-Prozesssignalverarbeitung in einem Multiprozessorsystem
US4953072A (en) * 1987-05-01 1990-08-28 Digital Equipment Corporation Node for servicing interrupt request messages on a pended bus
WO1988008576A2 (en) * 1987-05-01 1988-11-03 Digital Equipment Corporation Apparatus and method for servicing interrupts utilizing a pended bus
KR930002791B1 (ko) * 1987-05-01 1993-04-10 디지탈이큅먼트 코오포레이숀 펜디드 버스에서의 인터럽트 서비스노드
JPH04128795U (ja) * 1991-05-17 1992-11-25 株式会社タカラ 動作玩具
EP0576764A1 (de) * 1992-06-30 1994-01-05 International Business Machines Corporation Verfahren und Vorrichtung zur Verwaltung von Zugriffen auf ein Betriebsmittel von mehreren Benutzern in einem Datenverarbeitungssystem
JP2005316951A (ja) * 2004-03-30 2005-11-10 Seiko Epson Corp 情報端末、情報処理システム、及び、これらの制御方法
US11635915B2 (en) * 2021-03-17 2023-04-25 Macronix International Co., Ltd. Managing memory reliability in memory systems

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS50156336A (de) * 1974-06-05 1975-12-17
JPS5925258B2 (ja) * 1976-09-28 1984-06-15 日本電気株式会社 プロセツサ制御システム
IT1100916B (it) * 1978-11-06 1985-09-28 Honeywell Inf Systems Apparato per gestione di richieste di trasferimento dati in sistemi di elaborazione dati
US4376982A (en) * 1980-06-30 1983-03-15 International Business Machines Corporation Protocol for inter-processor dialog over a communication network
US4381542A (en) * 1980-10-20 1983-04-26 Digital Equipment Corporation System for interrupt arbitration
US4420806A (en) * 1981-01-15 1983-12-13 Harris Corporation Interrupt coupling and monitoring system

Also Published As

Publication number Publication date
AU562975B2 (en) 1987-06-25
JPH0719242B2 (ja) 1995-03-06
KR910001788B1 (ko) 1991-03-23
BR8404842A (pt) 1985-08-13
CA1213374A (en) 1986-10-28
EP0139568A3 (en) 1986-10-08
AU3334384A (en) 1985-03-28
FI843713L (fi) 1985-03-23
EP0139568B1 (de) 1989-12-20
FI843713A0 (fi) 1984-09-21
EP0139568A2 (de) 1985-05-02
KR850002914A (ko) 1985-05-20
JPS60150157A (ja) 1985-08-07

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee