DE3467832D1 - Process for forming a narrow mesa on a substrate and process for making a self-aligned gate field effect transistor - Google Patents

Process for forming a narrow mesa on a substrate and process for making a self-aligned gate field effect transistor

Info

Publication number
DE3467832D1
DE3467832D1 DE8484105543T DE3467832T DE3467832D1 DE 3467832 D1 DE3467832 D1 DE 3467832D1 DE 8484105543 T DE8484105543 T DE 8484105543T DE 3467832 T DE3467832 T DE 3467832T DE 3467832 D1 DE3467832 D1 DE 3467832D1
Authority
DE
Germany
Prior art keywords
self
substrate
making
forming
field effect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8484105543T
Other languages
English (en)
Inventor
Alan Bicksler Fowler
Allan Mark Hartstein
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3467832D1 publication Critical patent/DE3467832D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/082—Ion implantation FETs/COMs

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Inorganic Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
DE8484105543T 1983-06-06 1984-05-16 Process for forming a narrow mesa on a substrate and process for making a self-aligned gate field effect transistor Expired DE3467832D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/501,463 US4587709A (en) 1983-06-06 1983-06-06 Method of making short channel IGFET

Publications (1)

Publication Number Publication Date
DE3467832D1 true DE3467832D1 (en) 1988-01-07

Family

ID=23993657

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484105543T Expired DE3467832D1 (en) 1983-06-06 1984-05-16 Process for forming a narrow mesa on a substrate and process for making a self-aligned gate field effect transistor

Country Status (4)

Country Link
US (1) US4587709A (de)
EP (1) EP0127814B1 (de)
JP (1) JPS603158A (de)
DE (1) DE3467832D1 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3602461A1 (de) * 1986-01-28 1987-07-30 Telefunken Electronic Gmbh Verfahren zum herstellen eines sperrschicht-feldeffekttransistors
US4689869A (en) * 1986-04-07 1987-09-01 International Business Machines Corporation Fabrication of insulated gate gallium arsenide FET with self-aligned source/drain and submicron channel length
EP0416141A1 (de) * 1989-09-04 1991-03-13 Siemens Aktiengesellschaft Verfahren zur Herstellung eines FET mit asymmetrisch angeordnetem Gate-Bereich
US5168072A (en) * 1990-10-12 1992-12-01 Texas Instruments Incorporated Method of fabricating an high-performance insulated-gate field-effect transistor
US6127242A (en) * 1994-02-10 2000-10-03 Micron Technology, Inc. Method for semiconductor device isolation using oxygen and nitrogen ion implantations to reduce lateral encroachment
US5661059A (en) * 1995-04-18 1997-08-26 Advanced Micro Devices Boron penetration to suppress short channel effect in P-channel device
US5849613A (en) * 1997-10-23 1998-12-15 Chartered Semiconductor Manufacturing Ltd. Method and mask structure for self-aligning ion implanting to form various device structures
US20070166971A1 (en) * 2006-01-17 2007-07-19 Atmel Corporation Manufacturing of silicon structures smaller than optical resolution limits

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3837935A (en) * 1971-05-28 1974-09-24 Fujitsu Ltd Semiconductor devices and method of manufacturing the same
US4287660A (en) * 1974-05-21 1981-09-08 U.S. Philips Corporation Methods of manufacturing semiconductor devices
JPS5928992B2 (ja) * 1975-02-14 1984-07-17 日本電信電話株式会社 Ｍｏｓトランジスタおよびその製造方法
US4037308A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
US4037307A (en) * 1975-03-21 1977-07-26 Bell Telephone Laboratories, Incorporated Methods for making transistor structures
DE2729657A1 (de) * 1977-06-30 1979-01-11 Siemens Ag Feldeffekttransistor mit extrem kurzer kanallaenge
DE2729658A1 (de) * 1977-06-30 1979-01-11 Siemens Ag Feldeffekttransistor mit extrem kurzer kanallaenge
JPS5447489A (en) * 1977-09-21 1979-04-14 Hitachi Ltd Production of mos semiconductor device
JPS5482983A (en) * 1977-12-14 1979-07-02 Mitsubishi Electric Corp Manufacture of insulating gate type field effect transistor
JPS54105482A (en) * 1978-02-06 1979-08-18 Mitsubishi Electric Corp Manufacture of semiconductor
US4313782A (en) * 1979-11-14 1982-02-02 Rca Corporation Method of manufacturing submicron channel transistors
US4377899A (en) * 1979-11-19 1983-03-29 Sumitomo Electric Industries, Ltd. Method of manufacturing Schottky field-effect transistors utilizing shadow masking
US4312680A (en) * 1980-03-31 1982-01-26 Rca Corporation Method of manufacturing submicron channel transistors
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
NL188432C (nl) * 1980-12-26 1992-06-16 Nippon Telegraph & Telephone Werkwijze voor het vervaardigen van een mosfet.
JPS57204172A (en) * 1981-06-08 1982-12-14 Ibm Field effect transistor
US4471524A (en) * 1982-06-01 1984-09-18 At&T Bell Laboratories Method for manufacturing an insulated gate field effect transistor device
US4450620A (en) * 1983-02-18 1984-05-29 Bell Telephone Laboratories, Incorporated Fabrication of MOS integrated circuit devices

Also Published As

Publication number Publication date
US4587709A (en) 1986-05-13
JPS603158A (ja) 1985-01-09
EP0127814B1 (de) 1987-11-25
JPH0523056B2 (de) 1993-03-31
EP0127814A1 (de) 1984-12-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee