DE3377963D1 - Signal input circuit - Google Patents

Signal input circuit

Info

Publication number
DE3377963D1
DE3377963D1 DE8383306163T DE3377963T DE3377963D1 DE 3377963 D1 DE3377963 D1 DE 3377963D1 DE 8383306163 T DE8383306163 T DE 8383306163T DE 3377963 T DE3377963 T DE 3377963T DE 3377963 D1 DE3377963 D1 DE 3377963D1
Authority
DE
Germany
Prior art keywords
signal input
input circuit
circuit
signal
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8383306163T
Other languages
English (en)
Inventor
Ohtani C O Patent Div Takayuki
Iizuka C O Patent Divi Tetsuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Application granted granted Critical
Publication of DE3377963D1 publication Critical patent/DE3377963D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Static Random-Access Memory (AREA)
DE8383306163T 1982-10-25 1983-10-12 Signal input circuit Expired DE3377963D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57187278A JPS5975721A (ja) 1982-10-25 1982-10-25 信号入力回路およびその制御方法

Publications (1)

Publication Number Publication Date
DE3377963D1 true DE3377963D1 (en) 1988-10-13

Family

ID=16203195

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8383306163T Expired DE3377963D1 (en) 1982-10-25 1983-10-12 Signal input circuit

Country Status (4)

Country Link
US (1) US4594519A (de)
EP (1) EP0107442B1 (de)
JP (1) JPS5975721A (de)
DE (1) DE3377963D1 (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4704547A (en) * 1984-12-10 1987-11-03 American Telephone And Telegraph Company, At&T Bell Laboratories IGFET gating circuit having reduced electric field degradation
JPS61163655A (ja) * 1985-01-14 1986-07-24 Toshiba Corp 相補型半導体集積回路
JPS61262827A (ja) * 1985-05-15 1986-11-20 Mitsubishi Electric Corp 半導体集積回路装置
US4682047A (en) * 1985-08-29 1987-07-21 Siemens Aktiengesellschaft Complementary metal-oxide-semiconductor input circuit
US4766334A (en) * 1986-03-07 1988-08-23 The Singer Company Level clamp for Tri-state CMOS bus structure
US4728820A (en) * 1986-08-28 1988-03-01 Harris Corporation Logic state transition detection circuit for CMOS devices
US4987318A (en) * 1989-09-18 1991-01-22 International Business Machines Corporation High level clamp driver for wire-or buses
JP3556679B2 (ja) 1992-05-29 2004-08-18 株式会社半導体エネルギー研究所 電気光学装置
US5461331A (en) * 1994-07-28 1995-10-24 International Business Machines Corporation Dynamic to static logic translator or pulse catcher
JP3045071B2 (ja) * 1996-05-30 2000-05-22 日本電気株式会社 差動信号生成回路

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3745731A (en) * 1971-01-27 1973-07-17 M Simpson Interlocking building construction
GB1381963A (en) * 1971-05-07 1975-01-29 Tokyo Shibaura Electric Co Counter using insulated gate field effect transistors
US3989955A (en) * 1972-09-30 1976-11-02 Tokyo Shibaura Electric Co., Ltd. Logic circuit arrangements using insulated-gate field effect transistors
JPS5723356B2 (de) * 1973-07-24 1982-05-18
JPS5461433A (en) * 1977-10-26 1979-05-17 Toshiba Corp Tri-value converter circuit
JPS5490941A (en) * 1977-12-26 1979-07-19 Hitachi Ltd Driving circuit of tristate type
US4350906A (en) * 1978-06-23 1982-09-21 Rca Corporation Circuit with dual-purpose terminal
JPS5571322A (en) * 1978-11-24 1980-05-29 Hitachi Ltd Switch input circuit
US4329600A (en) * 1979-10-15 1982-05-11 Rca Corporation Overload protection circuit for output driver
JPS57809A (en) * 1980-05-31 1982-01-05 Matsushita Electric Works Ltd Switch input circuit
US4435658A (en) * 1981-02-17 1984-03-06 Burroughs Corporation Two-level threshold circuitry for large scale integrated circuit memories
US4449064A (en) * 1981-04-02 1984-05-15 Motorola, Inc. Three state output circuit
JPS57166739A (en) * 1981-04-07 1982-10-14 Nec Corp Logical circuit
US4347447A (en) * 1981-04-16 1982-08-31 Mostek Corporation Current limiting MOS transistor driver circuit
US4465945A (en) * 1982-09-03 1984-08-14 Lsi Logic Corporation Tri-state CMOS driver having reduced gate delay

Also Published As

Publication number Publication date
EP0107442B1 (de) 1988-09-07
JPS5975721A (ja) 1984-04-28
JPH0446013B2 (de) 1992-07-28
US4594519A (en) 1986-06-10
EP0107442A2 (de) 1984-05-02
EP0107442A3 (en) 1985-07-10

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8320 Willingness to grant licences declared (paragraph 23)