DE3202025A1 - DEVICE FOR CONTROLLING THE OPERATION OF THYRISTORS OF A HIGH VOLTAGE VALVE - Google Patents

Description

Device for the operational control of thyristors of a high-voltage valve

The invention relates to a device for controlling the operation of thyristors of a high-voltage valve and in general the field of high-voltage power converter technology.

The invention can be used to control the components of high-voltage systems, in particular to monitor the operation of thyristors of the high-voltage valves in direct current transmission systems. 2Q known, contain high-voltage valves a large number of gesohalteten in series thyristors. The breakdown of a number of thyristors can lead to the breakdown of the entire valve. To increase the reliability of the valve operation, an excess number of thyristors is provided in the valves. But there remains the likelihood that a number of thyristors will fail during valve operation which is greater than the excess number of thyristors. To prevent valve rupture and the occurrence of accidents, the valve is equipped with a device for controlling the thyristor operation, which generates a warning signal and activates it in the event of further thyristor failures. There is a command to switch off the high voltage valve.

High operational reliability and immunity to interference are the main requirements for the thyristor control device, because valve breakthrough or incorrect valve shutdown lead to accidents in energy systems or to the shutdown of energy consumers.

It is a device for controlling thyristors a high-voltage valve is known (cf. e.g.

DE-PS 1.1941 _s 9ö9) i contains two scanners movably mounted on guides. There are electrical contacts on the guides that are connected to the anodes and cathodes of the thyristors. The connections of the scanners are connected to a display device which shows the operability of the thyristors. When checking the operability of the thyristors, the scanners are moved on the guides and thus to the anodes

and connected the cathodes of the thyristors. The operability of the thyristors is determined by the display of the Judged display device.

When checking thyristor operability but the valve must be switched off. There is no information about the state of the thyristors at their operation. In the period between the planned thyristor controls, however, the number of failed Thyristors exceed the excess number of thyristors, with the whole valve also failing. The state of the thyristors during their operation cannot be monitored with the device mentioned.

A known device for continuous control of thyristors (see e.g. SW-PS 556749) a first resistor in parallel with all of the thyristors in the valve and a second resistor in parallel is connected to one of the thyristors, the so-called reference thyristor. The resistors are in series with rectifiers whose leads out with a electrical measuring device and / or are connected to an electronic amplifier. When thyristors break down the pointer of the measuring device is deflected, the magnitude of the deflection being proportional to the number of thyristors broken is. The electronic amplifier sends a signal to a signaling and protection circuit.

However, the device is insufficiently reliable and as a result of uneven voltage division on the thyristors also insufficiently accurate in determining the number of failed thyristors. When the Reference thyristor fails the whole device. In addition, the facility does not provide any information which thyristor has just failed.

Another known device for the operational control of thyristors of a high-voltage valve shows accordingly the thyristor number thyristor voltage range? on, which are connected with the help of fiber optics to the inputs of a Lion-osignal converter, which the Converts light signals into electrical signals. The Aus

output of the Liohtsignal converter is with the input of a Buffer electrically connected, its output to a display unit for. Display of the number of failed thyristors and to a circuit arrangement for Protection of the high-voltage valve against breakthrough is connected. The facility also includes a Selector that works with the light signal converter electrically is connected, the address input of the selector being connected to a control unit and its output

IQ is on a display unit to display the numbers of failed thyristors (see e.g. SW-PS 365915).

-In the facility are the outputs of the buffer memory to the selector and the zero position input connected to the corresponding output on the control unit. Contains to control the display units the facility also includes a control pulse generator that works with the inputs of the display units for displaying the number of failed thyristors and the numbers of failed thyristors. The ones from the thyristor voltage generators The generated pulses reach the storage elements via the fiber optic channels, in which they are stored will. With the help of the selector, the signals are sent from the memory in the form of narrow pulses transmitted to the display units.

The serial signal transmission takes place without control and without confirmation of the correctness of the result. Those leading to accidents in the energy supply system Failures in the facility are not recognized in time. The facility is characterized by low immunity to interference

XQ , although it is intended for use in converter substations of direct current transmission systems, where the interference level is very high. Malfunctions and incorrect response of the device in which the information is processed in the form of brief pulses falsify the result. In addition, the device outputs incorrect information, for example about breakdowns of all thyristors, if the voltage on the valves briefly becomes zero in the event of an accident.

The invention is based on the object of a device for operational control of thyristors of a high voltage valve to develop in the encoded by comparing the after, repeated query processes Numbers of failed thyristors the reliability ^ · The ability to determine the number of defective thyristors is increased.

This task is achieved by being in the facility for the operational control of thyristors of a high-voltage valve, which corresponds to the number of thyristors Contains thyristor voltage transmitter that with the help from optical fibers to the inputs of a converter designed to convert light signals into electrical signals (Light signal converter) are connected, its output is electrically connected to a buffer memory, at which the inverted output with a display unit for Display of the number of failed thyristors and with a circuit arrangement for protecting the high-voltage valve has electrical connection before breakthrough, and the one electrically connected to the light signal converter Has selector whose address input is connected to a control unit and whose output is connected to a Display unit for displaying unusual numbers According to the invention, the input of the selector is connected to the output of the light signal converter and the thyristors Output of the selector to the input of the buffer memory can be switched, whereby the device is also provided with the following components: an OR gate block, in which the input to the corresponding output of the buffer memory and the output to the data input of the Display unit for displaying unusual numbers Thyristors are switched; a bummator whose input is connected to the output of the OR gate block will; a memory block in which the inputs are connected to the output of the summator or to the outputs of the control unit are connected and the output is fed to the second input of the OR gate block; a comparator, whose inputs are connected to the second output of the

matora or with the address reading output of the memory block be connected and its output to the An. display unit for displaying the number of failed thyristors as well as to the circuitry for protection · The high-voltage valve is switched before the breakthrough. JSs is useful to provide the facility with a data control unit for registered mail, at which the inputs to the output of the display unit to display the number of failed thyristors or to the output of the circuit arrangement to protect the high voltage svalve must be connected before the breakthrough and the output with the control input of the control unit and is connected to the control input of the circuit arrangement for protecting the high voltage valve from breakdown.

The device can contain an additional comparator, the input of which is connected to the output of the summatora is switched and its output to the reset input of the sumiaator is connected.

It is advantageous to equip the summator with a combination sensor with N stages, each of which Level several elementary main summers and additional ones

^ iu -. ^ o. -U- number η _., ...

Summators includes, with one / of inputs of the

Elementary summators as single-digit inputs of the combination summator are used, the S outputs of the main summators and the additional summators of the first Stage to the inputs of the additional element ar suuuaatoren connected to the same stage, the S output of the additional Suiauiators of each stage the output of the Combination summators forms the P output of each stage and the next stage is connected to the inputs of the elementary main summers of the following stage, the last stage only receives one elementary summator, its P and S outputs as outputs of the combination summator serve, and a code converter is also used in the summator, the inputs of which are connected to the outputs of the combination summator and a storage element with flip-flops corresponding to the number of stages is used, where the I and K inputs with the paraphase outputs of the code converter, the C inputs

ge but are switched together and the control input of the summator, while the Q output of each flip-flop is connected to the input of the elementary summator of the value of the flip-flop corresponding stage is performed and serves as the output of the summator, and a counter is used in which the count input to the carry output of the code converter is switched, the second counter input is interconnected with the C outputs of the flip-flops and the outputs serve as outputs of the summator, as well as a logical OR gate built in whose inputs with the control unit and with the Output of the additional comparator are connected and its output to the reset inputs of the flip-flops and of the counter can be switched.

The memory block can conveniently be used as a Series connection of a write selector, a memory unit and a read selector are set up, the Data inputs of the reading selector are connected to the second .Inputs of the logical OR circuits of the OR gate block will.

The comparator may include a comparison circuit and a with this AND gate unit lying in series, where the first inputs of each logical AND circuit with the corresponding address input of the reading selector are connected in the memory block and the input of the comparison circuit is switched to the output of the combination ummat or s. ·. ·

The structure of the display unit for the display is advantageous of numbers of failed thyristors with the following Building units: an AND circuit group in which the first Inputs of the AND circuits are connected to the outputs of the · OR gate look, a register. the inputs of which are fed to the outputs of the logical AND circuits; a light indicator whose inputs switched to the outputs of the register; a return pulse shaper, where the input to the second Inputs of the logical AND circuits is connected and the output is connected to the input for resetting the

gisters is connected; a comparison circuit whose first inputs switched to the address outputs of the selector and the output of which is connected to the second inputs of the logical AND circuits; an arrangement for specifying addresses of the thyristors to be monitored, the outputs of this arrangement with connected to the second inputs of the comparison circuit will.

By connecting the selector to the output of the light signal converter and to the buffer memory,

is there in the ^inventu ? ^{In accordance with the} arrangement, there is less need for storage elements which, in contrast to the interconnection circuits, are less immune to interference. The reduction in the number of storage elements in the circuits for calling up thyristors leads to higher immunity to interference and the operational reliability of the device. By using the logical OR circuits, the installation of another summer can be avoided and the reliability of the device is increased. The summator used in the facility provides the ability to count failed thyristors. The count is based on the information represented by the non-position code, while the result is output in binary-decimal code. This results in the possibility of counting failed thyristors with the help of known, proven and reliable elements of computing technology and thus additionally increasing the reliability of the device. The use of the memory block makes it possible to call up the thyristors of the valve several times and to process the results of the call processes statistically, for example according to the voting principle, the credibility of the results being considerably increased when the device is in operation. The comparator present in the device allows the results obtained in the event of faulty operation of the device, for example if its thyristor voltage generator to respond incorrectly, to be omitted and thus the reliability of the results to be further improved. By

the installation of the data control unit for registered mail The possibility now arises of the correctness of the data storage in the register of the display unit to display the number of failed thyristors and the circuit arrangement for protecting the high-voltage valve to monitor before breakthrough. This control unit also prevents the Protective circuit in the event of a failure of the device or in the event of a malfunction, thereby increasing its reliability. The use of the additional! Comparator enables the display to be deleted if one of the Donor group.

The invention is described in the following description a specific embodiment and based on the attached Drawings explained in more detail. Show it

]? ig. 1 is a block diagram of the facility for operational control of thyristors of a high voltage valve according to the invention;

Piss. 2 is a block diagram of the summer in FIG Device according to the invention;

Pig. 3 is a schematic of the facility comparator according to the invention;

Pig. 4 is a block diagram of the display unit for Display of numbers of failed thyristors in the device according to the invention.

The device for the operational control of thyristors a high-voltage valve contains thyristor voltage generator 1 (Pig. 1), which with the help of optical fibers connected to the inputs 3 of a light signal converter 4 which converts the light signals into electrical signals. The thyristor voltage generator 1 is used as an encoder used, with the help of which the voltage on the thyristors 5 in. A light signal is converted. The number the encoder 1 is determined by the number of thyristors 5 im. Determined high-voltage valve, each transmitter 1 with the JUiode and the cathode of the corresponding thyristor is electrically connected.

The multi-channel output of the light signal converter 4 is

connected to the input 6 of a selector 7, the address input ü of which is at the output of a tit your unit 9. The number of channels in the light signal converter 4 depends on the number of thyristor voltage generators 1 connected to it. The address output of the selector 7 is connected to the address input; IO connected to a display unit 11 for displaying numbers of failed thyristors. The data output of the selector 7 is connected to the input 12 of a buffer memory 15. To control a high-voltage valve with 256 thyristors, the »Selector? in the variant described, twelve address lines.

The setup also includes an OR gate block 14, whose input 15 is connected to the corresponding output of the Buffer memory 13 is connected, and a summer 16, in which the input 17 at the output of the OR gate block 14 lies. The output of the OR gate block 14 also has the data input 18 of the display unit 11 for display from the throbbing of failed thyristors connection. The device also has a memory block 19 auf, bei.dem the inputs 20, 21 to the output of the summator 16 or to the output 22 of the control unit 9 are connected and the output 25 is connected to the second input 24 of the OR gate block 14. Another component the device is a comparator 25 whose inputs 26, 27 with the second output of the simulator 16 or with the address reading output 28 of the memory block are connected and its output at the input 29 of a display unit 50 for displaying the number of failed Thyristors and at the input 51 of a circuit arrangement 52 to protect the high paintings ν ent ils from breakdown lies.

To assess the reliability of the information transmitted about the number of thyristors that have failed the device contains a unit 55 for data control when writing, in which the inputs 54, 55 to the output of the display unit 50 to display the Number of failed thyristors or to the output

the closure assembly 32 to protect the high-voltage valve are connected before breakthrough and the output to the control input 36 of the control unit 9 and with the control input of the circuit arrangement 32 for Protection of the high-voltage valve from breakthrough connected is.

In order to prevent the device from failing to respond if a short circuit occurs in the circuit of the high-voltage valve or the voltage at the valve connections decreases to a level at which the transmitter 1 does not supply any signals, an additional comparator 37 is provided, the input 38 of which is at the output of the summator 16 and the output of which is connected to the setting input 39 of the summator 16. The reset input 40 of the memory block 19 is at output 41 of the control unit 9 The outputs 42, 43, 44, 45, 46 of the control unit 9 are connected to the reset input 47 of the buffer memory 13, to the control input 48 of the summator 16, connected to the control input 49 of the memory block 19 »to the reset input 50 of the circuit arrangement 32 to protect the high-voltage valve from breakthrough or to the ßüoksetze input 51 of the display unit 30 to display the number of failed thyristors.

In the relevant embodiment variant of the device, the summator 16 contains a combination summator 52, a code converter 53 and a storage element 54 which are connected in series. The output of the memory element 5 ^ is connected to the multi-digit input 55 of the combination summer 52. The combination summator 52 (Pig. 2) has a number N _{V of} stages, where N is equal to four.

The. first otufe N-, contains four elements ar summa-

^χ the

gates 56, 57, 5a, 59, of which / the first three are the main summers and the summator 59 is an additional summator. The second stage N ₂ consists of two elements ar summat or en with three inputs, with 60 being the main summator and 61 being the additional summator. The third

Stage N is composed only of an elementary summator 62 with three inputs, which is a main summator, while the fourth stage £ L contains a summator 63 with two inputs. Eight .Inputs of the elementary summators 56, 57, 58 form the input 1? of the combination summator 52, and an input of the element arsummat or s serves as an input for the first digit in the multi-digit input 55. The S outputs of the summators 56, 57, 58 are connected to the inputs of the element arsummat or s 59, while the P outputs are at the inputs of the El an nt ar summ at or s 60. One input of the elementary summator 61 serves as an input for the second digit in the multi-digit input 55, and two other inputs are connected to the P output of the elementary summator 59 and to the SA us output of the element arsummat ors 62. One of the inputs of the Elementarsummators 62 "serves as the input of the third point in the multi-digit input 55 'while two other inputs to the P outputs of the elementary averagers 60 and 61 lie. An input of the Elementarsummators 63 is for input of the fourth digit in the multi-digit input 3 ^> provided, the other input is connected to the P output of the element arsummat or s 62.

The code converter 53 is widely known Circuit of the linear decoder built and for Conversion of the binary number code into the binary decimal code certainly. This implementation also implies the delivery of the decimal transmission signal " ahead if the sum of the lower digits is the same at the given time or greater than ten igt. For example, the number becomes written in binary code as 1100, with the number 0010 and the carry signal at the output of the code converter 53 appear.

The S outputs of the elementary summators 59 »61, 62, 63, and the P output .des summator 63 are connected to the 3 ^ inputs of the code converter 53 »whose output with the Storage element 5 ^ is connected. Here are the paraphase outputs of the code converter 53 », which are intended for low-order digits, to the IK inputs of the

Flip-flops 64, 65, 66, 67 connected, which have a common C input for control and an R input for zero position, the latter forming the input 48 of the Suminator 16.

The output 68 of the code converter 53, at which the carry signal appears, is connected to the counting input 69 of a counter 70 which belongs to the storage element 54. The second count input 71 of the counter 70 is connected to the C control input of the IK flip-flops 64, 65, 66, 67 ζ. The R input of the counter 70, which is intended for zero setting, is connected to the full position R input of the IK flip-flops 64 ... 6? connected and connected to the output of a logical OR element 72, in which one input forms the input 39 of the summator 16 and the other 15 .

The QrAusgäneje the flip-flops 64 ... 67 are accordingly at the inputs of the first, the second, the third and the fourth digit of multi-digit input 33 of the D Kombinationssumrnators 52. _A at serve the Q outputs of the flip-flop 64 IK .. .67 and the Q outputs of the counter 70 as the output of the Suramator 16.

The memory block 19 (Fig.l) contains a write selector 73> whose multi-digit input forms input 20 of memory block 19. The number of digits of the multiple The first input is determined by the data processing code in the summator 16. The pale binary-decimal code ipt is most useful, since two decimal points of the Ö-bit- -Group correspond to the byte that underlies the structure of the majority of current microprocessor systems lies.

The memory block 19 also includes a memory unit 74 and a read selector 75 which are in series with the selector 73.

The number of multi-digit inputs of the memory unit 74 depends on the number of registers in this memory unit 74 and is chosen based on the condition of sufficient earnings averaging, in which

· The control input of the write selector 73 forms the Control input 21 of the memory block. 19 · In the present embodiment of the invention, the writing selector 73, the storage unit 74 and the read selector 75 according to the largely usual circuits (see e.g.

Branka Soucek .., "Microprocessors and Microcomputers", USA, 1976, 8. 38 and Handbuch für Integrale Mikroschalt-. gen edited by Tarabrina AB, Moscow, "Energia", 1980 p.340, Spravochnik. po integralnym Mikroskliemam pod redakfcsiei larabrina AS, Moscow "Energia" 1980, p.340).

The comparator 25 (Fig. 3) contains a comparison circuit 76 and a UM lying in series with it) - -Gate unit 77 The first inputs of the logical UM) - -Circuits form the input 27 of the unit 77> which is connected to the address outputs 28 of the read selector 75 is. The comparison circuit 76 includes a binary-decimal De bait 79, whose multi-digit input 80 serves as input 26 of the comparator 25 and with the output of the combination sumraat or s 52 is connected. The den Numbers "5", "6", "7", "8", "9", "10" correspond to outputs of the binary-decimal decoder 79 »at which the comparison signal arises, · are connected to the inputs 81 of an OR circuit 82 with multiple inputs. The output of the latter is at the second inputs 83 of the logical AND circuits.

The display unit 11 intended for displaying numbers of failed thyristors (FIG. 4) contains a AND circuit group 84, in which the first inputs ■ the outputs of the OR gate block 14 are switched and the outputs at the asynchronous inputs 85 of a register 86 lying. The outputs of the register 86 are connected to the inputs 87 of the illuminated display 88, which are shown in the present execution variant by a set of Light emitting diodes is formed. At the reset input 89 of the

gisters 86 is a reset pulse shaper 90, whose .Input 91 to output 92 of a comparison circuit 93 is switched. The output 92 is also to the second Inputs 94 of the logical AND circuits 84 connected. The first inputs of the comparison circuit 93 are at the address outputs of the selector 7 and the second entrances 95 at the exits of an arrangement 96 for specifying the addresses of the thyristors of the high voltage valve to be monitored.

For the transmission of information about failed thyristors via the communication channel to the calculating machine contains the display unit intended for displaying numbers of failed thyristors 11 additional structural units, the in J? ig. 4 are not shown. The latter do not belong to the subject of the present invention and are therefore not described.

The control unit 9 (FIG. I) contains a clock pulse shaper 97 'the one from a pulse generator 98 and four Frequency dividers 99, 100, 101, 102. The latter represent binary counters with counting modules 10, 10, 4 and 9 and. are connected in series with the binary decimal decoders.

The output of the pulse generator 98 is at the input 103 of a logic non-element 104, to the input 105 of a delay element and to the input of the Frequency divider 99 connected to Rösch. The single-channel output of the Frequency divider 99 is at the input of the frequency divider 100, at the entrance 10? another logical non-member 108 and at the first inputs 109, HO logical AND -Glieder 111 or 112. The second input 113 of the AND gate 111 is connected to the output of the logical NOT gate 104 connected, while the second input 114 of the AND element 112 is connected to the output of delay element 106.

The single channel outputs of the frequency dividers 100, 101 are connected to the inputs of the dividers 101 and 102, respectively. The multi-channel output II5 of the frequency divider 100 is at the first inputs 116 of an AND element group II7, at which

ren second inputs 118 the output of the logical NOT- Link 108 is connected. The outputs 119, 12Π the logical AND elements 111, 112, the multi-channel output 121 of the logical IHiD elements of the group and the multi-channel outputs 122, 123 of the frequency dividers 101, 102 are connected to the inputs of an address command shaper 124.

This address command former 124 constitutes a sentence of logical AND elements, with the help of which the conjunction of the address sisnale comes about.

IQ Each channel of the multi-channel output 121 of the logical

ÜITD membership group 11? is intended for the transmission of clock pulses with address designations a1, a2, ... a9, aO, in a similar way, each channel of the multi-channel outputs 122, 123 of the frequency divider 101, 102 for the passage. ν on '^ Aktimpuls with address designations bl, b2, b3, b4 or el, c2, c3, ... c9, cO provided.

To increase the speed you can use the number the buffer memory 13 with simultaneous simplification of the selector * / between the buffer memory 13 and the Insert ODBR gate block 14 after an additional selector.

The operational control of thyristors of a The high voltage valve specific device works as follows.

When the high-voltage ^{valve is energized, senders 1 (S 1} Ig.1) emit light pulses. These pulses reach the light signal converter 4 via the light guide 2, in which they are converted into electrical pulses. If all thyristors 5 are fault-free, the number of pulses at the output of the light signal converter 4 is equal to the number of thyristors 5 in the valve. If a thyristor 5 is broken, the pulses at the output of the corresponding encoder 1 are missing. From the output of the light signal converter 4, the electrical pulses are fed to the input 6 of the selector 7, the number of these pulses being determined by the number of whole thyristors 5 will. An address signal in the form of a combination of two im-

pulses a1, a2, a3 »... a8 and bl, b2, b3, b4 given. After this signal, a group of thyristors 5 connected to the buffer memory 13. In the present Embodiment consists of the group of eight thyristors 5. The same combination of pulses a and b is applied to input IO of display unit 11 for display created by numbers of failed thyristors.

The input 12 of the buffer memory IJ is a number fed by H and L signals, the H signals correspond to the thermosetting thyristors 5 of the high voltage valve. These brief Η signals are read into the register of the buffer memory 1 $ and get from its output via the OR gate block 14 to entrance 1? of the summator 16 and at the same time to Data input 18 of the display unit 11 for displaying numbers failed thyristors.

In the combination summer 52 is in the form of a Encoded sequence of H and L signals represented information. It is from the output of the summer 52 to the Input of the code converter 53 the binary coded information transmitted over the number of Η signals. The operation of the code converter 53 will now be described. From the output of the code converter 53, the signals are fed to the memory element 5 ^.

The control unit 9 then switches to the input 47 of the buffer memory 13 a signal for resetting this buffer memory 13 given. Then the address signal at the input 8 of the selector 7 changes and begins the read-in cycle for the second Thy-

3ö ristorgruppe supplied information. In the storage element 54, the sum of the query results from two thyristor groups 5 is entered. The entry takes place in the binary decimal code. After all Thyristor groups of the high voltage valve whose.

Number in the present embodiment is 32, is from output 22 of control unit 9 to the Input 21 of the memory block I9 is given a control signal. After this signal, the number is stored in the memory element

with. Help of the write selector 73 in the register of the Memory block 19 belonging memory unit 74 in binary -Decimal code rewritten. Exit 43 the control unit 9 to the input 48 of the suinmator 16 a signal for zeroing the memory element 54 is given.

After entering the information in the first register the memory unit 74 are all thyristor groups 5 of the high-voltage valve is again queried. The number of failed thyristors is determined by the storage element 54 and into the second register of the storage unit 74 transferred. The third and the next following register of the memory unit 74 are then opened. fills. In the relevant embodiment variant of the invention, the memory unit 74 has eight registers.

by means of the multichannel output 44 of the control unit 9 successive pulses delivered the information written in the storage unit 74 read out. At the same time the same impulses arrive from the output 28 of the memory block 19 to the multi-channel -Address input 27 of the comparator 25

The first impulse that goes through the first line to the Control input .49 of memory block 19 arrives, switches the first way is to create the storage unit 74 at the multi-channel output 22.

A sequence of eight Η signals or eight L signals ■ is fed to the input 24 of the OR gate block 14 and from the output of the latter to the input 17 of the summator 16. If encoder 1 works incorrectly for a short time, the eight-signal sequence consists of L and H signals. In this case, a signal is given from the second output of the summer 16 to the input 26 of the comparator 25, which the number of Η signals at the output 23 of the memory. ' · Indicates blocks 19 in binary code. If the specified number of Η signals is a plurality, e.g. five out of eight, then the comparator 25 delivers a pulse to the inputs 29 and p1 of the display unit 30 via the line corresponding to the first line of the teaching channel input 27 to

show the number of failed thyristors or the Circuit arrangement 32 for / α use of the high-voltage valve before Durohbruch.

The Η signal is entered in the first register position of the memory elements, not shown in FIG. 3, of the display unit 30 and the circuit arrangement 32 are read. in the opposite pail if the number of Η signals in the first registers of the memory unit 74 is the same is four or less, is entered in the first register position of the memory elements of the display unit 30 and the circuit arrangement 32 the L-Siü'nal entered.

The second pulse, which is sent via the second line from the main channel output 44 of the control unit 9 to the multi-channel input 49 of the memory block 19 is transferred, switches the second register positions of the memory unit 74 to the multi-channel output 23. A sequence of H and L signals come to input 24 of the OR gate block 14 and from the output of the latter to the input 17 of the summator 16. From the second exit of the Suamiators 16 is on the input 26 of the comparator 25 is given a signal, this is the number of H-Sia-nals at the output 23 of the memory block 19 »i.e. the number of in the second digits of the eight registers of the memory unit 74 read in H signals in binary code.

If the specified number of Η-signals is a plurality, E.g. five out of eight, the comparator 25 delivers via the second line of the Iviehrkanale inganges? 7 corresponding line sends a pulse to the inputs 29 and 31 of the display unit 30 or the circuit arrangement

jO ^D as Η signal is read into the second register location of the memory elements der.Anzeigeeinheit 30 and the circuitry 32nd

The rewriting takes place according to the similar majority principle derH signals from all register locations of the memory unit 74 of the memory block 19 into the corresponding Register locations of the memory elements of the display unit 30 and the circuit arrangement 32. Is shown in the registers of the display unit 30 'and the circuit

arrangement 32 an equal number in binary-decimal code read in, it means that the registers are working properly and no malfunctions occur, whereby the multi-digit inputs 35, 34 of the unit 33 for data control. the same information is supplied when registered. From the output of the unit 33 is on Input of the circuit arrangement 32 continues to be given a signal that the transmission of the command to shutdown of the high-speed valve releases. The same thing . The signal also reaches the input 36 of the control unit 9

and allows the generation of the signal for zeroing the registers in the memory unit 74 of the memory • blocks .19.

If the in the register of the circuit arrangement 32 registered number is greater than the certain number of excess thyristors 5 in the valve, gives the for Protection of the valve provided circuit arrangement 32 ' a command for the Vent i lab circuit. · ·

The zero setting of the storage elements of the display unit it 30 takes place with the aid of one from the output 46 of the control unit 9 supplied signal after all registers of the memory unit 7 ^ have been filled. Are in the register of Storage elements of the display unit 30 and the circuit arrangement 32 different dates are entered the output circuits of the circuit arrangement 3? blocked, and is due to the unique 36 of the control unit 9 no signal. Therefore, the control unit 9 commands twice more to rewrite the information the registers of the memory unit 74 into the registers of the Storage elements of the display unit 30 and the circuit arrangement 32 given. All memory elements are on it deleted from the facility. A new cycle of interrogating thyristors 5 of the Hochspaimungsvent ils begins.

If the signals at the outputs of the register positions the display unit 30 and the protection. maintenance order 32 are unequal for a certain length of time, the unit 33 intended for data control when writing outputs a signal that responds to the disturbed loading

- 25 drive indicates the establishment.

The Sumwator 16 (Fig. 2Ϊ works as follows. The information about the respective state of the thyristors 5 of the high-voltage valve is the input 17 of the summer 16 in .Form of bytes supplied.

Each byte contains the information about eight thyristors. 5. The number of Η signals in one byte corresponds to the number of defective thyristors 5. The bytes arrive at input 17 serially in time. Simultaneously or with a time delay are on the line the first digit of the expensive entrance 48 from the Sumlüator 16 from the output 43 of the control unit 9 control pulses fed in.

When the first thyristor group is queried, the first byte, which consists of eight single-digit signals, arrives at input 17. This byte is fed to the eight single-digit inputs of the combination summer 52. At the outputs of the latter, the sum of Η signals in the first byte appears in the binary code, while the binary-decimal code of the same number that is fed to the data inputs of the memory element 54 is generated at the outputs of the code converter 53. Before the start of counting defective thyristors, the memory element 54 is set to zero, so all digits of the multi-digit input ^ of the combination sumiuat or s 52 have zero values. When the first thyristor group is queried, the summator'52 adds up only eight single-digit signals that are applied to the eight inputs of the elementary summators 5ö, 57 »5Ö. Signals with a weight of one are fed to the inputs of the first adder stage N1, with signals weighted also being generated at the S outputs of this stage, while signals with a weight of two appear at the P outputs. At the S outputs of the summators 65,57,58 there are signals from between before ns umtue η of weight one. The * units place of the calibrated sum is formed at the S output of the sumiuator 59.

The second adder N2 sums the signals of the

- άΌ -

the following second place, i.e. with weight two. The intermediate sum "appears at the S output of the summator 60 the second digit as the result of the summation of the signals from the P-outputs of the summators 56, 57 »58. Thisea Signal as well as the signal from the P output of the summator 59 and the signal from the second digit of the input 551 which is the same when querying the first thyristor group Was zero are fed to the summer 61. The value of the second digit of the sum you are looking for appears at the S output of summer 61.

The stimulator 62 also generates this at its S output four evaluated signal of the third digit of the sum to be determined by adding the signals from the P outputs the summators 60, 61 and the signal of the third digit of the input 55 is used, which is used when interrogating the first thyristor group was zero.

The summator 63 supplies that with eight from the S output weighted signal of the fourth sum digit and from the P output the (JbertraessiRnal weighing sixteen. This off-ολ output signals are generated according to the values of the

P output of the summer 62 and generated by the fourth digit of the input 35 supplied input signals, the latter input signal being equal to zero at the first interrogation.

In the code converter 53, the binary code of the sum obtained from the output of the combination summators 52 is converted into the binary-decimal code. After the counting pulse has dropped, which arrives at the first digit of input 48 when each thyristor group is queried, four low-order digits 1,2,4,8 of the sum in the binary decimal code are entered in the IK plip-flops 64, 65, 66 , 67 read. The counting pulse is fed to the interconnected counting inputs of these plipflops 64 ... 67 and the second input 71 of the binary-decimal counter 70. At output 68 - P ^ ₀ the zero signal is missing in the first query.

The initial zero setting of the memory element 54 takes place with a signal that is generated by the logical two-one

output OR gate 72 is supplied, on the inputs Signals from input 39 and over the line of the second Place of the control inganges 48 are given.

Faoh drop in the first counting pulse will be the more urgent input 55 from the Q outputs of the flip-flops 64 ... 67 the information about the number of defects Thyristors supplied, which were counted in the binary-decimal code at the first query. This code is correct for the places one to four match the binary code.

In the second query, the sum of defective thyristors in the second and first thyristor groups, ie the sum of the binary signal number at input 17 and the binary number at input 55, is determined in summator 52. This can result in a count greater than ten. In this case, the Η signal appears at the output 68 - P _{10 of} the code converter 53, which is entered in the low-order digit of the binary-decimal counter 70 when the second counting pulse falls.

In this case, in the case of the third query, the üummator 52

the sum of defective. Thyristors in the third group of thyristors and the number stored in the flip-flops 64 ... 67 as a result of the second query is determined. Furthermore, in the summator 16 the resulting numbers at the input 17 and those in the flip-flops 64 ... 67 at Queries of the previous thyristor group saved Number summed up. Jüach completion of the query of all thyristor groups becomes the addition result from the Q outputs of the mentioned flip-flops 64 ... 67 and from the outputs of the counter 70 into a register of the memory unit 74 rewritten.

The comparator 25 (Fig. 3) functions as follows.

Signals in the form of a number stored in binary code are fed to the input of the comparator 25.

This number represents the number of Η signals stored in the registers of memory unit 74. Actual if this number is equal to or less than four, it gives

* Λ

- 28 -

the number of incorrect entries of the logical H level in the register of the memory unit? 4 again. If the mentioned number is equal to or greater than five, so indicates that the number of incorrect applications of the logic L level in the registers equal to the difference between the number eight and the comparison number, is.

The pulses which represent the number in the binary code arrive at the inputs 80 of the decoder 79 pulses appear at the outputs of the decoder 79 »their order numbers O, 1, 2, ... 9 correspond to the numerical value of the Correspond to the input signal. Is the numerical value on the * If the output 26 of the comparator 25 is equal to or less than four, then the logical OR circuit appears at input 81 no impulse. Is the numerical value at input 26 of the co-comparator 25 equal to or greater than five., Then comes the from Output of the decoder 79 output pulse to one of the inputs 81 of the logical OR circuit 82. The on Output of the logical ODSR so-hold 82 generated 'pulse represents the output pulse of the comparison circuit 76. In this way, the comparison of the number fed to the input of the! Comparator 25 with the number four, which represents the maximum possible number of incorrect response processes in the thyristor voltage sensors 1. From the output of the comparison circuit 76 comes the Pulse to the second inputs 83 of the logic UliD circuits of AND gate unit 77 · In the consecutive Query the eight register locations of the storage unit 74, a control signal is sent to the address input 27 of the comparator 25 at the same time. When querying the The address signal is sent via the first line of the input 27 transmitted, when querying the second digits, it arrives on the second line, and so on Address H signal is in input 78 of the corresponding logic IMD circuit fed, and at the output this AND circuit appears a üatenimpuls, which leads to corresponding line of the output 28 in the comparator is directed. The rewriting takes place in this way

of the eight in the registers of the storage unit 74 im Binary code stored numbers in the register of the display unit 30 and the circuitry 32. The presence of the! Comparator 25 enables to switch off false failures of the thyristor voltage transmitter 1 and the reliable functioning of the display unit 11 as well as the protective circuit arrangement 32 to best ize.

The ones for displaying the numbers of failed thyristors certain display unit 11 (Pig. 4) works as follows.

The operator specifies the address of the thyristor group to be queried with the aid of the specification arrangement 96, whereby in two of twelve lines of the input 95 the.

Comparison circuit 93 two Η signals are fed. The input 10 of the display unit 11 is provided by the control unit 9 about the selector? alternately address signals of all thyristor groups of the high-voltage valve fed. At the time when the address signals match arises at the inputs of the comparison circuit 93 an H pulse at its output 92. This impulse arrives to the input 91 of the reset pulse shaper 90, which sends a brief zeroing signal to the input 89 of the ■ ßesisters 86 issues. At the same time the same impulse comes at the second turns of the logical AND circuits 84 at. When querying the respective thyristor group the input 18 of the display unit 11 via eight lines the information about the state of the thyristors 5 in the Group fed. This information is seen in the form of logis L and Η signals shown. If a thyristor of the group is broken, then the input 18 of the Display unit 11 and to the first input of the corresponding logical AND gate 84 via the appropriate line the logical Η-impulse. From the output of this AND element 84, a pulse is sent to input 85 of the register 8S given. Register 86 stores the information supplied to input 18 as a combination of high and low signals, showing the state of thyristors in the group

reproduces whose address was specified by means of the arrangement 96.

From the output of the register 66, pulses of a long duration are applied to the inputs 8.7 of the indicator 88, with the help of which the state of thyristors of the respective group is visually displayed.

The control unit 9 (PIg.1) operates in the following Way.

The clock pulse generator 98, which is called symmetrical Multivibrator is constructed, generates g-pulses, which.

the input of the frequency divider 99 are fed. At the Output of the frequency divider 99 pulses appear - ^ the first intermediate frequency with a duty cycle that the counter module (equal to ten) of the binary counter of this frequency divider 99 corresponds. The duration of these impulses

c < is equal to the oscillation period of the multivibrator in generator 98. By means of the logical non-element 104 and the logical AND element 111, a pulse is formed whose leading edge is in phase with the leading edge of the output pulse of the frequency divider 99 and whose duration is half that long as the duration of this impulse is. The generated pulse is intended to form the counting command for the storage elements 54 of the summer 16. With the help of the logic AND element 112, a pulse is generated whose trailing edge is in phase with the trailing edge of the output pulse of the frequency divider 99 and whose duration is half as long as the duration of this pulse. The generated pulse is intended for the formation of the zero position command for the buffer memory 13. At the multi-channel output 115 of the frequency divider 100, pulses of the second intermediate frequency are generated. These pulses are fed to the first input 116 of the AND element group II7, to whose second input the inverted signal c <from the input of the frequency divider 100 is given. This shortens the duration of the output pulses supplied by the output of the frequency divider 100. These impulses serve to

generation of clocked logical L signals that are used for interrogation the thyristor groups are determined.

After the decay of the next clocked Sienals to query any »thyristor group the pulse of the mentioned counting command follows, and then with a time delay necessary to finish the count the pulse of the zeroing command for the buffer memory 13 is given, whereupon the new clocked The interrogation signal for the next thyristor group begins. The one at the input channel from the frequency divider generated pulses are fed to the input of the frequency divider 101 ', at the multi-channel output 102 pulses of the third intermediate frequency appear. These impulses arrive to the input of the address command shaper 124 and are used to generate the actual signals "b".

From the single-channel output of the frequency divider 101, the pulses are fed to the input of the frequency divider 102, at its multi-channel output 123 low-frequency pulses appear that are used to generate the '.taktsignale "c" are determined.

The conjunction takes place in the address command former 124 of the above-mentioned signals, and thereby the possibility is given of commands for the structural units of the device to create.

To the input 8 of the selector 7 and via this to the input 10 of the display unit 11, commands of the following type arrive:
(cl + o2 + c3 + ... + 088). (bl + b2 + b3 + b4 ^> ). (al + a2 + a3 + ... a8).

At the output 42 of the control unit 9 is with after a delay the command c <.g is issued. From the exit 43 to input 48, the count command oc.g and commands for zeroing the following are sent via two lines Kind given:

(cl + c2 + c3 + ... + c8) .b4.aO. From exit 22 get to the Input 21 of memory block 19 the following commands:

(cl + c2 + c3 + ... c8) b4.a9. Commands of the following type are fed from output 44 to input 49 of memory block 19: c9 .bl. (a2 + a3 + a4 + ... a9) i

.,. a9);
O9 »b3. (A2 + a3 + a4 +." .. a9).

From output 45 to input 50! Are zeroed Orders of the following type are given: o9.b4.a9j o9. (bl + b2 + b3) .al. From the exit 41 are via the entrance 40 of the memory block 19 entered the following commands: K.c9. (Bl + b2 + b3) .aO. Pur the entrance 36 is the Control command K determined. From output 46 on the display unit 30 commands of the type c9. (bl + b2 + b3) .al given.

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Claims (6)

Psfsrffafiwalte BEETZ & PARTNER 53o-33.261P 'Jan. 22, 1982 Steinsdorfsjfc 10, fiOOQ Munich 22 Vsesojuzny Elektrotekhnichesky Institut imeni V.I.Lenina Moscow, USSR PATMiDANSER (JCHE: lJ device for operational control of thyristors of a high-voltage valve with - According to the number of thyristors built-in thyristor voltage sensors, which are made with the help of light guides to the inputs of a for converting light signals are connected to certain transducers (light signal transducers) in electrical signals, - a buffer storage where the input with the Output of the mentioned light signal converter and the inverted one Output with a display unit to display the Number of failed thyristors and with a circuit arrangement are electrically connected to protect the high-voltage valve against breakthrough, and - one electrically connected to the light signal converter Selector whose address input to a control unit is connected and its output on a display unit to display the numbers of failed thyristors, j is indicated by - the connection of the selector input (6) with the Output of the light signal converter (4) and the selector out-530- (P 89..572-E-GD-E ganges with the input (12) of the buffer memory (13) and duroh - an OR gate block (14.) »in which the input (15) at the corresponding output of the buffer memory (13) and the output at the data input (18) of the display unit (11) to display the numbers of failed thyristors lie, - A summator (16), whose input (17) is connected to the output of the OR gate block (14), - A memory block (19) j in which the inputs ·. (20, 21, 40, 49) to the output of the summator (16) resp. are connected to the outputs (22, 41, '44) of the control unit (9) and the output (23) to the second input (24) of the OR gate block (14) is, - a comparator (25), the inputs (26, 27) of which the second output of the summator (16) or to the address read output (28) of the memory block (19) connected and its output on the display unit (30) for display the number of failed thyristors and the circuit arrangement (32) for protecting the high-voltage valve lies before breakthrough. 2. Device according to claim l, gekennzeiohnetdurch - A unit (33) for data control at Eins eiben, in which the inputs (34, 35) to the output of the display unit (30) to display the number of failed thyristors or to the output of the circuit arrangement (32) for Scautz des High-voltage valve are connected before breakthrough and the output is connected to the control input (36) of the control unit (9 ") and to the control input of the circuit arrangement (32") to protect the high-voltage valve from breakthrough. 3. Device according to claim 1 or 2, gekennzeichne.t by an additional comparator (37) »whose input (38) is connected to the output of the Summator (16) is connected and the output of which is connected to the input (39) of the summator (16). 4. Device according to / claims 1 to 3, since - characterized in that the summat or C16 ") - A combination sensor (52) with N stages each stage contains several elementary main summators and additional summators (56, 57i 58, 59> 60, 61, 62, 63 ^ includes, where Number η _, _, - one / of inputs of the elementary summators as single-digit inputs of the combination summator (52) to serve, - the S outputs of the main summators and the additional ones Summators (56, 57, 58, 59) of the first stage Nl to the inputs of the additional elementary summators (59) are connected to the same stage, - the S output of the additional summer of each stage forms the output of the combination summer (52), - the P outputs of each stage to the inputs of the elementary main summators (60, 61, 62) of the following Stage are switched, - the last stage N4 only a term ar s ummat or (63) whose P and S outputs serve as outputs of the combination summator (52), - the summator (16) also has a code converter (53) whose inputs are at the outputs of the combination summer (52) lie, and - a storage element (54) flip-flops (64, 65, 66, 67) according to the number of stages N , in which the I and K inputs are connected to the paraphase outputs of the code converter (53), but the C inputs are interconnected and form the control input (48) of the summator (16), while the Q output of each flip-flop (64, 65, 66, 67) is at the input of the elementary summator of the stage corresponding to the value of the flip-flop and serves as the output of the suinmator (16), and - Includes a counter (70) in which the counting inaa ^ b (69) is connected to the carry output (6ü) of the code converter (53), the second counter input (71) with the C outputs of the flip-flops (64, 65, 66, 67) combined switches 1st and the outputs as outputs of the Sumniator (16) serve, and - Contains a logic OR gate (72), the inputs of which with the control unit (9) and with the output of the additional! Comparator (37) are connected and its output to the reset inputs of the flip-flops (64, 65, 66, 6?) And the counter (70). 5 _f device according to claims 1 to 4, characterized in that the memory block (19) is constructed as a series connection of a write elector (73) »a memory unit (74) and a read elec ^ ors (75), the data inputs of the Read selector (75 ") are connected to the second inputs of the logical OR circuits of the ODSR gate block (14). 6. Device according to claims 1 to 5 »d ad u r c h I denote that the comparator (25) - A comparison circuit (76) and one with this in series AND gate unit (77) contains, wherein f. the first inputs of each logical AND circuit at the corresponding address input (28) of the read selector (.75) in the memory block (19) and - the input of the comparison holding (76) with connected to the output of the combination sumniat or s (52) is. 7 · Device according to claim!, Characterized by the structure of the display unit (11) to display the numbers of failed thyristors with - An AND circuit group (84) in which the first Inputs of the AND circuits are connected to the outputs of the OR gate block (14), - a register (86) whose inputs are connected to the outputs the logical AND circuits (84) are connected, - A Leuchtanaeige (88), whose inputs (87) on the outputs of the register (86) lie, - A return pulse shaper (90), in which the Input (91) to the second inputs of the logic UJH) circuits (84) is connected and the output is at input (89) for resetting the register (86), - A comparison circuit (93) ι whose first inputs connected to the address outputs of the selector (?) and whose output (92) is at the second inputs (9 * 0 of the logical AND circuits (84), - An arrangement (96) for specifying addresses of the thyristors to be monitored, the outputs of these Arrangement (96) to the second inputs (95) of the comparison circuit (93) are connected.