RU2486576C1 - Homogeneous computing environment for conveyor calculations of sum of m-n-digit numbers - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: homogeneous computing environment provides for parallel conveyor summation of m n-digit operands and comprises identical cells made of 2 double-input elements AND, 2 double-input elements EXCLUSIVE OR, a double-input element OR, an element NOT, 3 information triggers, at the same time the number of columns in the homogeneous computing environment is equal to p, where p=log₂m, and the number of cells in the j column is equal to m/2^j.

EFFECT: higher efficiency due to parallel-conveyor separation of bits of transfers of a digit cut of summands into the following digit cut and generation of digits of an unknown sum at every stage of device operation.

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Description

The invention relates to computer technology and is intended to build a homogeneous computing environment that performs the function of summing m n-bit operands by parallel-conveyor allocation of bits of the bits of the bits of the slice of the terms to the next bit slice and the formation of bits of the desired amount.

A homogeneous computing environment is a regular structure consisting of identical cells connected to each other, performing a certain function.

A homogeneous computing environment cell is an element of a regular structure.

A bit slice is a set of bits of the i-th position from m operands participating in the operation.

A device for summing single-digit numbers is known - copyright certificate SU 1023922 A1 dated 06/27/2000. The device comprises a binary adder block that contains groups of one-bit binary adders, wherein the one-bit binary adders of each group form a pyramid of one-bit binary adders, the inputs of the one-bit binary adders of the first group are connected to the inputs of the first group and the first input of the second group of the unit, the inputs of the one-bit adders of each subsequent group are connected with the transfer outputs of one-bit binary adders of the previous group and the corresponding input of the second group of the block, outputs ka Each group of one-bit binary adders is connected to the corresponding outputs of the block. The disadvantage of this device is that it processes numbers in a binary decimal system, and the pipeline principle of processing information is not implemented, which significantly reduces the speed of the device.

A technical solution is known for a parallel asynchronous adder, patented as an invention - patent RU 2097826 C1 of 11.27.1997. The device contains: n blocks 6 ₁ -6 _n parallel processing of bit slices, n-1 shapers 7 ₁ -7 _n-1 pulses, starting shaper 7 ₀ pulses, element 8 OR NOT, each block 6 contains 4 keys 1-4, having outputs with a high impedance state, and an arithmetic half-adder 5. The disadvantage is that the device does not implement the conveyor principle of information processing, which significantly reduces the speed of the device.

Closest to the claimed solution is the technical solution of the device, built on the basis of the pyramidal method of summing numbers - doubling (http://parallel.ru/fpga/Summ2/SummColamo.html#pirsum). Being one of the fastest devices for summing m operands, the device has significant hardware costs, which leads to a decrease in reliability, while the conveyor principle of information processing has not been implemented, which would further increase its speed.

The technical result of using the device for pipelining calculations of the sum of m n-bit numbers is to increase performance by parallel-pipelining the allocation of bits of the bits of the bits of the terms cut into the next bit section and the formation of bits of the desired amount in each cycle of the device. Also, as the number of participating terms increases, the number of cells in a homogeneous computing environment increases linearly.

Description of the technical solution of a homogeneous computing environment for pipeline computing the sum of m n-bit numbers. The inventive device consists of m-1 cells of a homogeneous computing environment, which are combined by regular links.

A homogeneous computing environment cell consists of two two-input AND elements, two two-input EXCLUSIVE OR elements, one two-input OR element, one NOT element, three information triggers.

The cell synchronization input is connected to the synchronization inputs of the first, second trigger and the element NOT, the output of which is connected to the synchronization input of the third trigger. The first and second information inputs of the cell are connected respectively to the first and second input of the AND element, the output of which is connected to the second input of the OR element. The first and second information inputs of the cell are connected respectively to the first and second input of the first exclusive OR element, the output of which is connected to the first input of the second exclusive OR element and the first input of the second AND element, the output of which is connected to the first input of the OR element, the output of which is connected to the information input the second trigger, the output of which is connected to the information input of the third trigger, the output of which is connected to the second input of the second AND element and the second input of the second element EXCLUSIVE OR, the output of which is connected to the information input of the first trigger, the output of which is the information output of the cell.

Figure 1 shows the functional diagram of a cell of a homogeneous structure, where 1, 2 are information inputs; 3 - synchronization input; 4, 6 - elements EXCLUSIVE OR; 5, 7 - elements And; 9, 10, 13 - information triggers; 12 - information output. A cell can be implemented on any element base that has the ability to represent Boolean functions, including: extra-large integrated circuits and programmable logic integrated circuits (FPGAs). An implementation option in the programming language of the equipment VHDL shown in figure 2.

In the claimed technical solution, a homogeneous computing environment is a collection of cells that are combined as follows.

The synchronization input of a homogeneous computing environment is connected to the synchronization inputs of all cells. An array of initial m n-bit binary numbers is processed in the form of n binary m-dimensional vectors, where m must be a multiple of a power of two, the first and second information inputs of the cells of the first column of a homogeneous computing environment are connected to the corresponding bits of the m-bit input vector. The information output of each (i-1, j) -th and (i, j) -th cell is connected respectively to the first and second information input of the (i / 2, j + 1) -th cell, and i∈ [2, m / 2 ^j ] and i takes only even values.

The number of cells in the jth column of a homogeneous computing environment is m / 2 ^j , the number of columns in a homogeneous computing environment is, where p = log ₂ m. The information output of the cell of the last column of a homogeneous computing environment is the output of the circuit from which the result is taken.

Device Description

The device provides parallel-conveyor addition of m n-bit operands, where a cell of a homogeneous computing environment (figure 1) implements the following system of logical functions:

s (t) = a⊕b⊕p (t-1);

p (t) = (a & b) v (p (t-1) & (a⊕b)),

where a, b are, respectively, the state of the signals at the inputs 1 and 2 of the cell;

s (t) - signal state at the output of 12 cells;

p (t) is the feedback of the transfer signal inside the cell.

Each ie binary positional term can be represented as a sequence of bits A _i (a _n , a _n-1 , ..., a ₁ ), where n is the bit capacity of the number, i∈ [1, m]. Then m terms can be represented as a matrix:

$$\left(\begin{array}{l}{a}_{\mathrm{one,}n},a_{\mathrm{one,}n-\mathrm{one}},...,a_{\mathrm{1,1}}\hfill \\ a_{2n},a_{2n-\mathrm{one}},...,a_{2.1}\hfill \\ ...\hfill \\ a_{m,n},a_{m,n-\mathrm{one}},...,a_{m\mathrm{,one}}\hfill \end{array}\right)$$

(a_1j,a_2j,…,a_mj) $$$$

являются входными векторами, которые поступают на обработку в однородную вычислительную среду.Matrix Columns with Elements $$$$

(a _1j , a _2j , ..., a _mj ) $$$$

are input vectors that are processed in a homogeneous computing environment.

In each cycle, the synchronization signal is supplied to the synchronization inputs of all the triggers. The first and second information inputs of the cells of the first column are supplied with the corresponding bits of the bit slices, and each subsequent bit slice is fed to the next clock cycle of the device. With each subsequent advance, the number of bits of the vector is halved. This continues until the number of bits of the transmitted vector becomes equal to unity. Having passed all the columns of a homogeneous computing environment, the number of bits in the i-th bit slice is reduced to one, this bit is the i-th bit of the desired sum of the source operands. The resulting units of transfers by feedback in the cell are transferred for processing to the next bit cut.

As a result, through the log ₂ m clock cycles of the device, the least significant bit of the sum m of n-bit numbers is formed, and m must be a multiple of a power of two. After which the pipeline is full and the result bits are available at the output of the device every subsequent clock cycle. Since in each step of the device’s operation, the vector is transferred to the matrix column adjacent to the right, the following vector can be fed to the input of the device at each clock step. Thus, the device implements the conveyor principle of information processing. Since the longest signal propagation chain in a cell has three logical elements, the signal propagation delay time is 3 · t, where t is the signal delay time by one logical element.

If we take for the summing time a pair of n-bit numbers of n-clock cycles of the device, then the time to calculate the sum in the proposed device in the pipelined mode is m ticks, while the summation time in the pyramidal way is p · n ticks, where p = log ₂ m . Thus, the speed of the device based on the described method is log ₂ m times higher compared to the speed of the device based on the well-known iterative summation method. For example, with the number of terms m = 64, the speed of the proposed device is more than 8 times.

Figure 3 presents a structural diagram of a homogeneous computing environment in general form based on a cell of a homogeneous structure, intended for pipelining calculations of the sum of m n-bit numbers, where CELL are cells of a homogeneous structure, information inputs X ₁ -X _m , information output Y. Cell can be implemented on any element base that has the ability to represent Boolean functions, including: extra-large integrated circuits and programmable logic integrated circuits (FPGAs). An implementation option in the programming language of the VHDL equipment is shown in Fig.4.

Claims (1)

Homogeneous computing environment for pipelining calculations of the sum of m n-bit numbers, consisting of cells made of two two-input AND elements, two two-input EXCLUSIVE elements, one two-input OR element, one NOT element, three information triggers, the cell synchronization input is connected to the synchronization inputs the first, second trigger and the element NOT, the output of which is connected to the synchronization input of the third trigger, the first and second information inputs of the cell are connected respectively to the first and second inputs the ode of the AND element, whose output is connected to the second input of the OR element, the first and second information inputs of the cell are connected respectively to the first and second input of the first EXCLUSIVE OR element, the output of which is connected to the first input of the second EXCLUSIVE OR element and the first input of the second AND element, the output of which connected to the first input of the OR element, the output of which is connected to the information input of the second trigger, the output of which is connected to the information input of the third trigger, the output of which is connected to the second input the second AND element and the second input of the second EXCLUSIVE OR element, the output of which is connected to the information input of the first trigger, the output of which is the information output of the cell, where the synchronization input is connected to the synchronization inputs of all cells, the array of initial m n-bit binary numbers is processed in the form of n binary m-dimensional vectors, and m must be a multiple of a power of two, the first information input of the cells of the first column of a homogeneous computing environment is connected to the odd bits of the n-bit input vector, the second information input of the cells of the first column of a homogeneous computing environment is connected to even bits of the m-bit input vector, the information output of each (i-1, j) and (i, j) -th cell is connected respectively to the first and second information input (i / 2, j + 1) -th cells, with i∈ [2, m / 2 ^j ] and i taking only even values, the number of cells in the j-th column of a homogeneous computing environment is m / 2 ^j , the number of columns is uniform computing environment is equal to p, where p = log ₂ m, the information output of the cell of the last column is homogeneous The computational medium is the output of the circuit from which the result is taken.

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