CA1191204A - Device for monitoring thyristors of high-voltage valve - Google Patents

Abstract

A b s t r a c t A device for monotoring thyristors of high-voltage val-ve comprises thyristor voltage detectors coupled via light guides to a buffer storage unit through a selector, Also pro-vided are an OR gate assembly, an adder, a memory unit, and a comparison unit, which are placed i series and coupled to a control unit. The OR gate assembly is connected to the buffer storage unit which is also coupled to the control unit.
A second input of the comparison unit is connected to a second output of the adder, while its output is connected to an indicator signalling the quantity of disabled thyristors and to a unit protecting the high-voltage valve against breakdown.
The selector is also connected to an indicator signalling the numbers of disabled thyristors. The hereinproposed device features high reliability in determining the quantity of disabled thyristors.

Description

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Field o:~ the Invention The present invention relate~ to high-voltage conversion equip;3ent and in particular to a device :~or monitoring thyris-tors o~ a high-voltage valve.
The invention ma~ be used for monitoring various compo-nents o~ high-voltage apparatus; more spacifically, for mo-nitorin~ thyristor~ of a high-voltage valvs used for HVDC tran-smi~sion.
Prior Art High-Yoltage valve are known to include a ~airly large number o~ seris~-connected thyr~tors. Failure of a certain number o~ ths thyristors may render the valve un~0rvioeable. '~o enhanc~ reliability, hîgh-voltage valve compri~e more thyris-tors than i~ actually needed in operation. ~here i~ still a probability that the number of disabled thyristor~ may, at a certain stage in operation, exceed the number o~ the additio-nal thyri~tors. To prevent ~ailure and also any condition that might cause it, t~ high-voltage valve i~ provided with a de-vide ~or monitoring thyri6tors, which i9 capable of ~urni~hing an alarm signal and, a~ the numb~r of di~abled thyristor~ in-creases, a con~and to turn off the high-voltage valve.
High reliability and adequate noi~e immunity con~titute the basic requirements ~or a thyri~or tester sinc~ ~ailurc of a high-voltage valve or itB turn-off ~ithout due reason may cause disconnection of loads or a ~ault in the power supply system.
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Known in the art is a device for monitoring thyristors of a high-voltage rectifier (cf. FRG Pat.
No. 1,g41,989), which comprises two probes installed in a manner allowing their movement along guides. The guides mo~nt electrical contacts connected to anodes and cathodes of the thyristors. The leads of the probes are connected to an indicator signalling ser-viceable condition of the thyristors. ~hen the thyristors are checked for condition, the probes mov-ing along the guides are connected to the anodes andcathodes of the thyristors under test. The indicator will then signal the condition of the thyristors.
The high-voltage valve must be turned off before checking the thyristors for conclition. In the known device no information is available on the condition of thyristors while a high-voltage valve is in operation, which is an apparent disadvantage since between scheduled checks the number of dis-abled thyristors may exceed the number of additional thyristors. Thus, failure of the high-voltage valve may result. So, the aforesaid device does not allow checking condition of thyristors while a high-voltage valve is in operation.
Also known in the art is a device for con-tinuously monitoring thyristors (cf. Swedish Pat. No.336,749, Allmannu Svenska Electris]ca A.B., July 12, 1971), comprising a first resistor placed in parallel with all the thyristors comprised in a high-voltage valve, and a second resistor placed in parallel with one o~
the thyristors (reference thyristor). The resistors are connected in series with rectifier cells who-~ ~ 3 ~ 2 V~

se leads are connected to a mea~uring instrument and/or anelectronic amplifier. As any of th0 th~:ristors ~ails, the instrument pointer deflect~, the amount o~ deflection being proportional to the number of disabled thyristors. The electronic amplifier furnishes a signal to a ~ignalling and protection cixcuit.
The .~oregoîng device ha~ low reliability and inadequate accuracy in determining the number of disabled thyristors due to the fact that voltage is unequally divided among the thy-ristor~ comprised in the high-voltage valve. Furthermore, the devics i9 rendered completely un~erviceable when the re-.~erence thyristor fail~. Another di~advantage o~` the devio~
i~ that it ~urnishes no in~ormation as to which of the thy-ristors has failed.
Another known dev~ca -~or monitori~g thyristors of a high-voltage recti~ier comprises voltage detectors whose num-ber corresponds to the number o~ thyristors, said voltage detectors con~ected via light guides to the inputs of a unit converting light signals into-electrioal ~ignals,-the OUtpllt o~ which ie electrical~ coupled to the input o~ a bu~er storage unit whose inverting output i~, in turn, electrically coupled to an indicator signalling the quan-tity o~ di~abled th~ristors and to-~ unit p~otecting the high-voltage valve against breakdown, ~he device being also provided with a se-Iector ~le:ctricall-y coupled--to ths unit Gonvertin& ligh-t sig-nals into elsctrical signalH9 an address input of ~aid ~elec-tor heing connected to a control unit, while its output i~4 --connec-ted to an indicator signalling the numbers of-disabled thyristors (cf. Swadish Pat. No. 365,915).
In tha a~ore-mentioned device the outputs of the buffer storage unit are connected to the selector and a re~et input is coupled to a re~pective output of the control unit. The -device also includes an indicator control pulsa ~haper con-nected to the input~ of the indicator signalling the quantity of disabl~d thyristors and an indicator ~i~nalling the numbers of disabled thyristors. Pulses furnished by the voltage gene-rators employing thyri~tor~ are fad through light guide~ to the oomponent~ of the memory unit to be ~tored. ~he ~lec~or i8 used to tran~mit sig~als ~rom th~ memor~ unit to th~ indi-cators in the form of narrow pul~es.
~ he signals are tran~mitted succes~ively without any check~-made. Moreover, the oorr~ctness o~ the data---obtained i8 not co~irmed. ~ailure--of---the-~device causing ~aults in the po~er 6upply system may not b~ detected in time, Beside~, the afo~lesaid deviGo ha~ inadequate noi~e immunity since it io de~ign~d for u~e at a d-c convar~ion ~ubstation wherein the noise level i8 fai~ly high. ~ailure or spurious re~ponse o~
the device proGes~ing the information as a ~equence of narrow pulses will distort the re~ult~. Furthermor~, the foregoing device 5upplies ~al~e information, say that all the thyristor~
are broken down when in-emergency-the voltage at-the v&lves equals zero for a ~hort time.
Brie~ Description of the Invantion-It i~ àn object of the--pre~snt invantion to pro~ide a device fo~ monitorin~ thyristors of a high-vo~-tage ~alve ~aturing high reliablli-ty in determining the number of di-sablad thyristors.
~ he foregoing-object i9 accomplished by that in a device ~or monitoring thyristors of a high-voltage valve comprising voltage detectors who~e number corr3sponds to the number o~
thyristors, said voltage dstectors connected via light guide~
to the inputs of a unit co~verting light signals into electri-cal signals, the output of said unit being electrica:Lly coup-led to a buf~er storage unit who~e inverting output is, in turn, electrically coupled to an indicator signalling the quantity o~ di~abled thyri~tor~ a.nd to a unit prot~ctlng the high-voltage valve agains-t brcakdown, and also a selector electrically aoupled to the unit converting light ~ignals in-to electrical signals, an address input o~ said selector being connHcted to the control unit-, while it3 output i~
connected to the indicator signalling the numbers of disabled -thyristors, according to the invention, the input o~ the se-lector ia connected to the output o~ the unit converting light 3ignal~ into eleotrical signals, while its output is ooupled to the input o~ the bu~f~r storage unit, the device being also providsd with an OR gate a~sembly having its input connected to a respsctive output of the buffer storage unit and it3 0utput coupled to a---data-input o~-the---indicator ~ig-nalling the number~ o~ di~abled thyri~tors, an adder whose input is oonnected to the output o~ the OR gate as~embly, a 34~

memory uni-t having its inputs connected respectively to the output of the adder and to the outputs of the control unit and its output coupled to a second input of the OR gate assembly, a compariso:n unit having its inputs connected respectively to a second output of the adder and to an address read output of the memory unit and its output coupled to the indicator signall-ing the quantity of disabled thyristors and to the unit protecting the high-voltage valve against break-down.
In accordance with a further particularembodiment of the invention there is provided a device for monitoring thyristors of a high-voltage valve.
The device includes thyristor voltage detectors having outputs, the number of the detectors corresponding to the number of the thyristors. Liyht gulcl~, whos~
number corresponds to the number of the detectors,have one end connected to a respective voltage detector.
The unit converting light signals into electrical signals has a group of inputs connected to the second ends of the light guides. The unit convertiny light signals also has an output, and a selector has an input connected to the output of the unit converting light si.gnals into electrical signals. The selector also has an address input and first and second outputs.
A buffer storage unit has an input connected to the first output of the selector, a reset input and an output. An OR gate assembly has a first input con-nected to the output of the buEfer storage unit, a second input and an output. An indicator signalling the numbers of disabled thyristors has an address ~ input connected to the second output of the selector and a data input connected to the output of the OR
gate assembly, and an adder has an input connected to the output of the OR gate assembly, a control unit and first and second outputs. A memory unit ~ 3~1 has a ~irst input connected to the fixst output of the adder, a second input, a reset input, a control input, an output connected to the second input of the OR
gate assembly and an address read output. A compari-son unit has a first input connected to the addressread output of the memory unit, a second input con-nected to the second output of the adder, and an output.
~n indicator signalling the quantity of disabled thyrist-ors has an input connected to the output of the com-parison unit, a reset input, and an output. A unitprotecting the high-voltage valve against breakdown has an input connected to the output of the comparison unit, a second input, a reset input and an output.
A control unit has eiyht outputs and a control input and is connected via the first OUtp~lt to t~e acldres~
input of the selector, via kh~ second output to t~l~
reset input of the buffer storage unit, via the third output to the control input of the adder, via the fourth output to the second input of the memory unit, via -the fifth output to the control input of the memory unit, via the sixth output to the reset input of the memory unit, via -the seventh output to the reset input of the unit protecting the high-voltage valve against breakdown, and via said eighth output to the reset input of the indicator signalling the quan-tity of disabled thyristors~
Advantageously the device includes a unit forchecking recorded information, the inputs of which are connected respectively to the out.put of the indicator signalling the quantity of disabled thyristors and to the output of the unlt protecting the high-voltage valve against br.eakdown, while its output is coupled to the control input of the control unit and to the control input of the unit protecting the high-voltage valve against breakdown.

. - 7a -Desirably the device incorporates an addition-al comparison unit having its input connected to the output of the adder and its output coupled to the reset input of the adder.
Preferably the adder represents a combina-tion adder having N stages, each of which includes a series of main and additional elementary adders, n inputs of which act as one-bit inputs of the combina-tion adder, S-ou-tputs of the main and additional adders of the first stage being connected to the inputs of the additional elementary adders of the same stage, - 7b -~, ~ }

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one S-output o~ the additi.onal adder o~ eacn stage serving as tke output o~ the combination adder~ while a P-output o~
each stage and subsequent stages is connected to the inputs o~ the main elementary adder3 o~ the next stage, the last ~tage comprising one elementary adder, the P- and S-outputs of which act as the outputs o~ the combina-tion adder, the adder ~eing also provided with a code converter having its inputs connected to the outputs of tha combination add0r, and a storage cell composed of flip-~lops whose number co-rresponds to the number o~ the ~tages, J- and K-irlput~ o~
~aid flip-~lops being conneo-ted to paraphase output~ of the code converte.r, C-input~ o~ the flip-flops b~ing comblned and acting as the-control input---of the adder9 a Q-output of each flip~lop being connectsd to the input o~ the elemen-tary adder of the stage corresponding to the flip-fIop bit and acting-as the output of the adder, a counter having one count input connected to the carry ou-tput o~ the ood~ conver-ter, while its sscond count input i~ combined with the C-inputs o~ the Plip-~lop~, the output~ thereof ~erving as the adder output~, and an OR gate having its lnput~ conn~oted to the control unit and to the output o~ the addltional com-pari~on unit and it~ output.coupled to the re~et-input~ of the flip-flops ~nd the counter~
It i~ of advantage that-the memory unit should lnclude such aeries-oonnected--¢omponen-t~ as a writ-e ~electorj a storage ass~mbly7 and a read~sel00tor, data-outputs~~o~--~th~_r~ad.

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selector being connected to second inpute of the 0~ gates comprised in tha gate assembly, Prefe~ably the compari~on unit incorporates such ~eries--eonnected components as a eomparison circuit and an ~D gate assembly, first inputs o~ each of said gates being eonnseted to a ~espective address output o~ the read seleetor o~ thc memory unit, -the input o~ the eompari~on cireuit being coup-pled to the output o~ the eombination adder.
Advantageously the indieator signalling the numbers of disabled thyri~tors ¢omprise~ a group of AND gato~ whose .first inputs are eonlleeted to the output~ o~ the or~ ~te as~embly, a r~gister eon.neeted via its outputs to the output~
of the AND gate~, a llght indicator having its inputs eonnee-ted to the outputs o~ the register, a elear pulse shaper having its input conneeted to seeond inputs o~ the AND gates and it~
output eoupled to the reset input of the reeister, a eompari-son circuit having its first input~ conneeted to the address outpu-ts of the se~eotor and it~ outpu-t eoupled -to seeond in-put~ o~` the AND gate~, and a unit ~or ~fltting th~ addre~ o~
the thyri~tors under test, the outputs of said unit being eonnected to ~seond inputs of the compari~on eireuit.
In the deviee forming the ~ubjact of the pre~ent inven-tion oonneetion o~.the.seleetor to the output of the unit eonverting light signals into eleet~ical ~ignals and to the buffer s-torage unit permits reduoing the number o~ ~torage eells whoss noise immunit~ i~ lo~ as eompared with eombina-_ g _ tion circuitsu ~ less0r number o~ storage cells in tha thy-ri6tor interrogation circuits allows increasing noise immu~
nity a~d operational reliability of the dcvice. The inclusion of gate~ pxevents the use of another adder whereby the opera-tional reliability o~ the devica ~ill be incxeased. The use of the adder makes it possible to count disabled thyristors.
~he calculation is ba~ed on in~ormation obtained by the use of non-position code and tha result i8 in the binar~-decimal code. This permits counting the n~mber of di~abled thyris-tors using highly reliable computing elements known in the art 9 a Peature ~nhanoing operational reliability o~ the devia0~ ~ho u~e of a memory unit permit~ repeated surYey o~ thyristors compriaed in a rectifier and statistical processing of the data obtained~ say by applying polling techniques, a Pactor incr0a~ing operational reliability of the device. ~he--provi-sion o~ a compari~on unit makes it possible to reject data obtained due to spurious response of the device, say spurious response o~ thyristor voltage detector~, which i9 ano-th0r ~actor increasing reliability. Th~ utllization o~ a unit for checking recorded information makes it possible to ascertain the correctness of records in storage registers o~ an indicator .
signalling tha-quan-tity o~ clisabl-ed-thyristors and a unit protecting a -valve-agains$ breakdown.--~h~-unit fo~ checking recorded in~ormation also precludes spuriou~ re~ponse of th~
protection unit when the device fails or function~ improperly, ~ 2()~

which enhances reliability. The use of an additional compa-rison unit ma~es it possible to psrform a reset operation in the event of fal~e ~ailure of the who~e group of d0tectors.
Brie~ Description of Drawings The in~ention will now be describe~ further with refe-rence to specific embodiments -thereof, taken in conjunction ~ith the accompanying drawing~, whsrei~o ~ IGURE 1 is a block diagram of a device for monitoring thyris-tors of a high~v ltage valve according to the inven-tion;
~ 'IGURE 2 i~ a block di~lgram of an adder comprised in the devic~ acoording to the invention;
~ IGURE 3 depict~ circui-try o~ a comparison unit oomprised in the devica according to the inven-tion; and FIGURE 4 is a block diagram of an indicator signalling numbers of di~abled thyri~tors in-the device according to the invention.
Detailed De~cription of the Invention Referring to the drawings the deviee for monitorin~
thyristors of a high-volt~ge-valve oomprises thyrl~tor voltage d0tectors 1 (~IGURE 1) aonneeted via light guides 2 to in-puts 3 of a unit 4 conv~rting light signals into electrical signals. ~he thyristor voltage detector 1 represents a tran~-duoer converting voltage acros~ a -th~ristor 5 into-a corres~
ponding light signal. The number of the deteotors 1 is de-termined by the number of the thyristors 5 comprised in the high-voltage-valYe~ each detector-l being elect~ically-coupled to th0 anode and cathode of the re~pective thyristor 5~

' ' Tha multichannel output o~ the unit 4 converting light signals into elactrical ~ignals is connacted to an input 6 of a ~elector 7 whose address input 8 is coupled to the output o~ a control unit 9. The numbsr of the channels comprised in the unit 4 is determined by the number of the th~ristor vol-tage detectors 1 coupled thereto. The address output o~ the selector 7 is connected to an address input 10 of an indica-tor 11 signalling the numbers of disabled thyristors, The data output of the seleetor 7 is connected to an input 12 o~ a bu~er storage unit 13.
To cheak a hi.gh-voltagc valv~ oompriBi:ng in th~ h~rein described modification 256 thyri.~tors, the sel~ctor 7 includea 12 address bu~e~.
~ he device forming the subject o~ the pre~snt invention also incorporates an OR gate assernbl~ 14 whose input 15 is con-nected to~a-respsctiv2-output--of the bu~er storage unit 13 and an add~r 16 whose input 17 is ooupled to the output of the OR gat~ assembly.l4. r~he output o~ the assembly 14 is al~o oonnected to a data input 18 o~ the indicator 11 ~ignalling the numbers o~ di~abled thyri~tors. Al~o provided are a memory unit 19 having its inputs 20~ 21 connected respectively to the output o~ ~he adder 16 and to an output 22 o~ the control unit-9 and itB output 23 -couple'd to a second input 24 of the OR gate assembly 14~ and a ¢omparison unit 25 ha~in~ its in-puts 26, 27 ¢onnected respectively to the second output o~ the adder l6..and to an.addre~s-read-output-28 o~---th~ memory unit ~ 2~

19 and its output eoupled to an input '9 of an indicator30 signalling the quantity of disabled thyristors and to an input 31 of a unit 32 protecting the high-voltaga valve against breakdown.
~ o check reliability of sonveyed information a~ to the quantity o~ disabled thyristors, the devics in compliance with the invention oomprise~ a unit 33 for checking recorded in~ormation, inputs 34 and 35 o~ which are connectad respecti-vely to the output o~ the indicator 30 ~ignalling the quantity o~ disabled thyri~tors and to the outpu~ of the unit 32 pro-tecting the high-voltage valve again~t breakdown, while the output thereo~ i~ eoupl~d to a eontrol i~put 36 o~ the eontrol unit 9 and to the eo~trol input o~ th~ unit 32 proteeting the high-voltage valve again~t breakdown.
To preclude spurious response o~ the device in the event o~ a ~hort in the high-voltage--valve circuit o~ when ~oltage across its terminal~ is reduced to a value preventing dsliver~
o* signals ~rom the detec~ors 1~ provision is made ~or an additional compari~on unit 37 who~e input 38 is eonnaeted to the output of the adder 16, while the output thereo~ i5 ooupled to a set input 39 o~ the adder 16.
A reset input 40 of the memory unit 19 is eonneeted to an OUtpllt 41 of the eontrol unit 9. 0utputs 42, 43, 44, 45, and 46 o~ the -eontrol unit 9 are connected respactively to a reset input 47 o~ the buffer storage unit 13 to a eontrol input_48 o~ the-adder-161 to=a-eontrol-input 49 o~ the memory ~9 ~

unit 19 3 to a reset input 50 o~ the unit 32 protecting thehigh-voltage valve against breakdown, and to a reset input 51 o~ the indicator 30 si~nalling -the quantity o~ disabled thyristors~
In the pre~erred embodiment of the in~ention the adder 16 comprises such sarie~-connected components as a combination adder 52, a code converter 53 5 and a storage cell 54. ~he output o~ the storage cell 54 is conne ctad to a multi-bit input 55 o~ the combination adder 52. The combination adder 52 (.FIGURE 2) has N stages, where N i8 4.
The ~irst stage Nl includes ~our elementary adders 56, 57, 58, 59, thr~e of which ar~ main add~r~, whil~ the adder 59 ls an additional add~r; the seoond ~tag0 N2 include~ tw~ ele~
ment~ry thr~e-input adders (a main adder 60 ancl an additional adder 61); the third--sta~e N3 comprises one el0men-tary three-input-.adder 62 acting as a--main adder; and the ~ourth ~ta~e N4 comprises a two-input adder 63. Eight inputs of the elementary adders.56, 57, and 58 ~erve a~ the input 17 o~ the combination adder 52, while one o~ the inputs of the ~lementary adder 58 a¢ts as the first-bit input of the multi-bit input 55.
S-outputs of the adders 56, 57, and 58 are coupled to the lnput~
o~..the ele~ent~ry adder .59, whil0..P-output~ ther00~.are coupled to the inputs of the elementary add0r 60. One of the input~
of the elementary addsr 61 act~ as the seoond-b~t input o~
the multi-bit.input 55., while the two other inputs-are con-nected-to th~ P-output of the elementary-adder 59 and to the ~ 14 -2V~

S-output of the elementary adder 62~ One of the inputs o~ the elementary adder 62 serves as the third-bit input of the multi-bit input 55~ and -the two other inputs are connected to the P-~outputs of the elementary addexs 60 and 61. One input o~ the eiementary adder 63 serves as the fourth-bit input o*
the multi-bit input 55, while the other input is connected to the P-output o~ tha elementary adder 62.
The code converter 53 employ.ing widely kno~n linear deco-der circuitry is designed to convert a binary number code into a binary-decimal code. The conversion process involves sepa~
ration o~ ~ declmal carry æignal if the lovler~digit ~um at a given mome.nt ie equal to or exceeds ten. For example, the fi-gu.re 12 in the binary code i~ written as 1100 wher0by 0010 and a carr~ ~ignal appear at the output of the converter 53.
Th~ S-outputs of the elementary adders 59g 61, 62, and 63 and--the P--output o~.the adder 63 are. connect.~d to the input~
o~ the code converter 53 ~ho~e outpute i~ connected to the .
storage cell 54. ~he paraphase lower-digit outputs of the code converter 53 are connected to the J- and K-inputs o~
~lip-*lops 64, 65, 66, and 67 having a common control C-input and a reset R-input, which ~erve a~ the input 48 of th~ adder 16.
-An output 68 of the code ¢onverter 53 *urnishing a carry ~ignal is--connected--to-a oount---input 69 of-a-counte~---70 which is part o~ the storage celr 54. A second -Gount-input 71 of the .counter 70 iB combinèd with the control-G-input of J-~.

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flip-~lops 649 65, 66, and 67. The ras~t ~-input of the counter 70 i8 combined with the reset :R input o~ the J-K
flip-flops 6~i through 67 and connected to the output of an OR gate 72, one o~ its inputs serving as the input 39 of the adder 16, whila the other input ~cts as the second-bit input of' the tvJo-bit input 48.
The Q~output~ of the ~lip-flops 64 through 6~ are con-n~cted respectively to the first-; ~econd-, third-9 and fourth-bit inputs of th~ rnulti--bit input 55 of th~ combina tion adder 52. The Q-output~ o~ the J-~ flip-flop~ 64 through 67 and the Q--outputs o~ the oounter 70 serv~ as t~ output o~ the adder 16.
The memory unit 19 (FIGURE 1) comprises a write selector 73 whoae multi-bit input serves a3 the i.nput 20 of the unitO
The number o~ bits of the multi-bit input is conditioned by the code i~ proces~ing data in the addar 16. The use of the bina~y-decimal code is optimum since two decimal cligits as a whole represent an eight-bit computer syllable (byte) whioh i9 th~ primary unit o~ most o~ the prrsent-day microprocessor sy~tems.
The memory unit 19 also inoorporates a storage assembly 74 and a read ~elector 75 conxlected in s~ries with th~ ~elec-tor 73.
1`hs numb~r o~ the multi-bit inputs of the storage assembly 74 is d~termined by the numbsr o~ ~`egister~ contained in th~
assembly 74 and is chos~n--to provida su~icie~t averaging at ~ 2~)~

which spurious response of the valve doe~ not in~luence the data obtained during its Rarviceability check. In th3 prefe-rred embodiment o~ the invention the number o~ th2 regi~ter~
~not shown in FIGURE 1) in the assembly 74 i5 eight. The control input of the write selector 73 acts as the control input 21 of the memory unit 19~ In the p~e~erred embodiment of tho invention the ~rite salector 73, the ass~mbly 74, and the read ~elector 75 use widely known circuitry (cf.
Branka Soucek "i.licroprocessors and ~icrocomputers", USA, 1976 9 p~ 38 and "The Manual on Integrated Microcircult~"
edited by Tarabrin A.S., Moscow, the Energia Publi~her~, 1980, p~3~0.
~ he oomparison unit 25 (FIGURE 3) includes such oerie~--connected components a~ a comparison oirouit 76 and an AND
gate-assembl~ 77, ~he ~irst input~ of the AND gates act as the input 27 of the unit conne-o~-ed to tha addres~ outputs 28 of the read selector 75. The compari~on circuit 76 contains a b.inary-decimal decoder 79 who~e multi-bit input 80 ~erves as the input 26 of ths unit 25 and i~ oonnected to the output o~ the combination adder 52. The output~ o~ the binary-de-clmal decoder 79 corresponding to digit~ "5", "6", "7", "8"
used to shape a ¢omparison signal are conneoted to inputs 81-of--a multi-input OR gate--82. ~he output o~ said gate--is Gonnscted to seoond inputa 83 o~ the AND gats~.
~ he indicator 11 (FlGURE 4) signalling the numb~r~ o~
di~abled thyri~tsr~ . contains a group o~ ~ND gate3 84 having their first input~ connected to th~ outputs of the OR gatba~sembl~ 14 and their output~ coupled to asynJhronous input~
85 of a regi~ter B6~ The outputs of the regi~ter 86 are con-nected to inputs 87 of a light indicator 8~ (set of light--emitting diode~ in the preferxed e~bocliment o~ the invention)O
Connected to a re~et input 89 of the register 86 is a clear pulse shaper 90 whose input 91 i~ connected to an output 92 of a comparison circuit 93. The output 92 is also connect-ed to second inputs 94 of th~ AND gatss 84. The ~irst inputs o~ the compari~on circuit 93 are connected to the address outputs o~ the ~eleotor 7, whil.e ~cond inputs 95 are coupled to output~ o~ a unit 96 ~o~ setting the addrc~s o~ hi~h-volta-g~ valve thyri~tor~ und~r tH~t.
To convey in~ormation on disabled thyristors ov~r a ooup-ling channel to the computer, ths indicator 11 signalling the number~-o~-disabled--thyri B~ or~-- incorporat es additional units (not ~hown in FIGURE 4). The latter feature i~ not co~
vered by the appsnded claim~ and will not, there~ore, be di.scu~sed in detail.
The oontrol unit 9 (FIGURE 1) contains a clock pulse shaper 97 which, in turn, include~ a pulse generator 98 and ~our ~requency divider~ 99, 100, 101, and 102 representing binary- counters-with c~unt modules.101 101 4---and 9, and placed in ~eries with the binary-decimal decoder~
Th~ output of the generator 98 is connected to an input 103 o~ a NOT gate 104, -to an input.105 o~ a delay el~ment 106 9 ~ 2(~

and to the input of the frequency divider 99~ The one-channel output of the frequency divider 99 is connected to the input o~ the divider 100, to an input 10~ of a NOT gate 108, and to fi~st input~ 109 and 110 of AND gate3 111, and 112, res-p~ctively. A aecond input 113 of the AND gata 111 .i9 aormec-ted to the output of the NOT gate 104~ whils a second input 114 o~ the AND gate 112 i~ coupled to the output o~ the delay element 106.
The one-channel ou~puts of the frequ0ncy divider6 100 and 101 are connected to the input~ of the divider~ 101 and 102, respactively. A multi channcl output 115 o~ the ~re-qu~ncy divider 100 i~ connected to ~ir~t input~ 116 of a group o~ AND gates 117, second input~ 118 of which are oon-nected to the output o~ the NOT gate 108. Output~ 119 and 120 of tha AND gates 111 and 112, a multi.-channel output 121 of the group o~ the-A~D-gates, a~d multi-channel outpute 122 9 123 of the fr~quency dividers 101~ 102 are co~nected to lnputs of an addres~ command ~haper 124.
The addre~s command shaper 124 represents a ~et of AND
gate~ accomplishing conjunction of addx~s3 signalsO
Each channel of the multl-channel output 121 ~f the g~oup of the AND gates 117.is u~ed to pa~s clock puls9~ ConVentiQnal-ly~designated as al, a2, ...a9, aO. Similarly~-each channel o~
th~ multi-channel outputR 122 a~d 123 o~ the ~r~quency divi-ders 101 and 102 iB used to pa~s clock pul~es--con~-entionally designat~d a~ bl, b2, b3, b4, and=cl, ~29 c3,-...c9~ c re6p~¢tively, In order to improve the ability of the devic~ to re~pond more quickly 9 it is po~sible to increa~e the numb~r of cells o~ the butter storage unit 13, to simplify the seleGtor 7, to arra~g0 an~dditional selector betweell the unit~ 13 and 14 o~ the OR gate assembly (~ot shown in ~IG. 1).
Th~ hereinproposed dsvice ~or testing thyristora of a high-voltaga valve opera~es in the ~ollowing man~er.
On application o~ voltage to tha high-voltage valve, the thyristor ~oltage detectors 1 (~IGURE 1) emit light pulaea. These pulaea ar~ fed via the light guide~ 2 to the unit 4 converting lîght aignala into electrical ai~nals~
wh~rein the pul~es ~re again converted into electrical signals. I~ ~11 the thyrlstors 5 are serviceable, the num-ber o~ pulses at the output o~ the unit 4 will equal the num-per of the thyristors 5 in th0 recti~ie~ If the thyristor 5 is broken dow~ no pulse~ are presant at the output o~ the de-tector 1. ~rom the output o~ the unit 4 the electrioal pul-~e~ are ~ed to the lnput 6 of the ~ele~tor 7, the number of theae pulses being datermined by the number of ~.rviceable thyri~tor6 5~ ~he address input 8 o~ the ~elactor 7 aocepta through twelvs buse~ an-addreas signal ~rom the con-trol unit 9, ~aid signal representing a combination of two pul8e8 al, a2, ~3,. .~,a8- and bl~ b2, b3, b4. Upo~ receipti. of the signal 9 the group o:E the thyristor~ 5 i~ conne ctad to the ~u:~fer sto.rage unit 13. In-the pref~rred embodimant of the inverltion-the-number o:~ the th~.ri~tor~3~5 in--th~: group is eight.

2n~

The ~ame combination of pulse~ a and b i~ applied ~o theinput 10 o~ the indicator 11 ~ignalling the number~ o~
disabled thyri3tors.
The input 12 of ths buffex ~tora~e unit 13 receives a ~roup of ~et and reset signals, the set ~ignals signalling the broken-down condition of the thyristors 5 of the high-vol-tage rectifier. ~hese short qet signal~ are written into the register o~ the bu~er storage unit 13. From the output o~ ~aid unit the above ~ig~al~ are ~ed through the OR gate as~embly 14 to the input 17 of the adder 16 and ~imultaneou~ly to the data input 18 of the indicator 11 signalling the numbers of di~abled thyristor~.
~ he in~ormation oonvey~d a~ a ~et o~ ~et arld res~t ~gnal~
i~ coded in the combination adder 52. The in~orrnation ~upplied ~rom the output of the adder 52 to the input of the code conv~rter 53 represent~ the number o~ set signal~ i~ the binary code. ~he opera-tion of~the code converter 53 will be da~cribed-below. ~he output signals of th~ code converter 53~
are ~ed to the storaga cell 54.
Ne~t, a buf~er ~torage olear ~ignal is applied ~rom the control unit 9 to the input 47 of the unit 13 whercupon the addre~ signal at the input 8 of the selector 7 changes and the~-xecording o~--data ~rom th~ ~eoond~group---o~ thyri~tors be--gin~. ~he ~um of data obtai~ed i~ surveying the two groups o~-th~ristor~ writte~ i~to the ~torage-:cell--54. The re cordlng is accomplished by the use of the binary-decimal code.
After all the g~oup~ o~ the th~ri~tors 5 in~the high-voltage - 2~ -rectifie~ have been ~urvsysd (32 in the pr~ferr~d embodime~t o~ tha invention), a oontrol signal i3 fed from the output 22of the control unit 9 to the input 21 of tha memor~ unit 19.
Upon receipt of the signal, the number in the binary-decim-al code is rewritten ~rom the storage cell 54 into th0 re~-gist~r o~ the storag~ assembly 74 o~ th.e unit 13 by maans o~ the ~elector 73. Thereafter 3 ~ignal clea~ing the storaga c011 54 is applied ~rom the output 43 of the co~t~ol unit to the input 4B of the adder 16.
After the obtained in~ormation is writtcn into the first r.egister of ~he storage assembly 74, all the groups of the thyri~ors 5 in the high volta~e valve are being surveyed r0-p0atedly, The number o~ disabled thyristor~ i~ oount~d by th~
storage cell 54 and rswritten into the s~cond r~gister o~ the ~torage a~sembly 74. Next 3 the-third and ~ubsequent register~
of the-storag~ ~saembly 74 are loaded. In the prefsrred cmbo-diment o~ the in~ention the number of registe~3 in the stora-.
g9 a~eembly 74 i~ eight.
The successive pulses coming ~rom the mul-ti-channel OUtpllt 44 of the control unit 9 cau~e the data stor~d in the storage assembly 74 to be read out. These pul~e~ are ~imul-taneou~ly ~ed from the output 28 of t.he memory unit 28 to the multi-cha~el addre~s input 27 o~ the compari30n unit 25.
~ he ~irst pul~e tran~mitt0d through the ~i~st bus to the co~t~ol input 49 of~the memory unit ~1~9 cause-~ tha ~ir~t bit~
of the registers of the storage assembly 74 to be connected to the multi-channcl output 23.

A group of eight ~et or eight re~et signals i9 applied to the input 24 of the OR gate as~embly 14 and from the output of the assembly 14 to the input of the adder 16~ In the casa o~ sho~t-time epurioU8 ra3po~9e of the generator~ 1 ths group o~ ~ight signals consi~ts of rs~et and ~et signals. A ~ignal coming :~rom the second output of the adder 16 te the input 26 o~ the cornpa~i~on unit 25 represents in the bina~y code the number of set signsl~ at the output 23 of the memory unit 19.
I~ the number o~ set ~ignals pre~ails, (constitutes ~ive of eight), the compariaon unit 25 transmits, via a bu3 correspon-din~ to the ~irst bus of the multi-chann~l input 27~ a pul~
to the input~ 29 and 31 of the indicator 30 ~ignalling the quantity of disabled thyri~tors and the unit 32 protecti~g the high-voltaga valve against breakdown~
A logic one 3ignal is written into the f~st-bit looation o~ the.regi~ters.of...the.storage.,col1s (not,..~hQwn in ~ig..,l) o~ the indicator~ 30 and the unit 32. Otherwise, i~ tha num-ber o~ set signals in the first-bit locations o~ the regi~
ter~ o~ the ~torage a~sembly 74 i8 equal to or i~ le~ than ~our, Q logic zero ~ignal will be written into the f'irst-bit location of the regi~ter3 of the ~torage cells of tha indi-.
cator 30 and the unit 3,2.
The seoond-pu~se-transmi-tted -Yia the ~econd bus ~rom:
the multi-channel.output 44 o~.the oontrol unit 9 to the multi-.ohannel input 49 of the--memory unit l9-cau3e3 the ~e-cond-bit loca~ions-o~the---regi~,ter~.of tha stQrage assembly-74 ~ 23 -to be connected to the multi-Ghannel output 23. A group of ~et and reset signal~ ig applied to the input 24 of the ~R
gate assembly 14 and from the output of the a~sembly 14 to the input 17 of ~he adder 16. A signal applied from the ~econd output of the adder 16 to tha input 26 of the compa-riaon unit 25 repres0nts in the binary code the number of set signals ~t the output 23 of the memory unit 19, i~e., the numb~r o~ ~et signal~ sto~ed in the seoond-bit location~
of eight registe~s of the ~torage assembly 74~
If the number of s~t ~ignals prevails (equals ~iva of eight), the comparison unit 25 transmit~, via ~ bu~ oorres-ponding to the second bus o~ the multi-ohannel input 27 7 a puls~ to tha input~ 29 and 31 o~ the indicator 30 and th~
unit 32. A logic on~ nal i~ writte~ into the second bit location of tha regi~ter~ of the storage cell~ o~ the indica-tor 30 and the unit 32.
Similarly~ with th~ polling involving the prevailing num-ber of si~nal~, logio one ~ignal~ are rewritten ~rom all the bit.location~ of th~ registers of the storage a~embly 74 o~ tha unit 19 into the correRponding bit locatione of the r~gi~ter~ o~ the ~torage celle of the indicator 30 and the u~it 32. I~ the ~am~ numher i~ writt~n in the binary-dè.cimal code into the regi~t~r~ of the lndioator 30 and.th~ ~i.t 32 (a condition indicating that the r~g~ ers-are-~ervi-ceable and no ~ailu~s have occurrad in operatio~), similar data are conveyed to the multi-bit inputs 35 and 34 o~ the unit 33 for cheoking rfloorded information. Still appl~ed from the . - 2~ -.

output of the unit 33 to the input o~ the protection unit 32i~ the ~ignal enabling tran~mission of the command to turn o~f the hi~h-voltage valve. The same ~ignal is fed to the input 36 o~ the control unit 9 whereby a signal clearing the register~ of tha.storage assembly 74 o4 the unit 19 will be genexated.
If the number 3tored in the register of the protection unit 32 e~eeds a predetermined number o~ the additional thy-ristors 5 in the rectifier, the protection u~it 32 initiates a co~mand to turn off tha valve~
The stora~e cell~ of the indicator 30 are cleared by applying a signal from the outpu-t 46 of the control u~it 9 after all the registers o:E the ~torage assembly 74 are loa-ded. If different data are ~tored in the registers o* the storage ~alls of....the.indicator 30 and--.the protectio~ unit -32, the output oircuit~ o~ the-unit 32 are interlocked and no signal comes to the input 36 of the control unit 9. Thus, the oontrol unit 9 ~ill transmit two mor~ times the co~mand to rewrite the data from the .registers of the stoxage a~em-bly 74 into the register~ o~' the ~torage cells oY the indi-oator 30 an~ the prot.ectio~ unit 32. Thereafter all the ~torage cells of th~ .device are olearcd, a~d anothex ¢ycle of ~urveying the thyristors 5 in the valve begins.
I~ the signal~ at the bit outputs o~ the regi~ters of tha indicator 30 and ~he protection unit 32 are unequal ova~ a long period~ the uni. 33 ~o.r.chscking--reoord~d information . - 2~ -~ L9~04 furnishe~ a signal indicating that the device iB u~service-able.
~ha adder 16 (~IGURE 2) ope~ates in the following manns~.
The information on the condition o~ the thyristors 5 in the high-voltage valve is conveyed to the input 17 o~ the addar 16 as bytes. Each byte conveys conformation on eight thyristor~ 5. The number of digits in a byte corresponds to the number o~ disabled thyristors 5. ~he bytes are successi-vely applied to the input 17. The control pulses from the output 43 o~ the control unit 9 are simultaneously (or with a csrtain delay) applied to the ~irst-bit bus of the control input 48 of the add~r 16.
A~ the fi~st group o~ the thyristor~ urveyed, the input 17 receives tho first byte, i.e.~ eight one-bit sig-nals. The first byte is ~ed to-eight one-bit inputs--o~ the combination adder 52r The outputs of ~aid adder develop the binary code o~ the sum o~ set signal~ in the first byte, whi-le the outputs of the code converter 53 produce the binary-de-cimal code of the same number~ which is ~upplied to the data inputs of the storage c~ll 54. ~efore count the numbsr of disabled thyri~tors, the storage cell 54 i~ cleared. So, all bit~ o~ the multi-bit input 56 of the combination adder 52 are sct to zero. Hence~ in survs~ing the Yirst group o~ thy-~i~tors the adder 52 sums up only one-~it signal~ coming to the eight inputs of the elementary adders 56 ~ 57 ~ and 58 ~
~he inputs of the ~ixst summa~ion-stage ~1 accept ~ignals having a weight of one, and the S-outputa of the stage deve-- ~6 -~ 2~)~

lop signals having the sams weight of one, ~hile the P-out-puts thereof devalop signals having a weight o~ two. The S-outputs o~ the adders 56, 57, and 58 devalop signal~ o~
inter~QGiate sum3 o~ unit weight. The firs-t bit of the un-known sum i~ ~ormed at the S-output of the adder 59.
The second su~ation stage N2 adds up the ~ignal~ of tha next second bit, i.e., ona having a weight of t~o. The S-out-put of the adder ~0 provides the .intermediate sum o~ the se-cond bit obtained as a result o~ adding up the signals from the P-outputs of the adders 56, 57, and 58. The adder 61 receives said ~ignal and also the signal ~rom the P-output o~ the adder 59 and the signal of the seoond bit of the input 55, the latter .lignal be:Ln~ s~ual to zero in ~u~veying the ~irst group o~ thyris-tors. ~he second bit o~ the unknown sum is ~ormed at the S-output of the adder 61.
~ he adder 62 de~elops at it~ S-output-a third-bit sig-nal (i.e., one having a weight of four} ~f ~he unknown sum upon reeeipt o~ the signals ~rom the P-outputs o~ the adders 60, 61 and a signal from the third-bit looatlon o~ tha input 55, the latter signal equalllng zero in sruveying the fir~t group o~ thyristors.
The adder 63 develops at itB S-output a ~ourth~bit signa~ (i.e., one having~a weight-o~ -eight3 o~-tha sum-and at its P-output a carry signal having a weight of ~ixtaen.
~he~e output signals are generated to con~orm to the valuos o~ the input signals ~rom the P-output -o~ the--adder~62 and of the ~ourth bit of the input 55, the latter sig~al equalling æero durin~ the ~urvey operation.

~ 3~

In the code converter 53 the binary code of the sum fo~med at the output of the combination adder 52 i~ converted into the binary-decimal code. As a count pul~e coming to the ~irst-bit locatlon o~ the input 48 in interrogating each group o~ thyxistors ceases 9 four low~r digit~ ~1, 2, 4, 8" o~ the sum in the binary-decimal code ars ~ritten into t~e J-K flip--flops 64~ 65~ 66, and 67. The count pulse is applied to the combined count inputs o~ said ~lip-~lops 64 to 67 and to the second input 71 o-~ the binary-decimal counter 70. During the first survey operation, no zero signal is present at the decimal oarry output 68-P10.
The stora~e cell 54 i5 preliminary cleared by a ~ignal coming from the two-l~put OR gate 72. The inputs of said gate receive sig.nalq applied .~rom the input 39 and through the bit-two bus of tha control input 48.
As the first count pulse fr.Dm the Q outputs of the ~lip-flops 64 to 67 ceases, the multl-bit input 55 receives in~ormation as to the number of disabled thyristors counted during the ~irst survey operatio~ in the binary-decimal code which coincide~ with the binary code in the bits :~rom ono to four.
During the seoond survey operation, th~ adder 52 deter~
mines the s~m of=.de~ective..thyristor~ in the--seoond-group of th~ristors and in the first group of thyristor~, i.e., the ~um o~ th~ number of bina~y æignal~ at the input 17 and the binQry number at the input 55. lt will then be po~-sible to obtain a number exceedi~g ten~ r~hu~, a o~e signalappeari~g at the output 68-P10 of the c:ode converter 53 will be writ-ten in the lower-digit location o~ the binary-decimal counter 70 after the second count pulse ceases.
In this case, during the third survey operation the ad der 52 computes the sum of the number of defective thyristors in the third group of thyristors and the number stored in the ~lip-~lop~ 64 to 67 as a result o~ the second survey ope-ration.
Therea~ter the adder 16 sums up the number~ at the input 17 and the number stored in ~h~ flip-~lop~ 6~ to 67 ~ a result o~ surveying the previous group of thyristors. A~ter all the groups o~ thyristors have been surveyed, -the summation data applied ~r.om the Q-outputs of said ~lip-~lops 64 to 67 and ~rom.the outputs of the counter 70 are rewritten into one of the registers o~ the storage assembly 74.
'rhe comparison unit 25 (~IGURE 3) operate~ in the ~ol-lowlng mann0r.
l'he input of the unit 25 accepts signal~ representing numbers written in the binary code. rThe numbe~ represents logic ones written lnto the registers of ~he storage assembl~ 74.
If this number is equal to or less than four, it represents the amount-of fal~a records:of logic ones in the register of the storage a~sembly 74. If the n~ber i8 equal to or exceeds *ive, it indicatss that the number of false re-cords o~ logic -one signals in the registers equals.a-dif~er0nce between eight and:.~he- number being-compar~d.

The pulses representing the number in tha binary codecome to the input 80 of the decod~r 79. The pulses appear at those outputs o-~ the decoder 79 whose consecutive num bers O, 1~ 2,...9 corre~pond to the numbsr o~ the input 3ig-nal. I~ ~he number at the input 26 of the comparison unit 25 i8 equal to or less than fou~ no pulse arrives at the input 81 of the OR gate 82. If the number a~ the input 26 of the unit 25 equals or e~ceads ~ive, the output pulse of ~ha decoder 79 com~s to one of ~the input~ 81 of the OR gate 82.
Th~ output pulse o~ the OR gats 82 act~ as the output pulse of the comparison circuit 76. Thus, the number ~upplied to the input 26 o~ the comparison unit 26 i8 compa~ed with the number ~our repres0nting the maximum possible number of spurious responses o~ th~ voltag~ gcnerators employing thyristors.
The output pulse of the comparison circuit 76 is applied to the ~econd inputs 83 o~ the ~ND ~ates o~ the gate assem-bly 77. 'i~en ei~ht bits of the-registers--of the 3torage assembl~ 74 are succ~ssively surveyed, the control signal is simultaneously applied to the address input 27 o~ the unit 25. ~'~hen the first bit~ are surveyed~ the addres,s sig-nal i~ applied through the *irst bu~ o~ the input 27. It ia ~ed through-ths-second bus in survaying the second bit.s, etc, The one addre~s signal is ~ed to the input 78 o~ the respective AND gate whose-output developa a data--pulse co-ming to the respective bus o~ the ou-tput 28 o~ the oornpari-~on-unit 25. Thu~ the eight numbers in the binary oode sto-red in the register~ of the storage assembly 74 are rewrit-ten into the regist~ra 3O and the unit 32~ The use of-ths unit 25 makes it possible to eliminate ~al~e ~ailu~ o~ the thyristor voltage detector 1 wh~reby the correctne~s of data supplied by the indicator 11 will be confirmed and the ope-ration of the protection unit 32 will be reliable.
The indicator 22 (FIGURE 4) signal:Ling the numbers o~
disabled thyristors operatès in the following mannerO
The operator use~ the ~etting unit 96 to set the ad-dre3s of the ~urveyed group of thyristor~. A~ this happens~
two logic ~ignals ar~ appli~d to two o~ th~ tw~lve bu~e~
of th~ lnput '35 of t;h~ compari~on oircuit 93. Th~ input lO
of the indicator 11 receiv~ address ~ignal~ o~ all groups of thyri~tors of the high-voltage ~alve, said addrsss ~ignal~
being applied from the con~rol unit 11 through the ~elector 7 As the address sig~al,q are made coincident at the input~ of the comparison circuit 93, its output 92 develops a set pulse. Said pulse i~ applied to tha input 91 o~ the olear pul~e ~haper 9O ~urnlshing a short reset ~ignal to the input 89 of the register 86. The q~me pul~e iB ~imultan~ously applied to the ~econd input~ of the AND gates 84. ~en th~
given group of thyri~tor~ i~ surveyad, the input 18 o~ the indicator 11 rec~ives information on the condition o~ the thyri~tors 5 in the group via ~ight buse~. This in~orma-tion r~presents logic zero and logic on~ ~ignal~ an~
thyristor in the group fails, a logic one pul~e 1B ied Yi~
a respective bus to the iDpUt 18 0~ the indicator 11 a~d to the fi~st input o~ the respective AND gate 84. ~rom the eutput of said AND gate 84 the pulse is fed to the input 85 of the register 86. '~he register 86 stores the in~ormation supplied to the input 18 as a combination of set and reset signals indicating condition of thyristors of the group whose addres~ has been set by the eetting unit 96.
~ rom ths output o~ ths register 86 long pul~es are appliad to the inputs 87 o~ the indicator 88 which is used to provide visual presentation of the condition o~ the thy-ristors in the giv~n group.
'rhe control unit 9 (.I~'IGURE 1) operat~ in the ~ollowing, manner.
The clock-pulse generator 98 is a balanced multivibrator generating g-pulses coming to the input of the ~requency divider 99. ~ha.output.o~ the ~requency divider 99 develops pulses ~ at the ~irst intermedlate ~requency, rel~tive duration of ~hi.~h corresponds to the count module of the binary counter o~ the given divider 99, which equals ten. The pul~e ~ duration is equal to the operating period o~ the generator 98. The NOT gate 104 and the AMD gate 111 are u~ed to generate a-pulse whose-leading edge coincides with th0 leadin~ edge of the output pul-se o~ the frequency divider, while it~.duration:~squal~.half -of the duration of the same pul8e. This pulse i8 u~ed to genorate a count oo~mand ~or the 8torage cell~ 54 0~ the adder 16.
Th0 AND gate 112 ~urni~hes a pulse whose trailing edge coincide~ with the traili.ng edge of the output pulse- of the ~9 ~ ZO ~

~requency divider 99, while itR duration equal~ half of theduration o~ the same pulse excluding the delay o~ the laading edge by the use ol he delay el~ment 106~ Thi~ pulse i8 u~ed to gane ate a cor~mand to clear the buffer ~torage unit 13.
The multi-channel output 115 o~ the divider 100 develops pui~e~ at the second intermediate ~requency. ~hesa pulses are fed to the ~irst input 116 o~ th~ group 117 o~ AND gates, the second inpu-t o~ which accepts an inverted signal ~ from the input o~ the divider 100~ This decr~ases the duration o~
output pUlSe8 coming ~rom the output o~ the divider 100. The-~e pulses are used to generate clock logic one signal~ for ~urveying the groups o~ thyristora.
A~ the ne~t clock pUl9e interrogating any group of thy~
ri~tor~ ceases, there appear~ a pul~e g~nerating the aount command. A~tar a certain delay required to complete the count operation, there appears a pul~e generating the comma~d to clear the bu~er stoxag~ unit 13 whereupon a new olo~k signal to interrogate the ne~t ~roup o~ thyristor~ is applied. The pul~es derived from th~ one-¢hannel output o~ tho divider 100 are applied to the input- o~ the divider 101 whose multi-ohannel output 102 devclop~ pul~e~ at th~ third intermediate frequenc~ ~h~e pul~es are ~ed to the input of th~ addre~
command ~hQp~r 124 and ~re used to produoe clock pulse~ b.
l'he pul8e~ derived ~rom th~ one-ch~nel output v~ the divider 101 are appli~d to the input o~ ths divider lV2 who~

2~

multi-channel output 123 develops low-frequency pulse~ used to generate clock signals c.
- '~hs shaper 124 accomplishes conjunction of the aforesaid ~ignal~ ~h~reby appr~priate commands will be transmitted to the various components of the device.
The following commands are applied to the input 8 of the selector 7 and through ~aid input to the input 10 o~ the indicator 11:
(cl+c2~x3-~...+x8).(bl+b2+b3+b4).(al+a2+a3...a8).
Applied ~rom the output 42 o:f the oontrol unit 9 with a delay i8 thc co~mand ~,g. 1'h~ command~ applied ~rom th~
output ~3 to thc input 48 pa99 two bu~s~. The~ oommand3 are as follow~: the count command ~. g and the clear command of the ~orm (cl+c2-~c3+...~c8).b4.aO. The ~ollowing command~
are applicd ~rom the output 22 to the input 21 of the unit 19:
(cl+x~3+..0+c8-).b4.a9.-The *oll-owing commands-are applied from the output 44 to the input 49 of the unit 19:
c9-bl.(a2~a3+a4~...a9);
c9.b2-(a2+a3+a4+...a9);
c9 b3.(a2~a3~a4~...a9).
'~he ~ollowing clear command~ are applied from the output 45 to the input 50: c9.b~a9; c9-(bl-~b2~b3) .al. The ~ollowing commands are applied ~rom the output 41 to the input 40 o~
the unit 19:
K-c9.(bl+b2+b3)-aO. ~he cheok command K i~ applied to the input 36. ~he ~ollowing command i9 appli~d-from the output 46 to---the input 51-of the indicator 30: c9.(bl+b2~h3)~al.

- 3~ -,

Claims (7)

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:-

1. A device for monitoring thyristors of a high-voltage valve comprising the following components:
thyristor voltage detectors having outputs, the number of said detectors corresponding to the number of the thyristors;
light guides whose number corresponds to the number of said detectors, one end of each light guide being connected to the respective voltage detector;
a unit converting light signals into elec-trical signals, which has a group of inputs, connected to second ends of said light guides, and an output;
a selector having an input connected to said output of said unit converting light signals into elec-trical signals, an address input, first and second outputs;
a buffer storage unit having an input connect-ed to said first output of said selector, a reset input, and an output;
an OR gate assembly having a first input con-nected to said output of said buffer storage unit, a second input, and an output;
an indicator signalling the numbers of disabled thyristors having an address input connected to said second output of said selector, and a data input connect-ed to said output of said OR gate assembly;
an adder having an input connected to said out-put of said OR gate assembly, a control unit, first and second outputs;

a memory unit having a first input connected to said first output of said adder, a second input, a reset input, a control input, an output connected to said second input of said OR gate assembly, and an address read output;
a comparison unit having a first input connected to said address read output of said memory unit, a second input con-nected to said second output of said adder, and an output;
an indicator signalling the quantity of disabled thy-ristors having an input connected to said output of said comparison unit, a reset input, and an output;
a unit protecting the high-voltage valve against break-down, which has an input connected to said output of said comparison unit, a second input, a reset input, and an output;
a control unit having eight outputs and a control input and connected via said first output to said address input of said selector, via said second output to said reset input of said buffer storage unit, via said third output to said control input of said adder, via said fourth output to said second input of said memory unit, via said fifth output to said control input of said memory unit, via said sixth output to said reset input of said memory unit, via said seventh output to said reset input of said unit protecting the high-voltage valve against breakdown, and via said eighth output to said reset input of said indicator signalling the quantity of disabled thyristors.

2. A device for maintorins thyristors as claimed in Claim 1, which includes a until for checking recorded infor-mation that has a first input connected to said output of said indicator signalling the quantity of disabled thyristors, a second input connected to said output of said unit pro-tecting the high-voltage valve against breakdown, and an output connected to said second input of said unit protec-ting the high-voltage valve against breakdown and to said control input of said control unit.

3. A device for monitoring thyristors as claimed in Claim 1, which comprises:
an additional comparison unit having an input, and an output;
a third output of said adder connected to said input of said additional comparison unit;
a reset input of said adder connected to said output of said additional comparison unit.

4. A device for monitoring thyristors as claimed in Claim 1, wherein said adder includes:
a combination adder having N stages;
a series of main and additional elementary adders forming said stages and having n inputs serving as one-bit inputs of said combination adder;
S-outputs of said main and additional adders of the first stage N1 connected to said inputs of said additional elementary adders of the same stage;
one said S-output of said additional adder of each said stage acting as the output of said combination adder;

a P-output of each said stage and a subsequent stage connected to inputs of said elementary adders of the next stage;
the last said stage including one elementary adder having P- and S-outputs acting as outputs of said combina-tion adder;
a code converter having inputs connected to said outputs of said combination adder, paraphrase outputs, and a carry output;
a storage cell containing flip-flops whose number cor-responds to the number of said stages, said flip-flops ha-ving J- and K-inputs connected to said paraphrase outputs of said code converter, C-outputs acting as a control input of said adder, and Q-outputs connected to said input of said elementary adder of the stage corresponding to the bit of said flip-flop and serving as the output of said adder;
a counter having a first count input connected to said carry output of said code converter, a second count input combined with said C-inputs of said flip-flops, and outputs serving as the outputs of said adder;
an OR gate having a first input connected to said output of said control unit, and a second input connected to said output of said comparison unit, and an output connected to said reset inputs of said flip-flops and to said input of said counter.

5. A device for monitorins thyristors as claimed in Claim 2, wherein the memory unit includes:

a write selector having a first input serving as said first input of said memory unit, a second input acting as said second input of said memory unit, and an output;
a memory unit having a first input connected to said output of said write selector, a second input serving as a reset input of said memory unit, and an output;
a read selector having a first input connected to said output of said storage assembly, a second input serving as said control input of said memory unit, a first output acting as said address output of said memory unit, and a second out-put serving as said output of said memory unit.

6. A device for monitorins thyristors as claimed in Claim 2, wherein said comparison unit includes:
a comparison circuit having an input acting as said second input of said comparison unit, and an output;
an OR gate assembly having a first input serving as said first input of said AND gates connected to said address read output of said memory unit, a second input serving as a second input of said AND gates connected to said output of said comparison circuit, and an output acting as said output of said comparison unit.

7. A device for monitoring thyristors as claimed in Claim 2, wherein said indicator signalling the numbers of disabled thyristors includes:
a group of AND gates having a group of first inputs ser-ving as a data input of said indicator signalling the numbers of said thyristors, a group of second inputs, and a group of outputs;
a register having a group of inputs connected to said group of outputs of said group of AND gates, a reset input, and a group of outputs;
a light indicator having a group of inputs connected to said group of outputs of said register;
a clear pulse shaper having an input connect-ed to said group of second inputs of said group of AND gates, and an output connected to said reset in-put of said register;
a comparison circuit having a group of in-puts serving as said address input of said indicator signalling the numbers of disabled thyristors, a second group of inputs and an output connected to said second group of inputs of said group of AND
gates;
a unit for setting the address of thyristors under test, which has a group of outputs connected to said second group of inputs of said comparison circuit.