CH662682A5 - DEVICE FOR MONITORING THYRISTORS OF A HIGH VOLTAGE VALVE. - Google Patents

Description

The invention relates to a device according to the preamble of claim 1.

The field of application of such a device is high-voltage converter technology, in particular in high-voltage direct current transmission systems.

As is known, the high-voltage valves contain a large number of thyristors connected in series. If a breakdown has occurred in such a series connection with a number of thyristors, the breakdown can extend to all thyristors of the valve as a result of increased voltage at the other thyristors. In order to increase the reliability of such a valve, it is common to provide an excessive number of thyristors. However, it cannot be ruled out that a number of thyristors will fail during the operation of such a valve, which is above the surplus number of thyristors. In order to prevent the entire valve from breaking through and the resulting consequences,

the valve is equipped with a monitoring device which generates a warning signal and, in the event of further thyristor failures, emits a signal for switching off the high-voltage valve.

Such a monitoring device places particularly high demands on the reliability and immunity to interference during operation, since both a valve breakthrough and an incorrect valve shutdown can lead to serious disruptions in the energy supply or even shutdown of the consumers.

A device known from DE-PS 1 941 989 for monitoring the thyristors of a high-voltage valve has movably arranged scanners on guides. There are electrical contacts on the guides, which are connected to the anodes and cathodes of the thyristors. The connections of the samplers are connected to a display device which shows the operability of the thyristors. When checking the thyristors for their operability, the scanners are moved on the guides and connected to the anodes and cathodes of the thyristors. The operability of the thyristors is assessed based on the display of the display device.

However, since it is necessary to switch on the valve to use this known device, the display does not provide any information about the state of the thyristors during operation. In the time intervals between the checks carried out, however, the number of failed thyristors can exceed the number of excess thyristors, so that the entire valve fails. It is a disadvantage of the known device that the state of the thyristors cannot be monitored during operation.

Another device known from SE-PS 336 749 for continuous monitoring of the thyristors contains a first resistor which is connected in parallel with all the thyristors of the valve and a second resistor which is connected in parallel with one of the thyristors, the so-called reference thyristor. The resistors are connected in series with rectifiers, the connections of which are connected to an electrical measuring device and / or an electronic amplifier. When thyristors break through, the pointer of the measuring device deflects, the device being dimensioned such that the size of the display is proportional to the number of failed thyristors. The electronic amplifier delivers a signal to a warning and protection circuit.

However, this known device is insufficiently reliable due to uneven voltage distribution across the thyristors and is also insufficiently accurate when determining the number of failed thyristors. When the reference thyristor breaks, the entire device fails. In addition, this known device provides no information about which thyristor has failed.

Another known device according to the preamble of claim 1 is known from SE-PS 365 915. In this known device, the outputs of the buffer memory are connected to the selector and the zeroing input is connected to a corresponding output of the control unit. To control the display units, this device has a control pulse shaper which is connected to the inputs of the two display units. The pulses supplied by the voltage sensors go through the light guides to the storage elements in which they are stored. The signals are transmitted from the memory to the display units in the form of narrow pulses by means of the selector.

However, the serial signal transmission takes place without control and without confirmation of the correctness of the result. The equipment failures that lead to serious disruptions in the energy supply are not recognized in time. For the operation of this known device in transformer substations of high-voltage direct current transmission systems in which the interference level is very high, its immunity to interference is insufficient. Malfunctions and incorrect response of the device, in which the information is processed in the form of short-term pulses, falsify the result. Furthermore, this known device provides incorrect information, for example about breakdowns of all thyristors if the voltage at the valve in question briefly becomes zero in the event of a fault.

The object of the invention is to develop a device of the type mentioned in the introduction, in which the coded numbers of failed thyristors obtained after repeated interrogation processes are compared with one another, and thereby the reliability in determining the number of failed thyristors is increased.

The object is achieved according to the invention by the features specified in the characterizing part of claim 1.

Preferred embodiments of the invention are described in the dependent claims.

The terms “P outputs” and “S outputs” each refer to a transfer function or a sum function. In this context, reference is made to the “Manual for Integrated Circuits” by Tarabrin B.W. and others, published in 1980 by the publishing house Energija, Moscow.

The term “elementary summator” is understood to mean such a summator or summator, which contains three input and two output functions.

Main or basic summers, hereinafter also referred to as summators, are those summers in each stage at whose inputs the signals from external information bus lines are fed. Since an encoder has “N” stages that contain “n” summators, each of which is based on Main summators and additional summators exist, S outputs of the same name are connected in each stage to the respective inputs of the additional summators. If the number of S inputs is greater than two, a number of additional summators is required in this stage, which allow S outputs to be linked to a single output which is an output of the combination summator.

P outputs of the same name of the summators, both the main and the additional summators of each stage, if their number is greater than two, are in a bus line

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merged, which serves as an external information bus line for a further stage.

The device according to the invention enables the repetition of interrogation processes in a high-voltage thyristor gate circuit (HTT), with the total number of failed thyristors being determined at the given instant in the given state of the HTT in each interrogation process. After completion of the query, the previously stored values of the total number of failed thyristors are compared. In order to increase the security in determining the total number of failed thyristors, the comparison is, however, transferred into every digit of the binary decimal number of the failed thyristors and a majority is decided using the voting procedure.

By connecting the selector with the output of the signal converter and with the buffer memory, the proposed device results in a lower need for memory elements which, in contrast to the combination circuits, are less immune to interference. The reduction in the number of memory elements in the circuits for calling thyristors leads to a higher immunity to interference and to a greater operational reliability of the device. By using the logical OR circuits, the installation of a further summer can be avoided, so that the reliability of the device is increased. The totalizer used in the device enables counting of failed thyristors. The counting takes place on the basis of the information represented by the non-position code, while the result is output in the binary-decimal code. This results in the possibility of counting failed thyristors with the aid of known, proven and reliable elementary elements of computing technology and thus additionally increasing the reliability of the device. By using the memory block, it is possible to call the thyristors of the valve several times and the results of the calls, e.g. Statistical processing according to the principle of coordination, whereby the credibility of the results in the operation of the facility is significantly increased. The comparator present in the device allows the operation of the device, e.g. omit the results obtained when their thyristor voltage transmitters fail to respond and thus improve the reliability of the results. By installing the unit for data control when writing, there is now the possibility of monitoring the correctness of the data storage in the registers of the display unit for displaying the number of failed thyristors and the circuit arrangement for protecting the high-voltage valve against breakdown. This control unit also prevents the protective circuit from failing in the event of a device failure or malfunctions, thereby increasing its reliability. The use of the additional comparator enables the display to be deleted if a donor group fails.

The invention is explained in more detail in the following description of a specific exemplary embodiment and with reference to the accompanying drawings. Show it

1 shows a block diagram of the device for the operational control of thyristors of a high-voltage valve according to the invention;

2 shows a block diagram of the summator in the device according to the invention;

3 shows a diagram of the comparator of the device according to the invention;

Fig. 4 is a block diagram of the display unit for displaying numbers of failed thyristors in the device according to the invention.

The device for checking the operation of thyristors in a high-voltage valve contains thyristor voltage sensors 1 (FIG.

1), which are connected with the aid of light guides 2 to the inputs 3 of a light signal converter 4, which converts the light signal into electrical signals. As a thyristor voltage sensor 1, sensors are used, with the aid of which the voltage at the thyristors 5 is converted into a light signal. The number of sensors 1 is determined by the number of thyristors 5 in the high-voltage valve, each sensor 1 being electrically connected to the anode and the cathode of the corresponding thyristor 5.

The multi-channel output of the light signal converter 4 is connected to the input 6 of a selector 7, the address input 8 of which is at the output of a control unit 9. The number of channels in the light signal converter 4 depends on the number of thyristor voltage transmitters 1 connected to it. The address output of the selector 7 is connected to the address input 10 of a display unit 11 for displaying numbers of failed thyristors. The data output of the selector 7 is connected to the input 12 of a buffer memory 13.

To control a high-voltage valve with 256 thyristors, the selector 7 contains twelve address lines in the variant described.

The device also includes an OR gate block 14, the input 15 of which is connected to the corresponding output of the buffer memory 13, and a summator 16, in which the input 17 is at the output of the OR gate block 14. The output of the OR gate block 14 is also connected to the data input 18 of the display unit 11 for displaying numbers of failed thyristors. Furthermore, the device has a memory block 19 in which the inputs 20, 21 are connected to the output of the summer 16 or to the output 22 of the control unit 9 and the output 23 is connected to the second input 24 of the OR gate block 14. Another component of the device is a comparator 25, the inputs 26, 27 of which are connected to the second output of the summator 16 or to the addressing output 28 of the memory block 19 and whose output at the input 29 of a display unit 30 for displaying the number of failed thyristors and at the input 31 of a circuit arrangement 32 for protecting the high-voltage valve from breakdown.

In order to assess the reliability of the transmitted information about the number of failed thyristors, the device contains a unit 33 for data control during writing, in which the inputs 34, 35 to the output of the display unit 30 for displaying the number of failed thyristors, respectively. are connected to the output of the circuit arrangement 32 for protecting the high-voltage valve against breakdown and the output is connected to the control input 36 of the control unit 9 and to the control input of the circuit arrangement 32 for protecting the high-voltage valve against breakdown.

In order to prevent the device from failing to respond in the event that a short circuit occurs in the circuit of the high-voltage valve or the voltage at the valve connections drops to a level at which the sensors 1 do not supply any signals, an additional comparator 37 is provided, the input of which is 38 is at the output of the summator 16 and its output is connected to the setting input 39 of the summator 16.

The reset input 40 of the memory block 19 is located at the output 41 of the control unit 9. The outputs 42, 43, 44, 45, 46 of the control unit 9 are at the reset input 47 of the buffer memory 13, at the control input 48 of the summer 16, at the control input 49 of the Memory blocks 19, connected to the reset input 50 of the circuit arrangement 32 for protecting the high-voltage valve against breakdown or to the reset input 51 of the display unit 30 for displaying the number of failed thyristors.

In the relevant variant of the device

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The summator 16 contains a combination summator 52, a code converter 53 and a memory element 54, which are connected in series. The output of the memory element 54 is connected to the multi-digit input 55 of the combination summer 52. The combination summator 52 (FIG. 2) has an N number of stages, N being four.

The first stage Nj contains four elementary summators 56, 57, 58, 59, three of which are the main summators and the summator 59 is an additional summator. The second stage N2 consists of two elementary summators with three inputs, 60 being the main summator and 61 the additional summator. The third stage N3 is composed only of an elementary summator 62 with three inputs, which is a main summator, while the fourth stage N4 contains a summator 63 with two inputs. Eight inputs of the elementary summators 56, 57, 58 form the input 17 of the combination summator 52, and one input of the elementary summator 58 serves as an input for the first digit in the multi-digit input 55. The S outputs of the summators 56, 57, 58 are at the inputs of the elementary summator 59 connected, while the P-outputs are at the inputs of the elementary summator 60. An input of the elementary summator 61 serves as an input for the second digit in the multi-digit input 55, and two other inputs are connected to the P output of the elementary summator 59 and to the S output of the elementary summator 62. One of the inputs of the elementary summator 62 serves as the input of the third digit in the multi-digit input 55, while two other inputs are at the P outputs of the elementary summators 60 and 61. One input of the elementary summator 63 is provided for the input of the fourth digit in the multi-digit input 55, the other input is connected to the P output of the elementary summator 62.

The code converter 53 is constructed according to a largely known circuit of the linear decoder and is intended for converting the binary number code into the binary decimal code. This implementation also presupposes the delivery of the decimal carry signal if the total value of the least significant digits is equal to or greater than ten at the given time. For example, the number 12 in the binary code is written as 1100, the number 0010 and the carry signal appearing at the output of the code converter 53.

The S outputs of the elementary summators 59, 61, 62, 63 and the P output of the summer 63 are connected to the inputs of the code converter 53, the output of which is connected to the memory element 54. The paraphase outputs of the code converter 53, which are intended for low-order digits, are connected to the IK inputs of the flip-flops 64, 65, 66, 67, which have a common C input for control and an R input for zeroing, the the latter form the input 48 of the summator 16.

The output 68 of the code converter 53, at which the carry signal appears, is at the counter input 69 of a counter 70, which belongs to the memory element 54. The second counter input 71 of the counter 70 is connected to the C control input of the IK flip-flops 64, 65, 66, 67. The R input of counter 70 intended for zeroing is connected to the zeroing R input of IK flip-flops 64 ... 67 and is connected to the output of a logic OR element 72, in which one input has input 39 of the summator 16 forms and the other input serves as the input of the second digit in the two-digit input 48.

The Q outputs of the flip-flops 64 ... 67 are accordingly at the inputs of the first, second, third and fourth digits of the multi-digit input 55 of the combination summer 52. The Q outputs of the IK flip-flops 64 .. .67 and the Q outputs of the counter 70 as the output of the summator 16.

The memory block 19 (FIG. 1) contains a write selector 73, the multi-digit input of which forms the input 20 of the memory block 19. The number of digits of the multi-digit input is determined by the code for data processing in the summator 16. The choice of the binary decimal code is most appropriate since two decimal characters correspond to the 8-bit group - the byte - which underlies the structure of the majority of current microprocessor systems.

The memory block 19 also includes a memory unit 74 and a read selector 75, which are in series with the selector 73.

The number of multi-digit inputs of the storage unit 74 depends on the number of registers in this storage unit 74 and is selected on the basis of the condition of a sufficient averaging of results, in which the correct determination of the valve operability is not influenced by malfunctions in the valve. In this embodiment of the invention, the storage unit 74 has eight registers, not shown in FIG. 1. The control input of the write selector 73 forms the control input 21 of the memory block 19. In the present embodiment of the invention, the write selector 73, the memory unit 74 and the read selector 75 are constructed according to the largely known circuits (see, for example, Branka Soucek ... "Microprocessors and Microcomputers », USA, 1976, p. 38 and manual for integral microcircuits, edited by Tarabrina AS, Moscow,« Energia »1980, line 340 (Spravochnik po integralnym Mikroskhemam pod redaktsiei Tarabrina SA, Moscow,« Energia »1980, line 340 .

The comparator 25 (FIG. 3) contains a comparison circuit 76 and an AND gate unit 77 lying in series therewith. The first inputs of the logic AND circuits form the input 27 of the unit 77, which is connected to the address outputs 28 of the read selector 75 . The comparison circuit 76 includes a binary decimal decoder 79, the multi-digit input 80 of which serves as the input 26 of the comparator 25 and is connected to the output of the combination summer 52. The outputs of the binary decimal decoder 79 corresponding to the numbers “5”, “6”, “7”, “8”, “9”, “10”, at which the comparison signal is generated, are connected to the inputs 81 of an OR Circuit 82 connected to multiple inputs. The output of the latter is at the second inputs 83 of the logic AND circuits.

The display unit 11 (FIG. 4) intended for displaying numbers of failed thyristors contains an AND circuit group 84 in which the first inputs are connected to the outputs of the OR gate block 14 and the outputs are at the asynchronous inputs 85 of a register 86 . The outputs of the register 86 are connected to the inputs 87 of the light display 88, which in the present embodiment variant is formed by a set of light emitting diodes.

At the reset input 89 of the register 86 there is a reset pulse shaper 90, the input 91 of which is connected to the output 92 of a comparison circuit 93. The output 92 is also connected to the second inputs 94 of the logic AND circuits 84. The first inputs of the comparison circuit 93 are at the address outputs of the selector 7 and the second inputs 95 at the outputs of an arrangement 96 for specifying addresses of the thyristors of the high-voltage valve to be monitored.

To transmit the information about failed thyristors via the message channel to the computing machine, the display unit 11 intended for displaying numbers of failed thyristors contains additional structural units, which are not shown in FIG. 4. The latter are not part of the subject matter of the present invention and are therefore not described.

The control unit 9 (FIG. 1) contains a clock pulse shaper 97, which consists of a pulse generator 98 and four frequency dividers 99, 100, 101, 102. The latter provide binary counters

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Counting modules 10, 10, 4 and 9 are and are connected in series with the binary decimal decoders.

The output of the pulse generator 98 is connected to the input 103 of a logic non-element 104, to the input 105 of a delay element and to the input of the frequency divider 99. The single-channel output of the frequency divider 99 is at the input of the frequency divider 100, at the input 107 of another logic non-gate 108 and at the first inputs 109, 110 of logic AND gate 111 and 112, respectively. The second input 113 of the AND gate 111 is on the output of the logic NOT gate 104 is connected, while the second input 114 of the AND gate 112 is connected to the output of the delay element 106.

The single-channel outputs of the frequency dividers 100, 101 are connected to the inputs of the dividers 101 and 102, respectively. The multi-channel output 115 of the frequency divider 100 is connected to the first inputs 116 of an AND gate group 117, to the second inputs 118 of which the output of the logic NOT gate 108 is connected. The outputs 119, 120 of the logic AND gates 111, 112, the multi-channel output 121 of the logic AND gate group and the multi-channel outputs 122, 123 of the frequency divider 101, 102 are connected to the inputs of an address command shaper 124.

This address command shaper 124 represents a set of logical AND gates, with the aid of which the conjunction of the address signals is achieved.

Each channel of the multi-channel output '121 of the logical AND group 117 is intended for the transmission of clock pulses with address designations al, a2, ... a9, aO. Similarly, each channel of the multi-channel outputs 122, 123 of the frequency dividers 101, 102 is provided for the passage of clock pulses with address designations bl, b2, b3, b4 or cl, c2, c3, ... c9, cO.

To increase the speed, the number of powder stores 13 can be inserted between the powder store 13 and the OR gate block 14, while simplifying the selector 7, an additional selector.

The device intended for checking the operation of thyristors in a high-voltage valve functions as follows.

When the high-voltage valve is live, the sensors 1 (FIG. 1) emit light pulses. These pulses pass through the light guides 2 to the light signal converter 4, in which they are converted into electrical pulses. If all thyristors 5 are error-free, the number of pulses at the output of the light signal converter 4 is equal to the number of thyristors 5 in the valve. If a thyristor 5 is broken, the pulses at the output of the corresponding transmitter 1 are missing. From the output of the light signal converter 4, the electrical pulses are fed to the input 6 of the selector 7, the number of these pulses being determined by the number of whole thyristors 5 . An address signal in the manner of a combination of two pulses al, a2, a3,... A8 and bl, b2, b3, b4 is given to the address input 8 of the selector 7 via twelve lines from the control unit 9. After this signal, a group of the thyristors 5 is connected to the buffer memory 13. In the present exemplary embodiment, the group consists of eight thyristors 5. The same combination of pulses a and b is applied to the input 10 of the display unit 11 for displaying numbers of failed thyristors.

A number of H and L signals are fed to the input 12 of the buffer memory 13, the H signals corresponding to the broken thyristors 5 of the high-voltage valve. These short-term H signals are read into the register of the buffer memory 13 and pass from its output via the OR gate block 14 to the input 17 of the summator 16 and at the same time to the data input 18 of the display unit 11 for displaying numbers of failed thyristors.

The information represented in the form of a sequence of H and L signals is encoded in the combination summator 52. The binary-coded information about the number of H signals is transmitted from the output of the summer 52 to the input of the code converter 53. The work of the code converter 53 will now be described. The signals are supplied to the memory element 54 from the output of the code converter 53.

Thereupon the control unit 9 sends a signal to reset this buffer memory 13 to the input 47 of the buffer memory 13. Then the address signal at the input 8 of the selector 7 changes and the reading cycle for the information supplied by the second thyristor group begins. The sum of the query results from two thyristor groups 5 is entered into the memory element 54. The entry is made in binary decimal code. After query of all thyristor groups of the high-voltage valve, the number of which in the present embodiment variant is 32, a control signal is given from the output 22 of the control unit 9 to the input 21 of the memory block 19. After this signal, the number from the memory element 54 is rewritten in the binary decimal code using the write selector 73 into the register of the memory unit 74 belonging to the memory block 19. Thereupon a signal for zeroing the memory element 54 is given from the output 43 of the control unit 9 to the input 48 of the summator 16.

After the information has been entered into the first register of the storage unit 74, all thyristor groups 5 of the high-voltage valve are again queried. The number of failed thyristors is calculated by the memory element 54 and transferred to the second register of the memory unit 74. The third and the next register of the storage unit 74 are then filled. In the relevant embodiment variant of the invention, the storage unit 74 has eight registers.

The information written into the memory unit 74 is read out by means of the successive pulses supplied by the multi-channel output 44 of the control unit 9. At the same time, the same pulses pass from the output 28 of the memory block 19 to the multi-channel address input 27 of the comparator 25.

The first pulse, which reaches the control input 49 of the memory block 10 via the first line, switches the first register positions of the memory unit 74 to the multi-channel output 23.

A sequence of eight H signals or eight L signals is fed to the input 24 of the OR gate block 14 and from the output of the latter to the input 17 of the summator 16. In the event that the encoder 1 works incorrectly for a short time, the eight signal sequence consists of L and H signals. In this case, a signal is given from the second output of the summator 16 to the input 26 of the comparator 25, which indicates the number of H signals at the output 23 of the memory block 19 in binary code. If the specified number of H signals is a plurality, e.g.

five out of eight, the comparator 25 supplies a pulse to the inputs 29 and 31 of the display unit 30 via the line corresponding to the first line of the multi-channel input 27 to display the number of failed thyristors or the circuit arrangement 32 to protect the high-voltage valve from breakdown.

The H signal is read into the first register position of the memory elements of the display unit 30 and the circuit arrangement 32, which are not shown in FIG. 1. In the opposite case, if the number of H signals in the first register positions of the memory unit 74 is four or less, the L signal is entered in the first register position of the memory elements of the display unit 30 and the circuit arrangement 32.

The second pulse, which is transmitted via the second line from the multi-channel output 44 of the control unit 9 to the multi-channel input 49 of the memory block 19, switches the second register positions of the memory unit 74 to the multi-channel output

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23. A sequence of H and L signals goes to the input 24 of the OR gate block 14 and from the output of the latter to the input 17 of the summator 16. From the second output of the summator 16 a signal is given to the input 26 of the comparator 25, that the number of H signals at the output 23 of the memory block 19, ie indicates the number of H signals read into the second digits of the eight registers of the memory unit 74 in the binary code.

If the specified number of H signals is a plurality, e.g. five out of eight, the comparator 25 supplies a pulse to the inputs 29 and 31 of the display unit 30 or the circuit arrangement 32 via the line corresponding to the second line of the multi-channel input 27. The H signal is transmitted to the second register position of the memory elements of the display unit 30 and the circuit arrangement 32 read.

According to the similar majority principle, the rewriting of the H signals from all register positions of the memory unit 74 of the memory block 19 into the corresponding register positions of the memory elements of the display unit 30 and the circuit arrangement 32 takes place. If the registers of the display unit 30 and the circuit arrangement 32 have the same number in binary Read in a decimal code, this means that the registers are working properly and there are no faults, the same information being supplied to the multi-digit inputs 35, 34 of the unit 33 for data control when writing. From the output of the unit 33, a signal continues to be given to the input of the circuit arrangement 32, which enables the transmission of the command to switch off the high-voltage valve. The same signal also reaches the input 36 of the control unit 9 and allows the generation of the signal for zeroing the registers in the memory unit 74 of the memory block 19.

If the number entered in the register of the circuit arrangement 32 is greater than the specific number of excess thyristors 5 in the valve, the circuit arrangement 32 provided for protecting the valve issues a command to switch off the valve.

The zeroing of the memory elements of the display unit 30 takes place with the aid of a signal supplied by the output 46 of the control unit 9 after all the registers of the memory unit 74 have been filled. If different data are entered in the registers of the memory elements of the display unit 30 and the circuit arrangement 32, the output circuits of the Circuit arrangement 32 blocked, and there is no signal at input 36 of control unit 9. For this reason, the control unit 9 issues twice to rewrite the information from the registers of the storage unit 74 into the registers of the storage elements of the display unit 30 and the circuit arrangement 32. All of the memory elements of the device are then deleted. A new cycle of interrogating thyristors 5 of the high-voltage valve begins.

If the signals at the outputs of the register points of the display unit 30 and the protective circuit arrangement 32 are unequal for a certain length of time, the unit 33 intended for data control when writing in outputs a signal which indicates the faulty operation of the device.

The summer 16 (Fig. 2) works as follows.

The information about the respective state of the thyristors 5 of the high-voltage valve is supplied to the input 17 of the summer 16 in the form of bytes. Each byte contains the information about eight thyristors 5. The number of H signals in a byte corresponds to the number of defective thyristors 5. The bytes reach the input 17 serially in time. At the same time or with a time delay, 9 control pulses are fed into the line of the first position of the control input 48 from the summator 16 from the output 43 of the control unit.

When querying the first thyristor group, the first byte, which consists of eight single-digit signals, arrives at input 17. This byte is fed to the eight single-digit inputs of the combination summer 52. The sum of H signals in the first byte appears in the binary code at the outputs of the latter, while the binary-decimal code of the same number is generated at the outputs of the code converter 53 and is fed to the data inputs of the memory element 54. Before the start of the counting of defective thyristors, the memory element 54 is set to zero, which is why all positions of the multi-digit input 55 of the combination summer 52 have zero values. When querying the first thyristor group, the summator 52 thus only adds eight single-digit signals which are applied to the eight inputs of the elementary summators 56, 57 58. Signals with a weight of one are fed to the inputs of the first adder stage N1, signals with a weight of one also being generated at the S outputs of this stage, while signals with a weight of two appear at the P outputs. Signals of subtotals of weight one result at the S outputs of the summators 65, 57. The unit position of the sum sought is formed at the S output of the summator 59.

The second adder N2 sums the signals of the following second digit, ie with a weight of two. At the S-output of the summator 60, the subtotal of the second digit appears as a result of the summation of the signals from the P-outputs of the summators 56, 57, 58. This signal as well as the signal from the P-output of the summator 59 and the signal from the second digit of the input 55, which was zero when the first thyristor group was scanned, are fed to the summator 61. The value of the second digit of the sum sought appears at the S output of the summator 61.

At its S output, the summator 62 generates the signal of the third digit of the sum to be determined, which is rated with four, by using the signals from the P outputs of the summators 60, 61 and the signal from the third digit of the input 55, which at the Polling the first thyristor group was zero.

The summator 63 delivers from the S output the eight weighted signal of the fourth summing point and from the P output the carry signal with weight sixteen. These output signals are generated in accordance with the values of the input signals supplied from the P output of the summator 62 and from the fourth position of the input 55, the latter input signal being zero on the first interrogation.

In the code converter 53, the binary code of the sum obtained from the output of the combination summer 52 is converted into the binary decimal code. After the counting pulse, which arrives at the first position of the input 48 when each thyristor group is queried, four low-order positions 1, 2, 4, 8 of the sum in binary decimal code are transferred to the IK flip-flops 64, 65, 66, 67 read. The counting pulse is fed to the interconnected counting inputs of these flip-flops 64 ... 67 and the second input 71 of the binary decimal counter 70. The zero signal is missing at output 68 - Pio during the first query.

The initial zeroing of the memory element 54 takes place with a signal which is supplied by the logic two-input OR gate 72, at the inputs of which signals from the input 39 and via the line of the second places of the control input 48 are given.

After the first count pulse has dropped, the multi-digit input 55 is supplied by the Q outputs of the flip-flops 64 ... 67 with information about the number of defective thyristors which were counted in binary decimal code during the first query. This code corresponds to the binary code for the positions one to four.

In the second query, the sum of defective thyristors in the second and in the first thy-

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ristor group, i.e. the sum of the binary signal number at input 17 and the binary number at input 55 is determined. This can result in a number greater than ten. In this case, the H-Si signal appears at the output 68 - Pio of the code converter 53, which is entered into the lower-order position of the binary-decimal counter 70 when the second count pulse drops.

The sum of defective thyristors in the third thyristor group and the number stored in the fliplops 64 ... 67 as a result of the second query is determined in the summator 52 during the third query.

Furthermore, the numbers resulting at input 17 and the numbers stored in flip-flops 64 ... 67 when querying the previous thyristor group are summed in summer 16. After the query of all thyristor groups has ended, the addition result is rewritten by the Q outputs of the aforementioned flip-flops 64 ... 67 and by the outputs of the counter 70 into a register in the memory unit 74.

The comparator 25 (Fig. 3) works as follows.

Signals in the form of a number stored in the binary code are fed to the input of the comparator 25. This number represents the number of H signals stored in the registers of the storage unit 74. If this number is equal to or less than four, it represents the number of incorrect entries of the logical H level in the register of the storage unit 74. If the number mentioned is equal to or greater than five, this indicates that the number of incorrect entries of the logical L level in the registers is equal to the difference between the number eight and the comparison number.

The pulses which represent the number in the binary code reach the inputs 80 of the decoder 79. In this case, pulses appear at the outputs of the decoder 79, the order numbers 0, 1, 2, ... 9 of which correspond to the numerical value of the input signal. If the numerical value at the input 26 of the comparator 25 is equal to or less than four, then no pulse appears at the input 81 of the logic OR circuit 82. If the numerical value at the input 26 of the comparator 25 is equal to or greater than five, the pulse emitted by the output of the decoder 79 arrives at one of the inputs 81 of the logic OR circuit 82. The pulse generated at the output of the logic OR circuit 82 represents the output pulse of the comparison circuit 76. In this way, the number fed to the input 26 of the comparator 25 is compared with the number four, which is the maximum possible number of incorrect response processes in the thyristor Voltage sensors 1 represents.

From the output of the comparison circuit 76, the pulse reaches the second inputs 83 of the logic AND circuits of the AND gate unit 77. When the eight register positions of the memory unit 74 are queried successively, a control signal is simultaneously sent to the address input 27 of the comparator 25. When querying the first digits, the address signal is transmitted via the first line of input 27, when querying the second digits it arrives via the second line, etc. The address H signal is fed into input 78 of the corresponding logic AND circuit, and a data pulse appears at the output of this AND circuit, which is sent to the corresponding line of the output 28 in the comparator 25. In this way, the eight numbers stored in the registers of the storage unit 74 in binary code are rewritten into the registers of the display unit 30 and the circuit arrangement 32. The presence of the comparator 25 makes it possible to get rid of incorrect failures of the thyristor voltage generator 1 and to ensure reliable functioning to confirm the display unit 11 and the protective circuit arrangement 32.

The display unit 11 (FIG. 4) intended for displaying numbers of failed thyristors functions as follows.

The operator uses the default arrangement 96 to specify the address of the thyristor group to be queried, two H signals being fed into two of twelve lines of the input 95 of the comparison circuit 93. Address signals of all thyristor groups of the high-voltage valve are supplied alternately by the control unit 9 via the selector 7 to the input 10 of the display unit 11. When the address signals at the inputs of the comparison circuit 93 match, an H pulse arises at its output 92. This pulse arrives at the input 91 of the reset pulse shaper 90, which outputs a brief zeroing signal at the input 89 of the register 86. At the same time, the same pulse arrives at the second inputs of the logic AND circuits 84. When the respective thyristor group is queried, the input 18 of the display unit 11 is supplied with information about the state of the thyristors 5 in the group via eight lines. This information is presented in the form of logical L and H signals. If a thyristor of the group is broken, the logic H pulse arrives at the input 18 of the display unit 11 and at the first input of the corresponding logic AND gate 84 via the corresponding line. A pulse is applied to the input 85 of the register 86 from the output of this AND gate 84. The register 86 stores the information supplied to the input 18 as a combination of H and L signals, which represents the state of thyristors in the group, the address of which was specified by means of the arrangement 96.

Long-lasting pulses are applied from the output of the register 86 to the inputs 87 of the light display 88, with the aid of which the state of thyristors of the respective group is visually represented.

The control unit 9 (Fig. 1) works as follows.

The clock pulse generator 98, which is constructed as a symmetrical multivibrator, generates g-pulses which are fed to the input of the frequency divider 99. At the output of the frequency divider 99, pulses a of the first intermediate frequency appear with a pulse duty factor that corresponds to the counting module (equal to ten) of the binary counter of this frequency divider 99. The duration of these pulses a is equal to the oscillation period of the multivibrator in the generator 98. By means of the logic non-element 104 and the logic AND element 111, a pulse is formed, the leading edge of which is in phase with the leading edge of the output pulse of the frequency divider 99 and the duration of which is half as much long as the duration of this impulse. The generated pulse is intended to form the count command for the memory elements 54 of the summer 16.

With the help of the logic AND gate 112, a pulse is generated, the trailing edge of which is in phase with the trailing edge of the output pulse of the frequency divider 99 and the duration of which is half as long as the duration of this pulse, the leading edge being used by means of the delay element 106. The generated pulse is intended to form the zero command for the buffer memory 13. Pulses of the second intermediate frequency arise at the multi-channel output 115 of the frequency divider 100. These pulses are fed to the first input 116 of the AND gate group 117, at the second input of which the inverted signal a from the input of the frequency divider 100 is given. This shortens the duration of the output pulses delivered by the output of the frequency divider 100. These pulses are used to generate clocked logic L signals which are intended to query the tharistor groups.

After the subsequent clocked signal for requesting any thyristor group has decayed, the pulse of the mentioned counting command follows, and then with a time delay required to complete the counting, the pulse of the zeroing command is given for the buffer memory 13,

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662 682

whereupon the new clocked interrogation signal for the next thyristor group begins. The pulses generated at the single-channel output of the frequency divider 100 are fed to the input of the frequency divider 101, at the multi-channel output 102 of which pulses of the third intermediate frequency appear. These pulses reach the input of the address command shaper 124 and are used to generate the clock signals “b”.

From the single-channel output of the frequency divider 101, the pulses are fed to the input of the frequency divider 102, at whose multi-channel output 123 low-frequency pulses appear, which are intended to generate the clock signals “c”.

In the address command shaper 124, the above-mentioned signals are combined, and this gives the possibility of generating commands for the structural units of the device.

Commands of the following type arrive at the input 8 of the selector 7 and via this to the input 10 of the display unit 11: (cl + c2 + c3 + ... C88) • (b 1 + b2 + b3 + b4) ■ (al + a2 + a3 + ... a8).

The command a-g is output with a delay at the output 42 of the control unit 9. From the output 43 to the input 48, the counting command a-g and zeroing commands are given over two lines: (cl + c2 + c3 + ... c8) -b4-a0. The following commands go from the output 22 to the 5 input 21 of the memory block 19:

(cl + c2 + c3 + ... + c8) b4- a9. Commands of the following type are fed from the output 44 to the input 49 of the memory block 19:

c9 • bl • (a2 + a3 + a4 + .., a9);

io c9 • b2 • (a2 + a3 + a4 + .. .a9);

c9-b3- (a2 + a3 + a4 + ... a9).

From output 45, zeroing commands of the following type are given to input 50: c9-b4-a9; c9- (bl + b2 + b3) -al.

The following commands are input from output 41 via input 40 of memory block 19: K-c9- (bl + b2 + b3) -a0. The control command K is intended for the input 36. Commands of the type c9 • (bl + b2 + b3) ■ al are given from the output 46 to the input 51 of the display unit 30.

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2 sheets of drawings

Claims (7)

662 682 2nd PATENT CLAIMS 1. Device for monitoring thyrostores of a high-voltage valve, with each thyristor (5) being assigned a voltage sensor (1), each of which is connected via an optical fiber (2) to an input (3) of a signal converter (4) that converts the light signals into electrical signals. is connected to a buffer memory (13), whose input (12) is electrically connected to the output of the signal converter (4) and its inverted output to a first display unit (30) for displaying the number of failed thyristors and to a protective circuit arrangement (32) intended to protect the high-voltage valve against breakdown, and with a selector (7) electrically connected to the signal converter (4), the address input (8) of which is connected to a control unit (9) and the output of which is connected to a second display unit (11) for displaying the numbers of the failed thyristors, characterized in that that the selector (7) is connected between the signal converter (4) and the buffer memory (13), for which purpose its further input (6) with the output of the signal converter (4) and its further output with the input (12) of the buffer memory (13) is connected, that an OR gate (14) is connected with its first input (15) to the output of the buffer memory (13) and with its output to a data input (18) of the second display unit (11), that a summing unit (16) has its input (17) connected to the output of the OR gate (14), that a memory block (19) with its inputs (20, 21, 40, 49) with the first output of the summing unit (16) or with outputs (22, 41, 44) of the control unit (9) and with its output (23) with the second input (24) of the OR gate (14) is connected, that a comparator (25) with its inputs (26, 27) with a second output of the summing unit (16) or with an addressing output (28) of the memory block (19) and with its output with the input (29) of the first display unit ( 30) and is connected to the protective circuit arrangement (32). 2. Device according to claim 1, characterized in that a data control unit (33) with its inputs (34, 35) with the output of the first display unit (30) and with the output of the protective circuit arrangement (32) and with its output is connected to a control input (36) of the control unit (9) and to the control input of the protective circuit arrangement (32). 3. Device according to claim 2, characterized in that an additional comparator (37) is connected with its input (38) to the first output of the summing unit (16) and with its output to a further input (39) of the summing unit (16) . 4. Device according to claim 3, characterized in that the summing unit (16) one of summers (56, 57, 58, 59, 60, 61, 62, 63) existing combination (52) with a number of N stages (Nl, N2, N3, N4), of which each stage contains at least one totalizer and each of the totalizers has an S output for a buzzer function and a P output for a transfer function, that each stage (Nl, N2, N3, N4) is assigned a single-digit input (55), that the last stage (N4) has only one summer (63) and that at least the first stage (Nl) has at least one further summer, that the S and P outputs of the single summer (63) of the last stage (N4) and the S output of one summer (59, 61, 62) from each of the previous stages (Nl, N2, N3) have the output form the combination (52), that the S outputs of the further summers (56, 57, 58, 60) stages (NI, N2) with more than one totalizer are connected to the inputs of the summer (59, 61) of the same stage whose S output forms the output of the combination (52), that the P outputs of each stage (Nl, N2, N3) with the exception of the last stage (N4) are connected to the inputs of the summers (60, 61, 62, 63) of the following stage (N2, N3, N4), that said outputs of the combination (52) are connected to the inputs of a code converter (53) of the summing unit (16), that the summing unit (16) furthermore has a memory element (54) with a number of flip-flops (64, 65, 66, 67) corresponding to the number of stages N, the J and K inputs of which each have outputs in phase of the same place values of the code converter ( 53) are connected, that the C inputs of the flip-flops (64, 65, 66, 67) are connected together and form the control input (48) of the summing unit (16), that the Q output of each flip-flop (64, 65, 66, 67) is connected to the multi-digit input (55) of the combination (52) of the stage corresponding to the position of the flip-flop and also serves as the output of the summing unit (16), that the memory element (54) also has a counter (70), the first count input (69) of which is connected to a carry output (68) of the code converter (53), the second count input (71) of which is connected to the C inputs of the flip-flops ( 64, 65, 66, 67) is connected together and its outputs serve as further outputs of the summing unit (16) and that the memory element (54) also has an OR gate (72), the inputs of which are connected to the control unit (9) and to the Output of the additional comparator (37) and its output is connected to the reset inputs (R) of the flip-flops (64, 65, 66, 67) and the counter (70). 5. Device according to claim 4, characterized in that the memory block (19) has a series connection consisting of a write selector (73), a memory unit (74) and a read selector (75) and that the data output (23) of the read selector (75) is connected to the second input (24) of the OR gate (14). 6. Device according to claim 5, characterized in that the comparator (25) has a comparison circuit (76) and an in series with this, a plurality of AND gates (Fig. 3) containing AND gate unit (77) that the first inputs (78) of each AND gate of the unit (77) are connected to the assigned addressing output (28) of the read selector (75) and that the input (26) of the comparison circuit (76) is connected to the output of the summing combination (52) is connected. 7. Device according to claim 1, characterized in that the second display unit (11) one of AND gates (84) existing circuit group, a register (86), a light indicator (88), a reset pulse shaper (90), a comparison circuit (93) and an arrangement (96) for specifying addresses of the thyristors to be monitored, that the first inputs (18) of the AND gates (84) are connected to the output of the OR gate (14), that the inputs of the register (86) are connected to the outputs of the AND gates (84), that the inputs (87) of the light display device (88) are connected to the outputs of the register (86), that the input (91) of the reset pulse shaper (90) is connected to the second inputs of the AND gates (84) and that the output of the reset pulse shaper (90) is connected to the input (89) for resetting the register (86), that the first inputs (10) of the comparison circuit (93) 5 10th 15 20th 25th 30th 35 40 45 50 55 60 65 3rd 662 682 are connected to the address outputs of the selector (7) and that the output of the comparison circuit (93) is connected to the second inputs (94) of the AND gates (84) and that the outputs of the default arrangement (96) are connected to the second inputs (95) of the comparison circuit (93) are connected.