DE1474094B - Program-controlled data processing system - Google Patents

Description

1 2

The invention relates to a data processing an error has occurred, but as a function system with a large number of stores and one of the special features of the system itself. This Control arrangement with two functionally equivalent known systems also provides that a test unit control units, each of which has a clock, the direction of a monitoring circuit automatically as well as with one the control arrangement with the memory 5 supplies a test signal sequence to a deviation A connecting transmission arrangement for the selection of the output signals from have to be able to determine the interconnection of the memory and the target output signals. Control units for several operating combinations. Finally, one is working in real-time operation each of which one of the control units and minde- data processing system known (French at least one of the memories contains, with one to the io patent specification 1 337 556), in which a plurality of Control units connected input-output error checking and display circuits are provided, Arrangement and with blocking circuits, which determine the over- to a faulty operation and the to be able to localize transmission of command signals from a selected faulty unit. In addition The control unit for the input-output arrangement also includes a test device in the form of a counting block. 15 lers, with the help of which it is determined whether a

With the increasing complexity, correct command within one for this command has been carried out by data processing systems including a predetermined time. Other multipurpose and special computer systems and, in any case, an error display is initiated, neatly high operating costs of such systems occurs to ensure long-term reliable the need for more reliable systems. 20 Operability of a data processing system ge-In In some cases, certain night times can take the known measures for error detection hours for maintenance of the facility. But not recovery and elimination. As far as the well-known j Even in these cases, serious night-time systems can even trigger an automatic error i parts for the user occur when the system is detected and remedied by switching j fails during normal business hours. 25 is provided for spare parts, the Er-J In addition, with the increasing incidence of crisis and remedial action, it is more discouraging Data processing operations, for example speaking programs, read from the memory the machine control of a production line, which and can be carried out correctly. aside from that Control of a telephone exchange and that is, even if the test of functionality Control of critical scientific processes of the 30 of the system components with the help of appropriate test development extremely reliable data processing circuits do not result in an error display, not safety systems become absolutely necessary. made sure that the system is working properly as a whole,

So, to ensure reliable operation, meaningful work in terms of machining of data processing equipment is a number of data or the implementation of remedial measures and method known. So it is doing well.

knows, individual components or component groups are duplicated. Accordingly, the invention has the object

to be provided so that in the event of a failure, a data processing system can be created,

Reserve unit can be switched. Furthermore, with the reliable permanent operability

is an information-processing connection already ensured or restored

location, in particular telephone exchange, 40 can if the system is due to a

known, in which the control of the connection on- Component tests and test programs do not determine

construction is carried out by electronic devices and does not do any meaningful work or does not make any mistakes

which works in the time division multiplex process. For groups at all is unable in the present

group memory and system interconnection programs are to be executed by participants,

associated control devices are available, the 45 To achieve the object, the invention is based

again a common control under a data processing system at the beginning

are ordered. An additional substitute control device mentioned and is characterized by the

tion can be placed anywhere any other, the following characteristics:

faulty group control device switched on. ,. ,. . . ".

(German Auslegeschrift 1135 056). 50 ^a ) ^dl % data processing system has a time

There is also a data processing system with a recording device to ^{which the clock generator responds to output two identical memory units and these associated sl} S ⁿ <* ^le and an occurrence of code checking devices is known (British drawing of the occurrence of patent specification 954 225), in which in the case an error output signals of the clock generator determined time determination by a code checking device the output 55 1 ° ^ΐη1 ^. ^{and eme} recording device, output signals of the respective storage unit are blocked. The execution of certain programs is blocked in order to prevent the error from affecting after ^f _A ^ol f? responds and to avoid recording the orderly circuits. Undertakes work that is associated with the execution of the

It is also known to use a comparative program sequence; arrangement for output pulses of a double pre- 60 b) it is a circuit arrangement for generating Existing monitoring circuit for determining control signals during the execution of the of differences in the results of a data program sequence and another Processing (British Patent 921,379). In the case of a circuit arrangement that checks whether the tax determination of a difference, only the output signals within a predetermined range are generated by the timing pulses a monitoring circuit to other recording devices of specified times Transfer parts of the system. The limits occur and an error signal is selected However, one of the monitoring circuits will testify when the control signals are not within not depending on in which of them the given time limits occur;

3 4

c) with the further circuit arrangement is an operation as well as the requirement for a permanent Sequential circuitry connected to operation does not apply to telephone exchanges alone Error signal responds and a combination system, but also for many other data from Emergency response control signals generated; Processing plants.

d) with the follow-up circuit arrangement is an emergency ⁵ developments of the invention are coupled in the submeasure control circuit, which addressed addressed.

, to which the emergency measures control signals responds.

i and the control units and the independent ⁿⁱ fg ^e £ an embodiment of the invention

i memory rewritten to new operating combinations. It shows

I, of which one with the input-output ^{10 Fl} & ¹ ^ general block diagram of a remote

! Gang arrangement in connection and each speech switching system as an exemplary embodiment

¹ further is inactive, the sequential circuit of a data processing system

I arrangement is designed so that you can independently f, ^l f ² _c ^the . Arrangement of information within

¹ of the output signals of the clock generator and half of the memory,

Regardless of the program, the one to achieve ¹ S ^ g-. 3 to 6 in the arrangement according to FIG. 82

the introduced by the error signal environmental "" *? _u ^detailed block diagram of a continuous

Order necessary emergency measures control exemplary embodiment of the invention

signals Fig. 7 generates a general block diagram of a program memory,

An incorrect operation of the data processing 20 Fig. 8 is a general block diagram of a system

The system can therefore be used independently of the component or call memory,

other tests can be determined in that Fig. 9 is a general block diagram of a

the execution of the program sequences, d. H. sensible control unit,

Work, not within certain time limits. Fig. 10 to 63 a detailed switching

; follows. It can then be used to restore the 25 image of a control unit,

i Operational ability a rearrangement of the operational com- F i g. 64 to 66 in the arrangement according to FIG. 80

j combinations by changing their interconnection- a schematic representation of the main news-

. processing can be carried out, regardless of the connection paths of the exemplary embodiment,

j from the output signals of the clock generators, i.e. their FIGS. 67 to 77 in the arrangement according to FIG. 81

■ Operability, and independently of the capability 30, a schematic representation of a program memory

'the facility to run programs. In contrast to chers, which is used in the exemplary embodiment,

to switch on a substitute control device, see Fig. 78 the reactions of the central data

Place a disturbed facility of several workers on successive emergency measures,

similar devices according to the above-explained FIGS. 79 to 82 the compilation of figures

th prior art leads to a rearrangement of FIG. 35 for parts of the exemplary embodiment indicated above.

Combinations of operations under certain circumstances, even then The main components of a telephone exchange

again to a workable combination if the management system as an embodiment of a data

several components of the combination are disturbed. Processing system are shown in FIG.

The invention can be applied generally to data processing In Fig. 1 contains the as a central data processor

use processing equipment. For explanation, block 100 denoted 40 is the control arrangement 101 and

however, in connection with a special one, the memory system with the program memory 102

Data processing system, namely a program and the call memory 103. The other EIe-

controlled telephone exchange system described in FIG. 1 form the input-output

ben. System of the embodiment.

Data processing systems are used under a wide variety of conditions which, in principle, are shown generally in FIGS. 3 to 6. These input and output devices and the figures used are intended to distinguish certain details of the control-specific data sub-arrangement 101 processed in the system, the storage system 171 and the. The invention does not depend on elucidating this transmission system 105-106.
Distinguishing features. 5 ° The control arrangement 101 has a first control-A telephone exchange provides, how many tion CCl and a functionally equivalent second data processing system, a real-time controller CC2.

The storage system 171 contains a multitude of

wrestled the independent memories connected to the central office, namely a multitude of

Subscriber and trunk lines without substantial 55 independent program memories 102 PSl bis

Delays need to be met. In addition, 102PSiV (Fig. 5) and a large number of independent

A call memory 103CS1 to 103CSiV must work to the satisfaction of the subscribers

tending telephone exchange permanently in (Fig. 6).

Operation. The transmission system 105-106, which connects the control units 101 CCl and 101 CC 2 to carry out repairs or changes to the line protection system 171 during the day or night, has a multitude of to interrupt leadership. On the other hand, telecommunication channels 6400-0, 6400-1, telephony are indispensable for modern society. Instructions for obtaining loaned, and serious personal emergencies that require the information from one of the program memories to make use of a telephone system 65 PSl to PSiV are made by the controls CCl, occur not only at times that are transmitted for the CC 2 via the transmission path 6400, Plant and monitoring staff are cheap. which consists of two independent multiple conductors over the conditions explained above for the real-time transmission paths 6400-0 and 6400-1. How out

5 6

F i g. As can be seen in FIG. 3, information that The audit circuits 460 included in a

proceed from the program address register, and will be described in detail later. Arrangements for the display of routing are supplied. The controls CCl- 5 faults are provided which indicate that the data] CC 2 are optionally dependent on the information processor on difficulties in obtaining functions in the path register 300 and the activity and / or execution of program instruction words in the flip-flop 55 AU these transmission routes and encounters. As already explained, this fact is associated with all other transmission paths. How important, because the data will be explained in more detail in the following, io processor is not able to make meaningful correction the control can be set up (by setting measures based on the execution of a prodes path register and the activity flip -Flops) that gramms are based to perform. The display of an instruction about one of the two transmission errors of this type results in the delivery of an output path or neither transmits. signal by the operation check circuit 460 that the 15 one of the maintenance interruption flip-flops transmitted via the transmission paths 6400 an instructions are supplied to all the program memories, which in Fig. 4 in the form of the LB flip-flops 465 102 PS1 to 102 PSN . As shown in FIG. 64. The setting of the maintenance can be seen under these transmission paths selection-breaking flip-flops 465 directs the function of the way to be energized by both controllers and emergency action sequence circuit 5702 in FIG. 3 a. are inductively coupled to each program memory. This circuit, which is described in detail later, pelt. Each program memory 102 PSl to 102PSiV is set up so that it is emergency control optionally depending on the setting signals independent of the ability of the control to receive and / or execute programs of the individual program memory path register, and 501 the multiplexer Transmission paths assigned independently of the clock circuits within the net. As will be explained in more detail below, 25 control supplies are provided. The sequential circuit 5702 should contain, the state of the position register in each of the monostable circuits, the output signal of which is program memory and the type of instructions on successive independent transmission paths with the aid of a tapped delay, the assignment of the assignment line within the sequential circuit to the j of the transmission paths and the independent pro Output connections of the sequential circuit applied to the gram memory. The program memory is transferred 30. These pulses change the state of the route} responses to the controls via the superregisters 501 in the independent program memories transmission path arrangement 6500, which are a first of the memory system 171 and control the state of multiple conductor transmission path 6500-0 and one of the activity flip-flops 55 AU in the first and second multiplexer transmission path 6500-1 ent- second control CCl and CC 2. After each receives. 35 excitation of the emergency measures sequential circuit 5702 leads In summary, it results that the assignment of the control, in which the activity flip-flop eyes of a program memory to the independent overview is set in state 1, a specific path and the assignment of the independent rapid program sequence which serves to define the basic transmission paths for a specific controller, the additional function of the controller, the current status of the path register 500 in the independent program memory allocated to it and the path register 300 and that of the memory system 171 and the connecting activity -FIip-Flops ^ t / in the controls down- check manifold systems. If the tax is pending. tion is able to execute the special program sequence for the transmission of instructions and data, measures are taken to ensure that the controls for the call memories CS1 to 45 carry out the normal work that is assigned to the data processor CSN of the memory system 171, separate Sam- assigned work (in In the exemplary embodiment, the line systems 6401, 6402 are provided and for processing long-distance calls). If the transmission of responses from the conversation memory but the data processor is not able to carry out a program sequence like a collecting line labyrinthine to the controls within a pre-system 6501.50 period of time, the further connect independent transmission emergency measures follow-up circuit is again energized, in order to produce the controls CC1-CC2 with a further rearrangement of the components, the input-output system 170, and separate namely another combination of a control, transmission paths 6600-0, 6600-1 transmit information of a program memory and the connecting mations from the input part 172 of the input 55 manifold system. The emergency action follow-up exit system 170 to the controls. circuit has a counter which is always switched on The transmission of commands to the input when the subsequent circuit is energized output system from the selected control CCl. This counter is only reset, or CC 2 takes place according to the setting of after it has been determined that the control flip-flops 55 A U of each control. As will later be shown again to win program sequences j is, when the flip-flop 55 AU in and execute, the control CCl is set, the corresponding
Flip-flop of control CC 2 reset. Similarly, if the flip-flop 55 AU in the central data processor 100 controller CCl is reset, the corresponding 65 is

Flip-flop of control CC 2 set. The control The central data processor 100 provides a central

tion, whose flip-flop 55 AU is set, transmits a neutralized data processing device which commands the input-output system 170. has the following parts:

7 8

1. Central control 101, transmission buses and cables

2. program memory 102, ⁶

3. Conversation memory 103. The transfer between the main sections

',. _D .. "..,,. . , the system takes place with the help of a manifold

With regard to its functions, the central _{5 s} ^ ^ ^ _{voQ multi-conductor cablesj} ^ ₆

Control 101 can be divided into three parts: ^^ Transmission paths between the selected

1. Data processing equipment, represent sections of the system.

2. Facilities for communicating with a bus system generally has two Inlet and outlet arrangements and double manifolds shown in the drawings

3. Maintenance facilities. ¹⁰ S ^en ^ ^s collective line »0« and collective line »!«

are designated.

As far as possible, be within the central

Controller 101 common circuits to through switching network 120

all of these functions are used. The switching network 120 comprises only transmission

The program memory 102 is in the initial i ₅ mission paths, means for making the paths and operation example of a permanent magnet means for monitoring the paths. The central magnet wire memory (twistor) and therefore enables data processor 100 to contain records and non-destructive reading of the information stored in it regarding the occupied and free status of all the second information. The program memory 102 which chenleitungen (left) of the network and a Aufvon is inherently semi-permanently, is to Speiche- ₂₀ drawing with regard to the construction of each hergestellrung the more permanent information in the system on ten or reserved path through the network, and finally uses the programs. Information These recordings are in conversation with the aid of the program memory card memory 103 of the central data processor 100. Writer 146 is entered into the program memory 102.

wrote. _as subscriber circuits

The call memory 103 consists of the subscriber sets such as 160, 161 are normal

management example from a ferrite plate memory. male designs.
Therefore, information in the conversation ■ '.,.,. "

memory 103 written in or taken from it

men will be. As the information is in the 30 The central impulse distributor 143 is an electrical storage device 103 itself at the normal speed niche high-speed converter, the two of the system can be changed, in it the uncertain types of output signals on the basis of commands more constant information is stored. of the central data processor 100 delivers. The at

the types of output signals will be unipolar

Central control 101 called 35 signals and bipolar signals and are each

because output connections of the central pulse

The central controller 101 assigns with regard to plates that are assigned as CPD unipolar points and The reliability of the system is indicated by two independent CPD bipolar points. Both signal controls on. The independent controls are made up of impulses from the CPD set up so that they transmit all necessary operation points to the consumer devices perform gears within the system. While will.

of normal operation, the two perform independently- In general, the unipolar signals are

Common controls use the same work functions to briefly control a specific component, for example A network controller 122, a network

\ tion through. This will stimulate lock-step operation.

called. At any given point in time, however, can
only one of the two controls the state of the main scanner 144

; System change or the implementation of telephone The main scanner 144 has a ferrite rod matrix,

control functions. This means that the two circuits, regardless of which the circuits to be monitored end in, pending controls control and maintenance information 50 and a device to optionally due to functions on a mutually exclusive one command from the central data processor 100 Hand over the basis to the rest of the system. the monitoring status of a selected group

In the exemplary embodiment, the central of monitored circuits leads to the central control system 101 a command, except for a program 101 to be transmitted. The sensing element used Jump, a reading of a program memory 55 is a so-called ferrite rod arrangement. It includes Data word or a selection of work radio - a perforated rod made of ferromagnetic material functions, for which special, described in the following with control, query and reading windings. the bene sequential circuits are required on which tax developments are. in series to the elek basis an instruction cycle of 5.5 μεεο from; Irish connections are switched, which the over-, this sets the time cycle of the program memory 102 to 60 monitoring state of the monitored circuit: and of the conversation memory 103. A micrometer. For example, if a ferrite rod for oversecond clocks in the central controller 101 monitoring of a subscriber line is used, is delivers pulses with a length of V2 μβεο and he in series with the wires of the subscriber line Intervals of 'Αμβεα These pulses give the and the subscriber set, switched. If the central controller 101 the possibility of a sequence 65 subscriber set in the hung-up state of successive functions is located within, no current flows through the ferrite rod Instruction cycle with a duration of 5.5 μ8βϋ control winding while in the off-hook state to execute. a current flows The interrogation and reading processes

9 10

consist only of individual conductors, which contain information bits through data, and these conductors lead the two holes of the ferrite rod, ie they are excited when a "1" is transmitted, and the interrogation conductor as well as the read conductor lead de-excited or close to Earth potential held when through both holes of the ferrite rod. One from one a "0" is transmitted. The single-track data generated on a bipolar pulse existing interrogation signal, 5 dem.:Kabel30.<404 are inverted bit for bit by the symbolic inverter 30 ^ 4 03 when it is applied to the interrogation conductor. The output signal in the read conductor of each ferrite rod, the output conductor of the inverter, consists of the input of a monitored circuit, which is wired to the conventional AND gate 30 ^ 402. If the ferrite rod is a The input signals of the AND gate 30 A 02 are monitored circuit in the off-hook state, the complement of the input signals of the AND due to the saturation of the ferrite rod is no read gate 30 A 01. The AND gate 3OA 01 and 30 A 02 \ impuls are generated. can be excited by a signal on conductor 30 ^ 4 05 er-The main scanner 144 generally corresponds to, and the output terminals of these to network scanners 123, 127, 135, 139, which gates represent the "1" and "0" rails which are distributed over the network frames. However, the main scanner 144 for setting and resetting registers is used for certain uses. To monitor the symbol for such a Umwan circuit element, which indicates the operation of the AND gate is shown in FIG. 30A, the operating state of the system. and designated by 30 A 06.

Component ^{description 2O} . Program memory 102 (Figs. 7 and 67-77)

In certain cases, the binary states. The program storage system 102 includes one

a circuit on a pair of alternately large numbers of independent program memories, energized output conductors shown. Such each program memory is a large memory with Arrangement is called two-track circuit, and 25 random access and consists in this of binary circuits, which individual »0« and »1« examples from a multitude of Twistor output signals deliver, two-pronged logical modules and the associated control and access elements In other cases, only one and readout circuits are called.

of the two states of a binary circuit as off Each twist module has a storage capacity

output signal is used, and such arrangements are 30 out of 8192 words with 44 bits each. The Twistor words are called single-track circuits. In all characters, they are assigned to each other in pairs in the memory, and in many cases connections can be gates, amplifiers. Each module therefore has 4096 discrete information symbols, etc. a multitude of gates or addresses. The selection of the appropriate word with stronger with a number of channels means 44 bits from the pair of words with 44 bits each which are equal to the number of individually transmitted 35 is made at the output of the twistor,
rush signals is. The information capacity of a program memory

For example, in FIG. 11, the ANDchers transmits is divided into two halves. One half of the gates 1104 in the excited state, the ten information capacity is designated as the left or if half tion bits ^ O to ^ 45, 51, 52, W and CM from the off and the other half as the right or passage of the cable receiver 1102 to Entrance of the 40 G half.

symbolic multiple OR gate 1109. In order DEM the use of odd numbers of Progemäß contains the cable receiver 1102 ten over- program store within a memory system to exchangers and ten amplifiers. The AND gate 1104 allow and still a complete comprises ten AND gates, and the OR gate to maintain duplication of the information, the 1109 contains ten OR gates. In addition, in FIG. 45 information is duplicated in accordance with the pattern shown in FIG. 85 with two types of AND gates sym- metrical for the call memories. That represented bolisch. The first type corresponds to one that is, the information stored in the right half of the conventional AND gate, such as the program memory, is in the AND gate 3006 shown in FIG "!" - program memory doubled bol represents a multitude of AND gates, whose 50 etc.

Number equals the number of information paths in The information is taken from the program memory

a cable is. If the cable carries information on system 102 by a command from the central single-track basis, an AND gate is obtained per controller 101 , which has an information information bit. However, if the cable designates group code names and an address, carries information on a two-pronged basis, the 55 is the location of the desired information word number of AND within the designated information group of gates is equal to twice the number of information
bits. The transmission busbar systems 105 with

The second type of AND gates which infor- the address and control buses 6400 and mation from the single track in the twin-track 60 the answer manifolds 6500 which convert the state in Fig. 30 symbolically DAR central controller 101 and the program memory. There, the gate 3008 is assigned as a conventional 102 alone, be AND gates are shown accordingly, in which, however, a cross table is arranged within the symbol used to receive commands from the central controller 101. Such to the program memory 102 and responses from AND gates is shown in Fig. 30A with a schematic 65 of the program memory 102 back to the central details. The data are to be transmitted on the control 101 cable. Except this present on single-track basis, that is, in-30.404, which receives its own transmission paths each ProCable 3oA 04 includes a conductor for each in the program memory of the program memory system 102

r further control information from the central controller 101 in the form of output signals from the central controller Pulse distributor 143..

In Fig. 74 7 bistable flip-flops are shown in each memory, which the input signals from control the busses and the output signals to the busses. Certain of these Flip-flops are set or reset by the output signals of the central pulse distributor 143, while others in an operation of the storage; chers set in the write control mode or postponed. A table of these flip-flops, the source of information on setting or Resetting the flip-flops and the meaning of the set or reset flip-flops is in the reproduced the following:

Source and meaning of setting the way flip-flops

Flip flop
(Fig. 74)

turned on and reset
by

meaning

RO

CPD

HSO

HSl

GSQ

GSl

TBLO

TBLl

Write control
Write control
Write control
Write control

CPD

CPD

set - Receiving from the bus "0". Sending from Maintenance and control readings on the collecting line »0« ..... ■ '■ "

reset - received from bus "1". Send out of maintenance and control readings on the bus "1"

set - sending normal readings from H on the collecting line "0"

set - sending out normal readings from J? on the manifold "1"

set - send normal readings of G on the manifold "0"

set - sending normal readings from G on the bus "1"

set - Blocking of traffic with the trunk line »0« (both send as well as receive)

set - Blocking of the traffic with the trunk line »1« (both send and receive)

These flip-flops are influenced by the central controller 101 in order to produce the desired memory bus combination to win.

The setting and reset signals for the flip-flops R 0, TBLO and TBL1 controlled by the central pulse distributor are received via the bipolar cable 6700.

In the event that the central controller 101 encounters malfunctions in obtaining information from the program memory 102 and the effects of this malfunction cannot be overcome in a simple manner by a routine troubleshooting check and a reorganization of the components according to the information obtained, the central controller takes action Control 101 certain "emergency measures". These emergency measures include fixed rearrangements of the program memories and manifold assemblies until the central controller 101 is able to resume operations without error. Emergency (measures) signals are transmitted from the central controller 101 to the program memory 102 via the emergency cable 6900 (FIG. 70). The emergency cable comprises four pairs of cables, labeled EAPIE to EAPZE , and a synchronization and backup signal is transmitted over the fourth pair, labeled EAPEE . The emergency cable pairs each end in a transmitter, such as 7513, and a signal on an emergency cable pair provides an input signal for its associated receiver amplifier 7515 and therefore represents an input signal for an associated AND gate, such as 7517. The information is passed through the AND gate such as 7517, under control of a jEL4P.Eii signal received via transmitter 7514 and amplifier 7516. After decoding, this information is used to set and reset the flip-flops 79R0, 79TBLO and 79 TBLl. An emergency command always includes a synchronization signal on the EAPEE line, a signal on the EAP 3 E line and a signal either on the EAPIE or EAP 2 E line is assigned to the arrangement of memories within a storage system.

In the case of the first emergency measure, the central controller 101 transmits signals on the lines EAPLE, EAPZE and EAPEE. After their decoding in the corresponding emergency decoders, such as 7802, the first emergency signals supply a state Λ signal in the first memory, a state ß signal in the second memory and state C signals in all other memories. The status Λ signal causes the first memory to receive signals from the "0" address and control bus of the program memory address and control bus system 6400 and all responses on the "0" response bus of the program memory -Answers manifold system 6500 transmits. The state β signal at the output of the decoder 7802 in the second memory causes this memory to address and

Receives control information on the "!" Manifold of the manifold system 6400 and replies on the "!" answer bus line 6500 transmits.

The state C signal at the output of the emergency decoder 7802 in all other memories causes that these memories are brought into the fault state and their operation is blocked in this way will.

In the second emergency measure, the central controller 101 transmits signals on the lines EAP 2E ₁ EAP 3 E and EAPEE. After their decoding, these signals supply a state β signal in the first memory of the memory system, a state Λ signal in the second memory of the memory system and state C signals in the other memories of the memory system. In accordance with this command, the first memory receives addresses and commands via the "!" Bus and replies via the "!" Response bus. The second store receives via the "O" manifold. The remaining memories in the system. are put into the fault state and can therefore not respond. The output signals of the emergency decoder 7802 are sent via the cable 7803 and the corresponding status conductors to the setting and reset connections of the flip-flops 79 ÄO, 79 TBLO and 79TBLl via the input OR gates 790I ₃ 7902, 7916, 7917,

ao 7918 and 7919 transferred. For example, a signal on the state ^ l conductor causes the setting of the flip-flop 79 RO, the setting of the flip-flop 79G50, the resetting of the flip-flop 79 GSl, the setting of the flip-flop 79 HSO, the resetting of the Flip-flops 79 TBLO and the setting of the flip-flop 79 TBLl. The following table shows the states of the control flip-flops after receiving a state Λ, a state Z? Or a state C signal.

'' ■■ 'State-
signal RO C750 GSl JISO HSl TBLO TBLl A.
B.
C. set
reset set
reset reset
set
no influence set
reset reset
set reset
set
set set
reset
set

In the table above it is indicated that when a memory is set to the state, ie, when the flip-flops 79 TBLO and 79 TBLl are set, the state of the other flip-flops is unimportant. Therefore, they are indicated in the above table to be in a state which does not exert any influence.

The "0" bus shown in Fig. 64 contains the following 25 bits like the "!" Bus:

A. 16 address bits A 0 to A 15;

B. 4 code bits KO to K3;

C. 4 partial bits CM, HM, GM, CRW and

D. 1 single synchronization bit.

Conversation memory 103 (Fig. 8)

The conversation mailbox system 103 comprises a plurality of independent conversation mailings. Any conversation memory consists of a large memory with random access, which in this embodiment is a ferrite plate memory with destructive Includes reading and the associated access reading and access writing circuitry.

The information capacity of a conversation memory 103 is like that of a program memory 102 in FIG Divided into halves. One half of the information is the left or H half and the other half of the information assigned to the right or G half.

To the use of odd numbers of call boxes within a call box system 103 while maintaining a complete duplication of the information in the storage system To enable the information is doubled according to the pattern shown in FIG.

Information is obtained from the call recording system 103 by a command from the central Controller 101 which designates an information group code name and an address, which indicates the location of the desired information word within the designated information group. In a similar way, information written into the call storage system 103 by a command from the central controller 101, which is an information group code name, an address indicating the location for the data and indicates the encoded data to be written into the designated information location.

As discussed above with respect to program storage system 102, each is a group of information permanently assigned a discrete code name, and since an information block is doubled in both memories is, both memories in which this information is located are arranged so that they are based on the information group code name speak to. In the case of the program memory 102, it is not possible to store the information in the memories of the program memory system 102 to rearrange. In the case of the conversation recorder 103, however, there is one in the event of a malfunction or more memory of the system the possibility of information to ensure the duplication rearrange certain important information. That is, certain information in the conversation logs 103 is of greater relative importance than other information. Therefore, it is desirable in the event of a call mail failure within call mail system 103, the information to duplicate the more important information at the expense of duplication rearrange less important information. Accordingly, although each conversation memory must respond to two information group code names, only one of the code names continuously assigned to a specific conversation partner, namely the code name in the left half of the The information group stored in the memory is permanently retained. The information capacity of the legal

A code name assigned to the half of a call log 103 can be changed by a command in the write control operation of the central controller 101 .

The transmission bus system 106 with the address and control buses 6401, the data buses 6402 and the response buses 6501, which are assigned to the central controller 101 and the conversation memory 103 alone, is used to transfer commands from the central controller 101 to the conversation memory 103 transfer. In addition, write data is transferred from the central controller 101 to the conversation memory 103 on it, and responses are returned from the conversation memory 103 to the central controller 101 . In addition to these three separate transmission paths, each call store 103 receives information from the central controller 101 through output signals from the central pulse distributor 143.

The connection of the address bus lines to a conversation memory 103 is shown in FIG.

Pulses on the five lines HM, GM, CM, R and W define the operation of the memory.

Central control 101 (Figs. 10 to 63)

The central controller 101, which is shown in simplified form in FIG. 9 and in detail in FIGS. 10 to 63, represents the data processing unit of the system. For explanation, the central controller 101 can be divided into three main parts:

1. Basic data processing facilities;

2. Equipment for the transmission of messages with input sources and output devices of the central control;

3. Maintenance facilities.

The central controller executes data processing functions in accordance with program instructions which are mainly stored in the program memory 102. In some special cases, the program commands are also stored in the conversation memory 103. The program instructions are arranged in orderly sequences within the memory. The program instructions can be divided into two main classes, namely decision instructions and non-decision instructions.

The central controller 101 is a synchronous system in the sense that the functions within the central controller 101 take place under the control of a polyphase microsecond clock source 6100 which supplies clock signals for performing all logical functions within the system. The clock signals derived from microsecond clock source 6100 are combined with DC signals from a number of sources in instruction combination gate circuit 3901. The details of the command combination gate circuit 3901 are not shown in the drawings because such a large number of details would only obscure the inventive principles of the system.

Work sequence of the central control

All functions of the system are carried out by executing command sequences which are obtained from the program memory 102 or the conversation memory 103 . Each command of a sequence causes the central controller 101 to carry out an operating step. An operating step can comprise several of the above-mentioned logical functions or also a decision and the generation and transmission of commands to other units of the system.

The central controller 101 executes the operational steps indicated by a command at times which are determined by the phases of the microsecond clock source 6100. Some of these operational steps take place simultaneously within the central controller 101 , while others are performed sequentially. The basic machine cycle, which in this exemplary embodiment lasts 5.5 μβεσ, is divided into three main phases of approximately the same length. To control successive processes within a main phase of the machine cycle, each phase is further subdivided into V2 μβεο long intervals that are ^{initiated every 1} U μβεό.

To denote the times, the main machine ^{cycle is subdivided into 1} U μβεσ long intervals, and the starting times of these intervals are identified by the designations TO to T ¹ Zl; Mistake. The main phases are called phase 1, phase 2 and phase 3. These phases lie in the machine cycle of 5.5 μ5βΰ as follows:

A. Phase 1 - r0 to T8,

B. Phase 2 - Γ10 to Γ16,
C. Phase 3 - 7 * 16 to Γ22.

To simplify both the following description and the drawings, time periods with bTe. where b is the number assigned to the point in time at which a time period begins, and e is the number assigned to the point in time at which a time period ends.

According to FIG. 61, each central controller has a clock oscillator 6106 for 2 MHz. The clock oscillator 6106 of the active central controller drives the microsecond clock source 6100 in both the active central controller and the standby central controller. The oscillator 6106 of the active central control is connected to the input of the microsecond clock source 6100 of the active central control via the AND gate 6108 and the OR gate 6110 . The AND gate 6108 is energized by a signal on the command line conductor 6 \ AU , which indicates that the activity flip-flop 55 AU is in the "1" state. The output of the oscillator 6106 is transmitted to the other central controller via the conductor 6111, the amplifier 6112, the transmitter 6113 and a link transmission pair.

In order to achieve a maximum data processing capacity of the central controller 101 , a three-cycle overlap is used. In this mode of operation, the central control simultaneously carries out the following processes:

A. The operational step for an instruction;

B. Receiving the command from program memory 102 for the next operational step;

C. Sending an address to the program memory 102 for the next but one instruction.

The three cycle overlap is made possible by having both an instruction word buffer register

109 516/268

17 18

2410 as well as a command word register 3403 and their additionally required time and is not necessarily corresponding Decoders are provided, namely the wise an integer multiple of a machine command word buffer decoder 3902 and the command cycle. On the other hand, the subsequent circuits, the word decoder 3903, lead. A mixing decoder 3903 solves delays in the execution of other commands Developments between the program words in the 5 always lead to delays, the integer Command word register 3403 and the command word are multiples of machine cycles. .:, Buffer Register 2410. The Command Word Auxiliary Buffer The sequential circuits take on the controller register 1901 simultaneous time differences of the prod data processing within the central control frame memory response time the end. tion 101 with the decoders, i. H. the command word

The start gate signals for the command Z - here io buffer decoder 3902 (BOWD), the command word decals index cycle - are part of the command the 3904 (OWD) and the mixing decoder 3903 word buffer decoder 3902 when the command (MXD) occurs . For commands in which the additional miss X is derived in the command word buffer register 2410. Work functions before the start of the execution cycle The command X is (while it is still being carried out in the command-, the sequential circuit controls the word buffer register 2410 for the index cycle) 15 central control 101 excluding the decoder during phase 3 of cycle 2 the command word- BOWD, OWD and MXD (Fig. 9). Jeregister 3403 is supplied for instructions. After reaching the command but, in which the additional work functions word register 3403, the end gate processes are carried out during and immediately after the execution for the command X, here with the execution cycle of the command, with the help of the command word decoder 3904 20 sequential circuits and the decoder together and controlled. at the same time the central control 101. In the latter

The duration of the index cycle and the execution case, a number of restrictions occurs for the cycle is each smaller than a machine cycle of commands that follow a command that requires the Erre-5.5 μβεα When executing operational steps, a sequential circuit is required . This one sequence of commands remains each command each 25 restriction ensure that the elements of the 5.5 μβεΰ in the command word buffer register 2410 and central control, which are controlled by the sequential circuit ge-5,5 yß & c in the command word register 3403. The command , cannot be controlled simultaneously by the pro word buffer decoder 3902 and the command word decoder program command words.
3904 are direct current combination circuits. Each sequential circuit has a counting circuit. The DC output signals of the decoders will define their states which are to be output by the sequential circuit with selected pulses from the microsecond leading gate functions. The excitation of the clock source in the command combination gate switch of a sequential circuit is that its counter is combined in 3901. This circuit 3901 generates gear is brought. The output signals of the counting according to the correct sequence of gate signals are used with other information signals in the execution of the index cycle and the execution of the central controller 101 and with selected cycle of each sequence of instructions in the order, clock pulses for generating gate signals in which they are first in the command word buffer register 2410 of the command combination gate circuit 3901 and then occur in the command word register 3403. amated. These gate signals carry the required

The implementation of the operational steps for certain gate functions of the sequential circuit by and issuing commands requires more time than an operational step- 40 starting the counting circuit, its sequence of internal period, d. H. more than 5.5 μεεα This need to go through states.

Additional time can be an essential property of the sequential circuits that determine the duration of a Bedes command. In other cases, the requirement of the operating step is determined by taking control of an additional time, however, by the fault central controller 101 displayed, excluding the deco states that prolong the BOWD, OWD and MXD when executing a command. If an instruction indicates that its arranged to take the address of the next execution longer than one operating step period of the program instruction word concurrently with the termination, the additional processing time for its gate functions can be transferred. Therefore, this command will be obtained in the following way: although the execution of the command will be delayed,

50 which immediately follows a command for which the subsequent

1. Implementation of the additional data processing circuit of the type specified above has been excited tion during and immediately after the index is maintained, the degree of overlap.

cycle of the command and before the execution sequence circuits that the decoders BOWD, OWD

cycle of command; and MXD (Fig. 9) do not rule out lead to

2. Performing the additional data processing 55 an additional overlap. That means that the processing during and immediately after the transmission of the address of a command and the abnormal Execution cycle of the command. would take the command immediately following a command

follows, for which a sequential circuit has been excited,

The implementation of this additional labor cannot be delayed. The additional gate function circuits required for such subsequent switching functions with the aid of a large number of subsequent circuits within the central controller 101 are not only achieved simultaneously with the index cycle. These sequential circuits are individual structures of the immediately following command, but also that are excited by assigned program commands or faults simultaneously with at least part of the execution displays and serve to guide the cycle of the immediately following command through time for the operating step via the normal operation. . :
to extend the drive step period. The time, some examples are intended to illustrate the usefulness of the sequence by which the normal operating step period interconnections. A program instruction which is to be extended changes depending on the reading of data from the program memory 102

is used, requires an additional period of two 5.5 ^ sec machine cycles to perform. With this type of command, the additional two cycles are obtained by delaying the acceptance of the command immediately following and by performing the additional work functions after the index cycle has ended and before the execution cycle of the command currently being processed.

If errors occur when reading words from the program memory 102, the Program memory correction reread sequence circuit 5301 energized for a correction or rereading j of the program memory 102 at the previously addressed location. This sequential circuit represents j represents an example of a sequential circuit that is excited by j a fault display and the control of the central controller 101 to the exclusion of the decoder takes over.

The command-command sequencer 4902, the network commands to the switching network 120 and the mixed network units, i.e. H. the main scanner 144, the billing unit 147 and the card writer 146, is an example of the sequential circuits that follow their excitation increase the degree of overlap, d. This means that the transmission of network commands in, stretches the execution cycle of the command following the network command command.

Response of the central controller to program command words

Fig. 9 shows a simplified circuit diagram of the central Controller 101 and facilitates understanding of the main operational steps carried out by the central Control 101 can be performed on the basis of various program instruction words. Any program command word contains an operation field, a data address field and a Hamming error indication and correction bit.

The operating field is a binary word with 14 or 16 bits that defines the command and indicates the operating steps which are to be carried out by the central controller 101 are to be carried out on the basis of the command.

There are groups of optional, additional command options that can be selected by each of the Program instruction words can be determined. j The operational step of each command consists of one certain group of gate functions for processing contained in the central controller 101 Data and / or for the exchange of information between the central controller 101 and other units of the system. If an optional, additional option by the person to be carried out Program command is determined, additional data processing is carried out in the operating step. The special gate functions and those performed for each optional additional option Data processing is described elsewhere. Part of the 14- or 16-bit operational field of a program command word defines the program command, and the rest of the field can select one or more of the additional options to be performed.

In the index method, the content of the designated index register is normally taken from its output to the uncovered collecting line 2014 and from there to the summand register 2908.

However, if successive commands use the same index register as the destination register for a memory reading and as the source register indicate, there is not enough time to hand over the To carry out information to the destination register. In these cases the mixer decoder transfers 3903 therefore the desired information from the concealed collecting line 2011 directly to the summand register 2908 at the time when this information was transferred to the specified index register will.

Cover and complement circuit 2000 (M & C)

The internal data processing is based on two multi-conductor collecting lines, the uncovered collecting line 2014 (UB) and the concealed collecting line 2011 (MB), which represent a link for the transmission of a multi-bit data word from a certain group of flip-flop registers to another group . This group consists of the index registers 2601 (BR), 5801 (FR), 5802 (JR), 4001 (KR), 2501 (XR), 3001 (YR) and 3002 (ZR) and the logic register 2508 (LR).

The cover and complement circuit 2000 (M & C) connects the uncovered manifold UB with the concealed manifold MB and represents a device for the logical processing of the data that go from the uncovered manifold UB to the concealed manifold MB . The logical operations to be carried out, namely a coincidence masking (AND), a mixed masking (OR), an exclusive-OR-masking (exclusive-OR) and complementing, are prescribed by the operating field of the program command, either by the command word buffer decoder BOWD or the Command word decoder OWD is decoded.

The cover and complement circuit M & C (2000), which is shown in more detail in FIG. 20 shown also provides a convenient means of interconnecting the data buffer register 2601 and the index adder output register 3401 with the concealed collecting line 2011.

K register 4001 (KR); K-Logic (KLOG);
First-One Indicator Circuit 5415 (DFO)

The Z register KR, the K logic KLOG and the first-one display circuit 5415 (DFO) constitute a second important internal data processing means.

The K logic KLOG has input and output circuits surrounding the K register 4001. The X logic KLOG contains the iL4 input register 3502, the Xβ input register 3504, the K input logic 3505, the jK logic homogeneity circuit 4502 and, at the output of the X register 4001, the rotation shift circuit 4500 and the X registers Homogeneity circuit 4503. The K logic KLOG can be caused to carry out one of four logical operations on two operators by output signals from the command combination gate OCG. One operator is the content of the X register KR, the other is the information on the hidden bus MB. The command word decoder OWD and the X register sequence circuit (part of SEQ) generate signals which cause the X logic KLOG to combine the two operators using the functions AND, OR, exclusive OR or addition. The result of the logical connection

21 22

The end word can be shifted by one to the right according to the command in the left, etc.

Missing word register OWR either to the K register means that the content of each flip-flop of the K-Re- KR or to the homogeneity control circuit CH registers KR to the one on the right-hand side.

and the sign control circuit CS is given the flip-flop. A "0" replaces the

will. 5 Content of the bit of the highest digit of the K-Re-

A word on the hidden bus MB gisters KR, and the original bit of the lowest

can in some cases go directly to the K-Register KR digit position of the K-Register KR will consequently fall-

can be given via the K logic KLOG . The K-relieved .

In this way, gister KR can be used as a simple logic function similar to a shift

Mood registers can be used for data, like the io is the "rotation" function. As with the different

other flip-flop registers in the central control are the 6 bits of the index adder IA as

tion, for example XR, YR, ZR etc. Direction and magnitude of the rotation are treated as

When performing the addition function in the above described for the shift. K logic KLOG , the two operators are treated as a rotation by one to the left is signed numbers of 22 bits, shifting with one is identical with the exception of the delt. The 23rd bit of each operator is the sign control of the two end flip-flops of the K register bit. If this bit has the value "0", the number is KR. In the case of a rotation by one to the left, it is positive, and its size is not indicated by the remaining contents of bit 22 as in the case of the shift ver-22 bits. If the sign bit is "1" but replaces the content of the O-bit, the number is negative and its size is given by the 20 lowest digit of the K register KR. A rotation by two to the left given the complements to 1 of the remaining 22 bits is identical to two j (the size is determined by inverting each of the 22-bit consecutive rotations by one to the left). The adding circuit within the Another logical gate function is the Be-K logic KLOG can correctly add all positive and negative moods of the "1" on the right in the content of the K register KR am wei operators as long as the size 25 test. This is achieved in that the algebraic sum of the two operators the content of the first-one display circuit DFO is equal to or less than 2 ²² -1. F register FR via the uncovered bus line The .K logic KLOG and the K register KR can UB, the masking and complement circuit M&C nen also other logical functions with the content and the concealed bus line MB is supplied to the K register Execute KR . One of these func- 30 The transmitted number is a binary number with 5 bits, the name "shift" has been given. which corresponds to the first cell (seen from the right) in the K-Re-Die in the event of a shift carried out the gate register KR which contains a “1”. If the function is partly based on the bits of the last bit of the lowest digit of the K register KR six digits of the number that is a "1" in the indexaddie, the count 0 of the F register FR becomes xexlA at the time occurs in which the seduced 35. When the first "1" is to be shifted as seen from the right. If the bits of the last five are in the next digit, the number 1 digit will represent a number that defines the size of the F-register FR . If a single "1" indicates a shift, and the 6th bit, which is in the highest digit in the K register KR , determines the direction of the shift. A "0" for the 6th bit is given the number 22 to the F register. If it is interpreted as a shift to the left, and the 40 in the K register does not contain any "1" values, nothing is added to the remaining 5 bits indicating the size of this shift in the F register FR. A "1" for the 6th bit is interpreted as a shift,., "_ ^ _" _T \ to the right, and the complements to 1 of the decision logic 3906 (DECL) the remaining 5 bits show the size of the shift at the exit to the right. Although in the case of shifts after a decision command in a sequence from the right, the bits of the last digits contain the complex commands either in the current sequence from ments to 1 for the size of the shift or jump to a new sequence of ten the number with 6 bits is treated like this in the following commands. The decision will be made by the decider as if it had a sign and logic 3906 (DECL) corresponding to the command, size. 50 which is currently being processed. The command A shift by one to the left results in the information to be checked and the basis for the content of each flip-flop in the K register KR to the decision. The information can be obtained from the homogeneity control flip-flop 5020, which is adjacent to the flip-flop on the left-hand side and is homogeneous when the register corresponds to the fact-control circuit CH, the sign-control figure; 40 is considered. (The bit of the highest 55 flip-flop 5413, the sign control circuit CS digit position of the K register KR, bit 22, is located or the KLOG bit can be obtained from selected output signals of the K logic on the extreme left. The basis for the lowest digit, the bit 0, is based on the decision, that the checked the rightmost side.) A "0" replaces the information (not or at least) arithmetically zero, content of the lowest bit digit of the K-Re- 60 is less than zero, greater than zero, and so on. A gisters KR (to the right of the flip-flop of the "0" digit continuation decision interferes with the current position, there is no flip-flop), and the bit of the sequence for the extraction and execution of the highest digit position is out of the register - Don't give orders. A decision to jump has been postponed, ie the flip-flop for bit 22 is open. There is no flip-flop adjacent to the left on the left-hand side, and the 65 corresponding to the specific, executed command with information is lost. coupled to a determination as to whether the shift by two to the left corresponds to two jump is an "early jump" or a "late consecutive shift by one jump". Accordingly, if the

The decision to jump is that either the early jump ladder ETR or the late jump ladder LTR are energized and the jump sequence circuit 4401 is activated, jump signals from these ladders cause the jump address to be fed to the program address register PAR. This register causes the next program instruction word to be obtained from a new sequence of instruction words.

Two sources of input information for the decision logic are in the outputs of the homogeneity control flip-flop and the sign control flip-flop which are used to register homogeneity and sign information from a number of locations. For example, a data word with 23 bits can be transmitted on the concealed bus line MB to the homogeneity control circuit CH. If the data word contains either only "O" values or only "1" values, the homogeneity flip-flop 5020 is set. Otherwise the flip-flop is reset. The sign control circuit CS retains the sign of the data word. The sign control flip-flop 5413 is set if the word is negative and reset if the word is positive.

The homogeneity control circuit CH and the sign control circuit CS are used for some decision commands in such a way that the output signals of a selected index register are sent to the uncovered bus UB, through the cover and complementary circuit M&C, to the concealed bus MB and from there into the homogeneity Control circuit CH and the sign control circuit CS are given. As a result, the content of one of the seven index registers, which is specified in the processed decision command, is identified in the homogeneity flip-flop 5020 and the sign control flip-flop 5413. Further gate functions in connection with a decision command execute the jump or the progress according to the output signals of the decision logic DECL.

Similar homogeneity and sign circuits form part of the X logic KLOG and represent facilities for a class of decision commands that cause a jump or a continuation according to combinations of the homogeneity and the sign of words with 23 bits in the X register KR .

Message transmission between the central
Controller 101 and connected units

A second main function of the central controller 101 is the transmission of messages to and the reception of messages from various other entities, such as the various memories within the central data processor 100, the switching network 120, the main scanner 144, the central impulse distributor 143 etc.

Message traffic is of three general types. The first type relates to the extraction of program instruction words which determine the sequence of processes within the central controller 101. Program instruction words are primarily obtained from program memory 102. In special cases, however, program command words for restricted processes are also obtained from a conversation memory 103. The second type comprises the extraction of data (not program instruction words) from the storage units within the central data processor 100, and the third type relates to the generation and transmission of commands to the various network units, such as the switching network 120, the main scanner 144 _{S and} the central pulse -ίο distributor 143 etc.

The various memories within the central data processor 100, namely the program memory 102, the conversation memory 103, the auxiliary buffer registers 3105, 3118, 3605, 3617, 4103, 4603, 5105 to 5107, 5500, 5902, 6205, 3206, 3703 to 3708, 4206, 4211 , 4717, 2725, 5201, 5209 to 5211, 5604, 5605, 6002, 6003, 6302 and 6307 (ABR-I ... ABR-N) and certain other locations within the central controller 101 are treated as storage units, and certain blocks of addresses are individually assigned to each of the memories. There are a number of memory cells which are used to selectively extract information from the aforementioned memories and enter that information into selected registers within the central controller 101. These are memory read commands. There are other memory instructions which are used to selectively transfer data from designated registers within the central controller 101 to one of the aforementioned memories. These are memory write commands. In this way, the command structure is simplified, since all of the above-mentioned memory locations are accessed using a single memory address format.

A memory address within the central controller 101 always contains a word with 20 bits, consisting of:

1. a code to define an information block and
2. an address within the specified block.

Program instruction words

The transmission between the central controller

101 and the program memory 102 for obtaining program instruction words can be seen with reference to FIGS. 9 and in more detail with reference to FIGS. 10 to 63. The program address register 4801 (PAR) and the auxiliary storage register 4812 (ASR) are optionally used to transfer commands to the program memory 102. The program address register 4801 is used in the absence of uncorrectable program memory read errors. The auxiliary storage register 4812 is used whenever a program memory

102 must be read again. When an instruction is received from the program address register 4801 is transferred to the program memory address bus system 6400, the code address becomes of the command is also given to auxiliary storage register 4812. The auxiliary storage register 4812 therefore takes the code address that is used to perform the Hamming error checks. These exams are used simultaneously on the returned command and the one used to obtain the command Address applied. Commands to the program

109516/208

memory 102 for reading information from the memory itself as opposed to addressing of checkpoints within the memory access and control circuits contain 25 bits as follows:

A. 16 address bits A 0 ibis A 15,

B. 4 code bits KO to K3,

C. 4 operating mode bits CM, HM, GM, CRW,

D. a single synchronization bit SYNC.

IO

The code bits KO to K 3 define the information block in which the selected program memory word is located, and the address bits A 0 to A 15 define the memory location within the defined information block.

The four operating mode bits define the operating mode of the program memory as follows: Note, that the program memory 102 in obtaining program instruction words and system operating data words is always operated in the normal way of working. The two maintenance modes and the read control and write control operations are for obtaining information reserved from the program memory to be treated as maintenance data.

The code and address parts of the program memory instructions are taken from the program address register 4801 or the auxiliary storage register 4812 and the 4 operating mode bits and the synchronization bit from the command cable 3900. The 4 working mode bits must be used in all working modes Other than the normal, they can optionally differ from "0", and in these modes of operation they are replaced by the executed program instruction words defined.

The program memories - transmission trunk selection gates 3300 are divided into two groups, those for transmission to the "O" bus 3306 of the program memory address bus system 6400 can be used, and those belonging to the "!" Bus 3307 of the program memory address bus system 6400 are assigned. The command information becomes optionally the "O" bus of the program memory address bus system 6400 according to the used combination of the program memory central control bus lines fed. When information from the central controller 101 to the program memory 102 over the "O" bus 3306 is transmitted, the AND gates 3302, 3308 and 3312 and the Amplifier 3310 used. However, when commands are transmitted over the "1" bus 3307, AND gates 3303, 3309 and 3313 and amplifier 3311 are used.

The program memory - transmission bus selection gates 3300 are optionally energized according to the setting of the state and path register flip-flops AU, PBO, PBA and PBT controlled by the central pulse distributor. The state of the flip-flops AU indicates which of the two units is the active central control. The flip-flops PBO, PBA and PBT have the following meaning (with the exception of commands for read or write control or maintenance data):

PBA PBT Active Receive Reserve- Receive PBO Central control O Central control 1 O O Send 1 Send O O 1 O O O 1 1 O O O 1 1 O O τ — Ι 1 O Oil O X O 1 O 1 Oil 1 X 1 1 1 1 Oil X 1 Oil X

In the table above, the X sign means that the standby central control is not on the "0" - still on the "!" - collecting line sends because the active central control is on both collecting lines transmits.

The state and path flip-flops AU, PBA, PBO and PBT are selectively set and reset by pulses from the central pulse distributor 143 via selected pairs of the bipolar cable 6700, the transformer 1707, the amplifiers 1708 and 1711, AND gates 1709 and 1712 and the CPD cable 1719 can be received.

The flip-flops PBO, PBA and PBT in the two central controllers are controlled by the same CPD points, ie if the flip-flop PBO is set in the first central controller, its counterpart PBO is also set in the other central controller. The flip-flops AU (active unit) in the two central controls are also controlled by a single bipolar signal point of the central pulse distributor. The bipolar signal that causes the setting of the flip-flop AU in the first central controller, however, resets the flip-flop AU in the second central controller. Similarly, the CPÖ signal, which resets the flip-flop AU in the first central controller, causes the flip-flop AU to be set in the second central controller.

The information required to determine the code address of a program store instruction is the program address register 4801 via one of three possible routes, the selected Path is determined by the sequence of events which are used to determine the desired address and lead the code. The desired code address is optionally obtained using one of the following methods won:

A. When executing a sequence of program instruction words and in the absence of a jump decision, the code address of the next instruction word in the sequence is incremented the code address of the previous command word obtained by the count value 1.

This increase is made using add-one register 4304 and add-one logic 4305 causes.

B. The second source of program memory code address words is the index add output register 3401. This register is provided to store the DAR word as described above. The contents of the index add output register 3401 are transferred to the program storage register 4801 via cable 3402, AND gate 4307 and OR gate 4808. This transfer of information is achieved by energizing the command wire header IRPA .

C. The third source of code address information is hidden bus 2011, the contents of which are provided to program address register 4801 via cable 4313, AND gate 4308 and OR gate 4808 at time 3 → 5 by energizing instruction wire MBPA . This path is used in the event of interrupts to supply code address words from the interrupt address source 3411 to the program address register 4801, and is also used for early jump instructions to supply the contents of the / register 5802 or the Z register 3002 to the program address register 4801.

Accordingly, program memory response bus select gates 1200 are energized by command cable signals on conductors 12PSiSO and HPSB1 in time period 19Γ8. This ensures that the full pulse width (approx. 0.5 μβεϋ) of the program memory response is received.

The 44-bit response word is transmitted over OR gate 1209 and cable 1210 and into auxiliary command word buffer registers 1901 and the command word buffer register 2410 is entered. Bits 0 through 20 (the data address field) and bits 37 to 43 (the Hamming coding bits) are entered directly into the command word buffer register 2410 via AND gates 1907 and 1906 and OR gates 2428 and 2425 given. Bits 21 through 36 (the operational field) become into the auxiliary command word buffer register 1901 via the AND gate 1905 entered. The synchronization signal is transmitted through OR gate 1211 and used to excite AND gates 1905, 1906 and 1907, which serve to convert the received 44-bit word from the auxiliary command word buffer register 1901 and the command word buffer register 2410 to be fed.

The all-seems-well signal represents when it comes from the "O" bus 6500-0 is received, the flip-flop 1214 in its "1" state, and if it comes from the "!" bus 6500-1, the flip-flop 1213 enters its "1" state. The flip flops 1213 and 1214 represent two capture signals for the error indication and correction circuit 2400. A The all-seems-good signal that is missing when a program memory response is received indicates a possible Malfunction within the program memory 102. Hence the validity of the answer is questionable.

Call memory read commands

When executing call memory read commands, the response contains a data word with 24 bits, an all-seems-good signal and a synchronization signal, which occur as pulses with a length of ¹ It \ iSQC on the call memory-reply bus system 6501. The word with 24 bits contains 23 information bits which are to be used for data processing within the central controller 101, and a data parity bit. The chat log reply signals appear in parallel at the input terminals of the chat log reply bus select gates 1300. The gates 1300 are selectively energized to accept the reply from the "O" bus 6501-0 or from the "!" Bus 6501-1 to record. The excitation of the gates is determined according to the setting of the state and path flip-flops controlled by the central pulse distributor.

The information received from the data buffer register 2601 and the special flip-flops 1313 and 1314 is single-track. Therefore, the data buffer register 2601 and special flip-flops 1313 and 1314 are reset before the time the information is received. The energization of the command line conductors REBR and REBRP resets the data buffer register 2601 and a signal on the command line conductor RECER resets the special flip-flops 1313 and 1314.

Call memory error indicator circuit 2200

When data is obtained from the conversation memory 103 on the basis of memory read commands, the DA parity generator 2609 is used to check the parity of the received data and the address transmitted to obtain this data. The status of the conductor 2418 indicates the parity of the code address with 18 bits, and the content of the data buffer register 2601 with the 24th bit supplies the remaining input signals to the DA parity generator 2609. The parity of the returned data including the address used to obtain the data should be odd. In the event of a parity error, a signal is transmitted on the PF conductor 2607 to the call log error indication circuit 2200.

The call log fault indicator circuit 2200 sums the assembly tests performed in executing call log commands. The inputs to the call memory error indication circuit 2200 are provided on the call memory synchronization signal conductors CSS1 and CSS 0, the call memory seem-good conductors ASWCSQ and ASWCS1, the parity error conductor 2607, and the command cable ladders CSCK and READCK . The call log error indicator circuit 2200 is actuated by a signal on the command line conductor CSCK, and when a parity check of a data reading is to be performed, the command line conductor READCK is also energized. If one or more of the above assembly tests fail, the call log fault indicator circuit 2200 energizes the output conductor CERI. A signal on the CERI line sets the CSjEZ flip-flop 2201 which then energizes the memory re-read sequence circuit 5700, the function of which will be described later. AND gate 2700 is energized by a signal on the command wire CSX and transmits the error indication on the CERI wire to the other central controller. The conversation memory

29 30

cher error indicator circuit 2200 will switch units for normal gram sequence. That is, the active one

Call memory commands excited. For the mainte- nance, central control unit, it becomes a reserve unit.

She will do control read and write commands, and the reserve control unit will be the same.

not aroused. early the active unit. This switchover takes place

5 by a CP £> command that the CPD-controlled

Message traffic status flip-flops AU in both central control

switch units at the same time using command commands. The state of this

The third main type of message traffic is flip-flops, the associated central controller, the generation and transmission of »commands in the reserve or active state. By feedback to the central pulse distributor 143, the adjustment of the flip-flop AU , an active central switching network 120, the main scanner 144 etc. control is switched to the reserve state.
These commands are used to control the central control 101, the program memory 102, the central control 101, the program memory 102, the

The central controller 101 uses program 15 call memory 103 and connecting address commands, here called "command" commands, for generating and answering manifold systems) to generate two such commands. Certain of these separate or partially shared duplicates errors generate commands that are only compiled to the central one of a central data processor Pulse distributor 143 are to be transmitted. These commands are. The active central control unit is the core are referred to here as "CPD commands", and the 20 of an "active central data processor", and the Commands assigned to these commands are reserved. Central control is used in the »Reserveais »CPD commands«. Other Korn Data Processors «. The doubled central data command commands generate information on the network processors are advantageously based on in the system Plant Command Bus 6406. These are used in two ways. The first type is the operation of the Called "network command commands" and the data processors doubled in "lock step", generation of information on the network com- That is, the active and the reserve data processing bus 6406 will carry out the same program sequences (from the selmandos " designated. Network command commands or doubled program storage units) are used to transfer information not only from, read and write data (from the same or to the switching network 120, but to all 30 duplicated call storage units), but only Units used, which are connected to the central controller 101, the active central data processor controls the zenüber the network command bus line 6406 tral impulse distributor 143 and the network coman connected such as the main command units. In the second operating mode, the scanner 144, the teleprinting unit 145, etc. From active central data processors, the call processing reasons For the sake of simplicity, these units are 35 working function by using a the group of program sequences with the help of the network command group during the reserve system 6406, »Network data processor carries out diagnostic tests under Called command units «. The network com- use of other program sequences and only mandobefehl uses the CPD command to deal with non-common units of the doubled drawing of a specific network command 4 ° central data processor.

unit that respond to the network command In the first mode of operation, the double targeting, execution of program sequences within the central _Λ,. , _.,.,.,, Data processor 100 used to detect the occurrence of cross-connection of error signals m of the central disturbances by a periodic comparison of control 101 ₄₅ strategic data processing nodes in

The central controller 101 is duplicated to display both central control units. (At and at each point in time one of the two units in this exemplary embodiment is two word pairs are compared as "active unit" and the other as "reserve in a cycle of 5.5 μβεσ.) The united unit" is referred to. The active unit carries out the same nodes containing the uncovered entire call data processing and the largest 50 trunk 2014, the hidden trunk part of the maintenance program sequences. That is, 2011, the index add output register 3401 and that in most cases the control of the remote data buffer register 2601, the program address speech switching system on the execution of register 4801, the instruction word buffer register 2410 program sequences within the active central and sequential circuit checkpoints .
Control unit is based. It is possible that the reserve 55 - _T
Central control unit from the same program sequences
leads, but it does not transmit any CP £> commands or network commands in the course of normal call processing and therefore has no direct malfunctions. The first systems. If there are difficulties in the operation of the attempt to recover the call processing center data processor 100 by one or the ability to work when a fault is displayed, several module or program tests are carried out with the aid of program sequences which are shown calculated in such a way that remedial maintenance programs are used to identify faulty faults Under-demanded, in which it can be shown that the groups of the system are narrowing down and the combined difficulty lies within the active central control positions of components with respect to the fault unit. If this is the case, the system "switches" to rearrange the adherent subgroups. This emergency action follow-up circuit 5702 or an attempt can only be successful if one of the active central control units carried out a pro-operable combination of a central one

31 32

Control, a program memory and a functions largely mutilate and so to a connecting manifold system at the moment highly unsatisfactory operation of the part is active. That is, although each of these elements lead to takers. Accordingly, a number t is doubled and although only one of the elements doubled by special, independent test circuits in the ι may have failed, central control 101 is provided to determine this doubling of no use when the central basic classes of faults. If controller 101 does not currently fail any of these independent tests within the active component combination using the active central controller, then using the active central controller

- ι is able to correctly program information either the emergency measures sequential circuit 5702 in the zenzu edit or win. That means, it must, io tral control excites and takes measures,

so that the central data processor 100 corrects its area around these disturbances. The basic cases

ability to process calls with the help of errors - which lead to an excitement of the emergency measures - follow-up -

- j recover recognition program sequences can lead circuit 5702 and the by independent r i and program rearrangements are combated by faulty test circuits, the following are

- j can perform subgroups, initially a 15 den:

- ^! Active, error-free combination of a central 1. Some of the sequential circuits, the certain control functions and a connecting bus repeating control functions are available in the system. If one of the subassemblies lead, the control of the central ι i tests detects a fault that the central controller 101, excluding the decoder 3902 -, i controller 101, the program memory 102 or the 20 to 3904. The occurrence of a fault in a or

• j conversation memory 103 is concerned, the emergency measure- several of these sequential circuits can do so

- ι men-40-ms key circuit of the real-time tester 5703 lead that this follow-up circuit is continuously in: excited and not reset until the call remains active. The ¹ sequential circuit would

• I the ability to process the central data processing - then the continuation of the conversation handling . ι ters 100 is ensured. That is, after locking permanently. Accordingly, the sixth

j it has been established that a reorganization of sub-level binary counters (the time lapse counter 4109) groups of the system with the help of program uses was possible in order to enable the active periods of these subsequent switching functions, the emergency measures will be summed up. That is, if one of these clock circuits is reset to prevent unwanted emergency follow-up circuits, the time-out counter will prevent action. However, if a 30 4109 is advanced and deferred once in every 5.5 nsec machine cycle recovery of the call processing capability when the sequence of the central data processor 100 was not possible with the aid of circuitry brought back to its inactive state by program functions. The subsequent switching and the emergency measures 40 ms clock switching off and on checked in this way are:
supplies one of the various signals for excitation 35

the emergency measures sequential circuit 5702. This jump sequential circuit 4401,

Sequence circuit is designed in such a way that it interrupts sequence circuit 4901,

call processing capability of the central data reading sequence circuit 4903,

processor recovers without the program return sequencer 5300,

Functions for carrying out re-orders 40 Program memory correction-re-reading

of components in the active combination of a sequence circuit 5301,

central control, a program memory and call memory-program sequence switch

connecting manifolds are required. The tion 5302,

Emergency measures follow-up circuit 5702 uses per call memory re-read follow-up program sequences taken from the program memory 102 45 tang 5700.
to evaluate their independent corrective actions. The remedial measures During every 5.5 ^ sec cycle in which one or, with reference to the rearrangement of components, several of the above-mentioned sequential circuits are in the active state with the help of device measures, the timing, i.e. Schaltangen, is in contrast to program measure - 50 counter 4109 performed by a signal on the command cable name. Head of TOC-INC forwarded. If none of these

As stated above, if the emergency response follow-up switch is active, a signal occurs while

40 ms clock switching only one of the different ones of the 5.5 ^ sec cycle on the instruction cable ladder

Signals indicating the excitation of Emergency Measures-Follow- TOC-R to the timeout counter 4109 in the

cause circuit 5702. To bring 55 zero state (000000) or in this

Keep the display of malfunctions with the help of Pro-. Note that the monitoring of the program tests and assembly tests, the subsequent switching only one of the purposes accompany normal conversation processing, one of the time-out counter is 4109 and that the above is an obvious source of information indicating that explanation only applies if the comparison control that the system is unable to use its normal 60 registers 4103 to time-out follow-up work functions perform. But there are still circuits indicating.

a number of other basic circumstances which become the outputs of the time-out counter 4109

Serious operational malfunctions of the system can be seen with the aid of the timing comparison circuit 4108

and not with the help of this program with the outputs of the timing counter

tests and assembly tests detectable 65 TOCRS ... TOCR-O compared. The lapse of time

are. If no corrective action has been taken, counting register TOCR-S - TOCR-O is at a value

these undetectable malfunctions can be preset, which corresponds to the maximum number of machine

the telephone processing and the maintenance radio cycles correspond during which the monitored

33 34

Follow-up circuits should be continuously active. processing sequences are arranged. This check if the number in the timeout counter 4109 corresponds to the check described above, which is in the timeout register TOCRS. .. TOCR-O is reached, to ensure that none of the output conductor SQC is energized. A signal on subsequent switching is stuck.
5 The real-time tester 5703 contains a Siebentung5702 and sets the flip-flop SETO (Fig. 52) step binary counter, which every 10 ms by the occurrence of the even 5 ms output pulses of the milli-

The above-mentioned sequential circuits will continue to be monitored in this manner for the second clock source 6101 on conductor / -5, since the program is switched off. The real-time checker 5703 has interruptions and even the level B emergency measures - io dem, as stated above, an analog 40 ms interruption of the completion of the functions of this clock generator, which further above than the emergency measure sequence circuits allow before the interruption men- 40 ms clock circuit has been designated. Which is running. As noted above, not all sequential circuits within the 40 msec clock circuit of the central controller 101 are used in this way to ensure that a display is monitored. However, other measures are taken for faults within the central data processing system for fault detection, in order to ensure that these faults are cleared within 40 ms and that they operate correctly. For example, that will be. The 40 ms clock circuit works on the analog emergency measures sequential circuit 5702, not on a superordinate basis instead of on a digital basis, and is kept watch because it is not capable of correcting its internal errors on its own when various, more independent, errors are carried out . Instead, 20 tests are used, which are carried out on a mutually exclusive basis with the aid of a maintenance routine program sequence. In the course of checking that the emergency measures follow-up circuit 5702 of normal call processing, the analogue is temporarily excited and the resulting effect of the 40 ms clock circuit for monitoring is monitored, the even and odd 5 ms pulses occur

The stop sequencer 4400 is not used directly, and in the event that these pulses are used for

monitored because the immediate tester 5703 the emergency measure- more than a few, consecutive 5-ms

action sequence circuit 5702 , if intervals do not occur, the 40 ms emergency action counts.

it remains in the active state. took clock circuit off and energized the conductor AT.

The command sequence circuit 4902 is A signal on the AT conductor excites the emergency measure

also excluded from the timing check, 30 men follower circuit 5702 and sets the flip-flop

because in the course of their normal functions they take LTO for a long time.

Can execute sequences of command commands and As will be described later, the

can therefore be active for relatively long time intervals, 40 ms emergency measures analog clock circuit of the

which the time interval in the time-out counting register real-time checker 5703 also to support the

Exceed TOCR-S ... TOCR-O . In addition, a "reason counter" is used, which is located within the

the monitoring of both this sequential circuit and the millisecond clock circuit 6101 is located,

The X register sequential circuit 5701 is also not critical. A real-time test cycle lasts a maximum of 640 ms.

table, because the interrupt sequencer 4901 At the beginning of this cycle, the seven-stage

can also be excited when the 2 ^ register real-time counter of the real-time tester in the NuIl-Zu- ^

Sequence circuit 5701 or the command command status 4 ° set. The even 5 ms pulses on the

Sequence circuit 4902 remains active. Head of JS switch this counter on and on

2. The output connections of the microsecond lapse of 320 ms, which is indicated by the level 6 of the counter set in the "1" to clock source 6100 are directly connected to the clock check 6103 , is switched on, which is the clock output signals creates a real-time test "window" condition. I'm closely monitored. If one or more of the 45 plan of the call processing programs are clock signals does not occur, a signal is present on the program commands, which generates two specific output conductors CKC , which generate one of the input commands of the central pulse distributor, signals of the command combination gate circuit 3901 namely a real-time test setting command (RT-S) , which causes the command cable conductor to be energized and a real-time test reset command (RT-R), EA GO . In this way, the emergency measures sequential circuit 5702 is again excited within prescribed time limits and the result occurs. The CPD command for the RT-S set the flip-flop CjE. Since the microsecond signal occurs some time after 320 ms of the clock source 6100 has elapsed, possibly no 640 ms real-time cycle (nominally at 400 ms) at all, clock output signals are generated, the signal is on and the CP-D command for the RT-R signal, conductor CKC joins a DC signal. 55 before the end of the entire period of 640 ms (nomi-

3. A program test for normal feed at 500 ms).

status of the call processing is carried out when the CPD command for the i? T-i? signal

to (a) ensure that the call is processed before 320 ms or after

If a continuous performance of 640 ms does not occur, the real-time test is considered negative

limited number of functions under exclusion 60. The LTC conductor is then excited,

the many other program functions, which in turn led to the emergency action sequencer

which energizes a 5702 to perform all normal tasks and sets the LTO flip-flop

Telephone exchange are required, and during the cycle of 640 ms, the

(b) the real passage of time caused by the call processing, if it is normal,

Status of the real-time binary counter in the real-time tester 65 on the basic level L according to a frequency

5703 is displayed to list with the passage of time. Each lower level of the elementary level is one

same as that when executing the program register location within the conversation memory 103

commands are displayed which are assigned to the call, which is set to the »!« state,

35 36

after the lower-level work monitoring pirate information in the insertion register that this lower-level has been visited for the program and all work, the insertion, is necessary, for example, this lower-level has been carried out. That means, the wise in the case of the insertion for the CPD-Kom-Grundstuf e L has five sub-levels. L _a to L _e . on, the command for generating the ÄT-S signal is the information, and each of these sub-stages is: a register cell 5 mationy assigned to the execution of this particular 10 $ in the call log. The Korn CPD command is required.
mandos the central pulse distributor ,, the Erzeu- for addition to the input of the push-in requirements of the signals transition on conductors RTS and RT-R and push-in details in the a shift register are ,, be with the help of "interpolations" the emergency control program serves also carried out, which in .die basic level with the help of an io to enter a binary counter in the conversation memory 103 emergency measures control program. That is, within the conversation that is set at the interrupt level e H in. Action memory 103 there are six memory cells. those of the program! treated as a binary counter

The basic execution program is to be used and repeated once approximately every 10 ms. that it is the different. Elementary level 15 is switched. This counter can therefore accumulate up to 640 ms of work according to a roughly regulated schedule. After about 400 ms ,, displayed leads. The times at which the work is carried out by the state of the counter, the emergency mafi is added, the frequency control program explained above, the insertion for the keitstabeHe and the formation of the program? - CPD command for generating the iiT-S- Signals follow determined which each of the various work 20: a, and if this counter is subsequently applied at approximately 500 ms on the various sub-levels of the low level, the-Emergency-Measures-Pro Execute. The basic level execution program grabs the insertion for the CPD command, one after the other, through the various to generate; of the .RT-Ä signal.
The work of the sub-levels continues, and there is none. The CPD command, which is used to generate the possibility of a basic level work 25 AT-S signal, is carried out without any condition by another basic level work to be carried out. Break CPD command to generate the RT-R. The work of the basic level is regularly signaled, however, depends on the state of the cells "interrupted" by interruptions in the levels ίί of the sub-level work order register. Es and J, for the execution of input-output- there are five register cells, which are used individually functions which are assigned to the collection of new 3 ° of each lower level of the basic level. Call information and the transmission of these cells are in the "1" state according to call information are assigned. The work functions assigned to the interruption stages H and / or executed on completion of all their lower stages are set, and since the frequency work can be a relatively large number of table is designed so that they require about once from machine cycles. It is therefore advisable to repeat it every second, should also excite the cell assigned to the subordinate sequence 4901 to stage L _e about once per second and set the "1" state to carry out the jump. The time table frequently required by the interruption program is designed in such a way that the cells assigned to the subordinate and subsequently to the interrupted stages L _ar L _b and L _c more frequently return to the program. The tasks that are set by an insert 40 as once every 500 ms, during the exercise, must be carried out with a knowledge of time accuracy, cells assigned to the sub-stages L _d and L _e. set more than once per 10000 ms. However, each of these jobs only requires a small number of machine cycles. supply of the signal on the RT-R conductor depends on the Therefore it is not appropriate. this work depends on the 45 state of these five cells. Since to execute the maximum of an interrupt stage for which the interval of the long-term test of 640 ms is not necessary to the interval of about 1 second of the frequency table of the interrupt sequencer 4901. With the help of insertions can correspond to the sub-stages d and e can therefore perform a relatively short work of internal memory cells assigned to one another within a prescribed period of time during insertions to generate the T-signal without a Program interruption may or may not be set. However, since the sub is required. The insertion of the inserts L _d and L _e more than once in 1000 ms in the basic level is nor one of the many tasks, it is ensured that the cells assigned to these sub-levels are each selected at least once in the interruption level H. It is therefore a sub-interval of two consecutive long-term test interruptions at level H at which a general-purpose sub-interval is set. Accordingly, when breaking; it is not only used for the insertion of every insertion for the execution of a CPD-Kom insertion. mandos and generating a signal on the conductor

When performing the basic-level execution RT-R, the state of the five of the five sub-levels

program and the basic level work over- ⁶ ° assigned memory cells in five auxiliary cells.

monitoring programs is stored in an insert register for the next, similar

Changer 103 checked from time to time to be used interpolation and the five

determine whether an insertion request before the sub-levels are allocated to all cells

is dealt or not. The insertion of the insert postponed. With every such insertion must

Exercise by the emergency measures control program 65 the logical AND operation of the states of the

During the interrupt stage H, the marches comprise sub-stages L _B , L ₁ , L _c assigned cells and

marking of a work activity flag in the insert of its assigned auxiliary cells together with the

register in the conversation memory and the input of the logical OR link of the L _d and L _{e trains}

37 38

arranged cells and their associated auxiliary cells represents the major system disturbance that led to it

will result in a 5-bit word in which all bits "one" has that the system is unable to do that. This logical combination of information normal conversation processing with the moment ensures that the compilation of subgroups of the ordered work assigned to _{the sub-levels L 0} to L _{c is carried out in each of two successive systems.}

The emergency action sequencer 5702 follows that the one of a prescribed series of emergency actions associated with the substages L _d and L _e.

Work at least once for consecutive The first emergency measure is limited to that

Insertions has been completed. Reason of the system with the one active at the moment

The flip-flops SETO, CE and LTO register io composition to check. Subsequent emergency

the occurrence of the difficulties explained above, however, cause rearrangements of the measures

in the central control that responds to these difficult-active compilations from the central

keiten. That is, when the time of a controller 101, the program memory 102 and input

Sequential circuit runs, the flip-flop SETO in the input and output transmission busses.

central control is set to this 15 After each emergency measure, a number of

Difficulty encounters when the clock test 5103 exams, which are identical to those in the first

Faults in the microsecond clock source 6100 Excitation of the emergency measures follow-up circuit 5702

detects the flip-flop CE is set and the tests carried out are carried out in order to

if the real-time validator 5703 fails , determine whether the new active composition

the flip-flop LTO is set. 20 of components the normal call processing

The states of these flip-flops within one may or may not perform. If these central control checks can show through this central control that the central data processor 100 is interrogated by the control that the normal call processing cannot carry out memory at the location of the auxiliary buffer register 18, additional changes are made to the read-together. In addition, these flip-flops can be set up. However, if the central data processor 100 is apparently queried by network commands from the central data processor 100, which can carry out call processing at the main scanner stations, the information is addressed that is sent to these flip-flops via the mation with reference to the operation of the emergency measure cables 5217 connected scanning point connections - Sequence circuit 5702 saved and then correspond to. The scanner access to these flip-flops 30 the call processing decreased,
is the possibility that the active central control Tests conducted at each excitation of Notdie states of these flip-flops in the reserve measures tracker of 5702 who performed central control can query. den, can be divided into four basic sections for explanation

The different system states that are divided into:

Activation of the emergency action follow-up circuit 5702 35
conduct during normal conversation processing,

have hereby been summarized. From this 1 · serviceability program
As an explanation, it can be seen that each of these conditions represents a serious malfunction which The operability program includes a number of program tests, each of which is detrimental to the "operability" of the system. can influence. The term less than 128 machine cycles to complete "operability" as used here refers to the capability of the center. At the beginning of each test, the operating system of the data processor 100 will recover the program instructions from the clock circuit which is to process and such instructions from the per millisecond clock circuit 6101 , back to the program memory 102 . The expression 45 is provided, and if the test is not restricted within the "operability", basic period of 128 machine cycles, the condition that the active compilation from the central operability clock circuit has ended, the control 101, the program memory 102 and the conductor 61 704 μβεσ excited. This brings about a further connecting transmission path, the correct excitation of the emergency measures sequential circuit 5702 processing of special sequences of program commands 50. The millisecond clock circuit 6101 has words and the right to obtain such consequences a plurality of binary counting stages on which the words from the program memory 102 enables odd and even 5-ms output signals, the light, the normal call processing and 704 ^ sec Signal and other discrete output normal maintenance functions require a degree of signals to be delivered and which is above the buffer collection of "operability", which can be monitored via the "underground line system" in order to ensure operability. This means that in order for the operation of the millisecond clock circuit 6101 to test all necessary telephone and alarm signals to the system.

The central serviceability program contains consequences

Data processor 100 not only needs to be able to interpret command words calculated so that the

a prescribed special "basic operational capability" of the central data processor 100 for

keits «program, but also in the processing of data and for the acquisition of

must be able to retrieve all of the various sequences from program words from the program memory 102

which will be checked during the conversation and will be checked. The special program requires the

used in normal preventive maintenance execution of various types of commands

will. ⁶ 5 finally of jump instructions, and after that

There is a very high probability that the special program will be carried out successfully

one of the statuses of the system, which the emergency a jump to a program, which the operational capability

Sequential action circuit excited, the central impulse distributor checks a problem.

39 40

2 CFZ) test program ^monitored · ^The 40 ms clock circuit is closed

'' excited at the point in time at which the serviceability

This program is provided in order to initiate the capability program, and is only put back to the central controller 101 for transmission to the after the emergency measures evaluation has led various units of the central pulse distribution program to a decision that Iersl43 should be checked and the The ability of the central is the operability of the system apparently pre-pulse distributor 143 to execute commands and that a return to normal dos and return of assembly test request call processing can be made to central controller 101. If that decision is not within the

'_, .... , ... ίο valls of 40 ms occurs, a subsequent

3. Taken the following emergency measure and the above

If the central data processor 100 appears to have carried out a series of tests again,
nend is able to send commands to the central ^ _T _ '· - ,,, _N

To execute the impulse distributor, an emergency measures follow-up circuit test (5702)

carried out whether the central control with the 15 There are the system tests that lead to the excitation of the units of the call storage system 103 in connection emergency measures sequential circuit 5702 , and the connection can be established. If, in addition, the emergency measure basic tests, which are undertaken to evaluate the effectiveness of a reorganization of the program memories of such measures, have included, these will be written apart from the programs. Now the emergency measures memories 0 and 1 existing program memory 20 sequential circuit itself and its influence on the construction are individually inserted into the system in order to explain the components of the system,
Configuration of the central data processor completed The emergency measures sequential circuit 5702 contains

to deliver. functionally a large number of flip-flops, which are

. _XT , "■. ,. moderately at location 14 (Fig. 42) of the buffer collection

4. emergency evaluation program _{2g le} itungssystems are arranged. This arrangement

Among other things, this program is used to deviate from the arrangement of the components of the others

setting of the frequency used, with the emergency measure sequential circuits and enables in advantageous

men occur. The execution of emergency ways to gain access to these flip-flops for that

takes a relatively long period of time. Reading and writing with the help of the buffer

Therefore, set rapidly recurring episodes of 30 manifold systems.

Emergency Action The emergency action sequencer 5702 must reduce the data processing capacity of the system. There is the possibility that one of their work functions, even without operational disturbance, leads to the excitation of the emergency measures- consequence-pulse sources, ie an operational microcircuit 5702 and after one or more seconds-clock source 6100 and millisecond-clock successive emergency measures found 35 source 6101 within their central control turns out that the central data processor can conduct the normal. The emergency response follow-up circuit can carry out call processing. Subsequently, 5702 contains a monostable circuit, the output of which is excited after a relatively short time signal successively on the outputs P1, P 2, a further disturbance spans the emergency measures and P 3 of the follow-up circuit with the help of the tapped follow-up circuit. Repeated excitations of emergency 40 th delay lines within the follow-up sequencer 5702 within proportionate circuit are given 5,702th If the emergency short periods of time need to be investigated, Taken Sequencer 5702 is energized, the will appear to remedy the cause. first of a series of Vs ^ sec pulses on the conductor

If the emergency measures evaluation program Pl during a period of time, which is determined here as time Pl, that the in sections 1 to 3 is designated by 45. A second! ^^ sec-impulse appears. Guided examinations are over, an emergency- on the conductor P 2 4 nsec later during a time measure register, which an input of the conversation segment, which is referred to here as time P 2. Includes memory 103, up to date overall A third V2 nsec pulse appears to save later during a completed emergency measure on the introduced, μεεσ to provide information with respect to the straight conductor P 3 again. 4 The emergency 50 time period, referred to as time P 3, contains a short-term entry, in This sequence of pulses is used to determine the number of repeated emergency measures, the work functions of the emergency measures follow-up were required to the reason of the System tion 5702 to be carried out.

The four flip-flops that set the three-cell binary counter time input, which specifies the point in time at which the 55 4206 and the overflow cell 4211 are formed, are an emergency measure has occurred here. There is therefore the emergency measures status counter called 4206, 4211. Determine possibility in the following manner, which of the state counter is have been switched during normal GeEinheiten and the time sprächsbearbeitung reset to zero and span between successive excitations at each successive excitation of the Notder emergency bus sequencer 5702 to loading 60 measures sequencer 5702 switched on, agree. The state counter keeps a record for

As indicated above, each section or number of consecutive excitations is the

each program test of the operability-pro-emergency measures sequence circuit 5702 on and will

gramms used by the serviceability clock circuit to define the specific functions

monitored in the millisecond clock circuit 6101. 65 the sequential circuit for repeated excitations

In addition, all of the above steps 1 to 4 must be carried out.

finally the emergency measures evaluation pro- The four cells EACQ to EAC 3 are here

gramms called by the 40 ms emergency measures clock switch emergency measures control flip-flops 4208 and

used as follows. The first control flip-flop EACO is always brought into the "1" state when a state within the central control indicates that the emergency measures follow-up circuit 5702 should be energized. The "!" Output conductor of the control flip-flop EACO represents an input for the command combination gate circuit 3901 , in which this information is combined with status information from the central controller to generate a direct current signal on the command cable conductor EA GO to the sequence circuit 5702 to excite. It should be noted that the emergency action sequence circuit 5702 is only excited in the active central controller and that the output signals P1 to P 3 of this sequence circuit perform special gate functions both in the active and in the reserve central controller. In summary, the flip-flop EACO is set when a fault indication indicates that the sequential circuit 5702 is to be energized, and is reset after the sequential emergency action circuit has completed its sequence of functions.

The control flip-flop EACl initiates the time cycle of the 40 ms emergency measures clock circuit within the real-time tester 5703 when it is set to its “1” state. If the flip-flop EACl is not set, the odd and even 5 ms pulses reset the 40 ms clock circuit continuously. When the emergency action sequencer 5702 is energized, the flip-flop EACl is set and these pulses are cut off. As a result, if this clock circuit is not reset before its period expires, this clock circuit will expire. The control flip-flop EAC2 performs a similar function for the 128 cycle (704 ^ sec) health clock circuit. That is, when the flip-flop EAC 2 is set, the operational clocking is initiated.

The control flip-flop EAC 3 is set whenever the emergency action sequence circuit 5702 is energized by the real-time tester 5703.

Each excitation of the emergency measures follow-up circuit 5702 generates the output pulses specified above on the conductors P1, P 2 and P 3. These pulses are combined in the command combination gate circuit 3901 with output signals from the emergency measures status counter 4206, 4211 to carry out the desired gate functions. Since the emergency-follower circuit 5702 energizes only in the active central controller 101 and as many gate functions are to be performed in both units of the central controller 101 of the-emergency sequence circuit 5702 signals produced crosswise of the first central controller to the second central control and vice versa connected.

The emergency measures status counter 4206, 4211 is reset to "0" during normal call processing and is switched on if the emergency measures sequence circuit 5702 is first energized and if it is repeatedly energized due to failures in the various sanity tests. The states of the counter 4206, 4211 , together with the state information of the central data processor, define the specific remedial measures that are ordered. Accordingly, the state counters 4206, 4211 in the duplicated central controls must be kept in lock step so that the control of compositional changes proceeds according to an ordered pattern.

The emergency measures follow-up circuit 5702 generates, according to the statuses of the status counter flip-flops 5C0 to SC 3 and according to the statuses of the status flip-flops PBA, PBT, AV and TCC, optionally signals on the command cable tables EACCI, EACSI, EABOI, EABlI, EASI , EASTI, EARI and EACEI. The letter / on these command wire lines indicates that the signals are generated by the emergency response sequencer 5702 within the central control unit that contains these wires. Signals on these conductors are transmitted from one central controller to the other central controller via cable drivers 2701 and cable 2706 . The cable 2706 of the one central controller is connected to the cable 2208 of the second central controller. As a result, the above signals are transmitted on the EACCE, EACEE, EACSE , etc. conductors via the cable receivers 2205. The letter E indicates that the signals appearing on these conductors of the emergency bus sequencer 5702 due to the excitation of the emergency bus sequencer 5702 have been generated in the other central control. A similar connection for the signals of the emergency action sequence circuit from the second central controller to the first central controller completes the necessary cross-connection. The corresponding internally and externally generated sequential circuit signals are combined in OR gates within the command combination gate circuit 3901 of each central controller in order to perform the required gate functions in one of the two central controllers due to the excitation of the emergency measures sequential circuit 5702.

A number of functions are performed each time the emergency action sequencer 5702 is energized regardless of the state of the emergency action state counters 4206, 4211 and the states of the state flip-flops PBA, PBT and TCC . These functions are achieved by signals on the command wire lines EAS and EAST .

A signal on the command cable conductor EAS (the logical OR operation of the internal conductor EASI and the external conductor EASE) at time P1 causes:

1. The setting of the level β interrupt source flip-flop EASI by a signal on a command wire conductor of cable 5205.

2. Provision of the millisecond clock source 6101 by a signal on the command cable conductor EAS, which is transmitted via the OR gate 6104 to the reset input of the millisecond clock circuit 6,101th

3. Setting the flip-flop EACl and thus starting the 40 ms emergency measures clock circuit within the real-time tester 5703 by blocking signals on the command cable ladders HS and JS.

4. Setting the flip-flop EAC 2 and thus starting the 128-cycle (704 ^ sec) operational capability clock circuit.

5. Resetting the flip-flop PCTO in the comparison control register 4103. This means that every pro-

program-controlled Auszähl count locked, the excitement of the emergency measures sequencer 5702 may have been in progress, so that a faulty excitation of the emergency measures sequencer 5702 on the Auszähl this way - preventing comparator 4108th

6. Resetting the counter 4109 to zero to initiate the operation of the count compare circuit 4108 . Consequently, in the event that one of the sequential circuits checked by the counting counter 4109 has got stuck, the counting counter 4109 is incremented to its final value in order to energize the emergency measures sequential circuit 5702 again. Accordingly, there is a change in the active units of the controlling central data processor, and the central control with the stuck sequential circuit is finally removed from the active combination of components ao.

7. Set the separation flip-flop DI to block the cross-connection for error signals between the central controllers. If a central control unit encounters difficulties in the transmission to the program memory 102, the conversation memory 103 or in the execution of command commands, such difficulties reduce the data processing capacity of the other combinations of components. In such cases it is desirable to limit these difficulties to a combination of units so that the other (if it does not have these difficulties) can be switched into or admitted to the controlling central data processor.

A signal on either the internal EASTI conductor or the external EASTE conductor energizes the EAST command wire conductor. Then the following processes take place:

1. Provide a signal on the START command wire to bring or leave the stop sequencer 4400 in its active state. This ensures that the active central control, which is currently in the controlling central data processor or has just been introduced into this by a gate function of the emergency measures sequential circuit, is not in the stop state and consequently can obtain and execute sequences of program commands.

2. Resetting the flip-flops EACh and EACO in order to bring the emergency action sequence circuit 5702 into its inactive state or to leave it in this state.

3. Continuation of the emergency measures - status counter 4206, 4211 to prepare for the next function in the sequence of emergency measures, if necessary.

In addition to the emergency measures that are carried out with each successive excitation of the emergency measures follow-up circuit 5702 , emergency measures, which are discretely assigned to individual states of the emergency measures state counter 4206, 4211 , are carried out with successive energizations of the follow-up circuit 5702. As indicated above, some of these emergency measures result in changes to the active combinations of a central controller, a program memory and connecting busbar systems. After every change in the composition, an interrupt is generated at level B , during which the interrupt program determines whether or not the "basic operability" has been achieved with this new composition of active units.

When a displayed fault occurs that leads to the first activation of the emergency action sequence circuit 5702, the active combination of components does not represent a fixed arrangement, but rather it can be any of the possible combinations of components, since the current, active combination is either determined by previous program- Rearrangements or previous emergency measures have been established.

Before proceeding to an explanation of the specific measures that are carried out to implement compositional changes, a review of the rules for combining the various units is intended to provide a basis for understanding the changes brought about by the emergency measures sequence circuit 5702. As already stated earlier, there are two central control units which form the central controller 101. At any given point in time, one of these is designated as the active central controller and the other as the reserve central controller. The status flip-flop AU is set in the active central control, while it is reset in the reserve central control.

The program memory address bus system 6400 has an "O" bus and a "!" Bus, and the program memory response bus system 6500 also includes a "0" and a "!" Bus. The active central control may transmit manifolds addresses for connection with the program storing information on either or both manifolds receive and answer information on any of the two.

Although the program storage system 102 may have any number of storage units between 2 and 6, the program information required to check the basic operability of the system after an emergency response composition change is duplicated in only two units of the storage system, namely in storage 0 and 1 This information can be found in the right half (G block) of memory 0 and in the left half (ii block) of memory 1. In the course of emergency measures and composition changes, all memories except for memory 0 and memory 1 are listed as » other "memories are treated because the information they contain is irrelevant until the" basic operability "is regained.

The emergency measures status counter 4206, 4211 is in the zero state (0000) during normal call processing and during normal maintenance sequences that are not assigned to the emergency measures sequential circuit 5702 , and only after a fault display, which is used to excite the emergency measure.

took sequential circuit 5702 leads, the state counter is incremented to other states. As noted above, the first time the emergency response sequencer 5702 is energized, its functions are limited to a normal series of tests. If, with the help of these tests, it has been established that the "basic operability" is not available, remedial emergency measures are ordered. The emergency measures status counter 4206, 4211 is incremented to its first active state (0001) in preparation for the possible occurrence of subsequent emergency measures. With each subsequent energization of the emergency action sequencer 5702, the same basic check routines are executed, and if the remedial actions commanded by the emergency action status counters 4206, 4211 are ineffective, further emergency action is required. When the remedial measures are in effect, as indicated by the correct execution of the test programs, the state counter 4206, 4211 is held in the last active state for a brief trial period. During this period of time, the operation of the system is monitored with the aid of the various test measures described above, and if a serious problem occurs again which leads to the activation of the emergency measures sequencer 5702 , the emergency measures consist of those which are determined by the current state of the condition counter To be defined. After the trial period has elapsed, the status counter 4206, 4211 is reset to zero under program control. The trial period and the resetting of the status counter 4206, 4211 are under the control of the emergency response control program stored in program memory.

A four-level binary counter can define sixteen active states. For the sake of simplicity, these states are divided into a first group of eight states and a second group of seven states, the 16th state 0000 being the inactive state. In previous explanations it has been indicated that components such as the program memory 102 and the central controller 101 can be put into a faulty state when a fault is indicated with respect to these units. For example, the program memory 102 contains the fault flip-flops TBLO and TBL1, which can optionally be set by commands from the central pulse distributor. In a similar way, the set status flip-flop TCC indicates that the standby central control is disturbed.

The successive emergency measures cause changes in the composition of the active combination of the central controller 101, the program memory 102 and their connecting busbar systems in order to check the usefulness of all possible combinations of units. Among the emergency measures that are carried out when each subsequent emergency measure occurs beyond the first is a "clearing stop" which is carried out in both central controls. A clearing stop is initiated by a signal either on the internal EACSI conductor or on the external EACSE conductor. This causes the stop sequencer 4400 to be energized by a signal on the HALT command line conductor. The energized stop sequencer 4400 provides the command word register 3403 and the command word buffer register 2410 ;;. 0 (back and also returns all subsequent circuits '' which, as described above, through the training |.! Monitored zählzähler 4109 and Auszähl comparing circuit] 4108 Upon completion of the emergency ■ measures for the current state is the central Control by the emergency measures follow-up circuit 5702 with a signal on the conductor ^! START, which is used to switch off the stop follow-up circuit

circuit 4400 is used, started again. j

With each subsequent excitation of the emergency measures follow -up circuit 5702 , the 704 ^ sec emergency measures clock circuit in the millisecond clock circuit 6101 is reset by a signal on the conductor j EAS , and the 40 ms emergency measures! Clock circuitry in real time checker 5703 is reset in a similar manner.

The following explanation relates to the measures that are required to carry out changes to the composition taken without details with j

Regarding the examination of the new composition, ι At the time of the first excitation of the emergency measure [

took sequential circuit 5702 can be any

A combination of the central controller 101, the program memory 102 and the connecting busbar system may be present. Accordingly> turn some of Notmaß- j described below took only active central controls and: to be considered program memory without order, j which program memory or providing central control j is made active. However, other measures j <determine specifically that the manifold "0"'■ or the bus "1" of address and answer manifold system, the active component are. ;

The emergency measures carried out according to the states of the state counter 4206, 4211 '. are listed below according to these states:

0000 This condition is the initial condition, and the emergency measures are as described above, limited to examining the active compilation and when this exam If the result is negative, to switch the status selector further.

0001 This state is the first active state, and the emergency measure is limited to switching the currently active central control to the reserve state and the reserve central control to the active state. This is achieved by resetting the flip-flop AU in the currently active central control, and by setting the flip-flop AU in the reserve central control. The emergency action sequence circuit 5702 is only excited in the active central control. In the active central control, the conductor EACC-I is energized to reset the flip-flop AU , and via a cross connection with the help of the

Conductor EACC-E , the flip-flop AU is set in the reserve central control. 0010 The emergency measures in this state swap the roles of the active and reserve buses of both the program memory - address - bus system 6400 and the response bus system 6500.

In this state, the manifold "0" of both manifold systems is put into the active state or kept in this state, and the above in FIG. 86 memory operation 1 shown is performed. That is, the two basic program memories, program memory 0 and program memory 1, receive signals via the emergency action cable 6900 in order to achieve the arrangement shown. Consequently, the memory 0, in the half G of which the sanity check programs are arranged, receives a signal which sets the flip-flop BLI to operate this memory with bus "1" of both the address bus system and the response bus system exclude, while the program memory 1 receives the signal for setting the flip-flop TBLO in order to exclude reactions to commands via the bus "0" of the address bus system. After the counter 4206, 4211 has reached this state, the emergency measures have defined the special program memory that is active and the bus lines of the bus system that are active. The choice of the central controller, however, depends on the state of the system before the emergency action sequence circuit 5702 was energized for the first time.

The emergency measures in this state bring the program memory into the position shown in FIG. 86 shown Mode of operation 2 and make the bus "1" of both the address bus system as well as the response bus system to the active transmission paths.

The emergency measures of this state have the effect that the program memories in FIG. 86 assume the combination of mode of operation 1 shown. As a result, the program memory 1 becomes the active memory, since in this configuration both it and the central controller 101 are connected to the active buses, ie to bus "1" of both the address bus system and the response bus system.
The emergency measures in this state cause bus "0" to become the active bus and switch the program memory from mode 1 to mode 2. As a result, the program memory 1 remains the active program memory.

When the states 0001 and 0010 of the counter are executed, the states of the fault flip-flops TCC and PBT are observed. The set flip-flop TCC indicates that the central control in which it is located has been recognized as malfunctioning, and the set flip-flop PjBT indicates that the bus system, which is currently not in use, is malfunctioning. Consequently, when the emergency action sequence circuit 5702 is subsequently excited, those actions of the states 0001 and 0010 that want to switch those units that have been recognized as faulty to the active state are blocked. Accordingly, although certain compositions are commanded for states 0001 and 0010, the presence of disturbances as noted above precludes making changes to those prescribed compositions.

Olli These states are reserve states and no changes are made to the composition. The following states, beginning with state 1001, cause composition changes without regard to the states of the fault flip-flops TCC and PBT, as explained below.

The emergency measures in this state switch the active central controls. Consequently the combination shown in Fig. '86 for state 0110 is changed by that the central controls are swapped. ,

The emergency measures in this state switch the reserve collecting lines to the active one Compilation a.

The emergency measures in this state mean that bus "0" becomes the active one The collecting line remains empty, and bring the program memory to operating mode 1, as shown in FIG. 86.

1100, The emergency response to these conditions will change

1101, the composition based on the arrangements shown in FIG. 86. The Hope assumed that when forwarding the emergency measures sequential circuit 5702 the operability of the system is achieved through their active states and the system is returned to its normal conversation handling. However, in the event that the operability of the System is not achieved, the emergency action status counter 4206, 4211 in the State 1111 advanced, requesting maintenance personnel intervention. However, such a case is very unlikely because preventive maintenance sequences are continuous be done with a view to keeping all elements of the system in working order. if not a complete failure of the system occurs, the emergency measures follow-up circuit 5702 restore the operability of the system and, consequently, the system to normal Bring back conversation processing.

There is the possibility that difficulties in the central data processor 100 which lead to a sequence of emergency measures will impede the advancement of the emergency measures status counter 4206, 4211. Accordingly, an additional device for synchronizing the status counter 4206, 4211 is provided. Real time verifier 5703 produces an output on the LTC conductor and this signal energizes emergency action sequencer 5702 as noted above and also causes a signal to appear on command wire SC-R which resets the three cells 4206 of counter 4206 . This signal is also transmitted on the EARI conductor to the other central control

109 516/268

transfer unit. The signal appears in the other central control on the conductor EARE, which resets the three cells of the counter 4206 in this central control. Consequently, the occurrence of a "long-term" test period is indicated by a signal on the LTC conductor, which causes the status counter to be incremented to the status 0000 or 1000 according to the status of the flip-flop 4211 at the time of this emergency measure.

IO

Claims (6)

Patent claims: 1. Data processing system with a large number of memories and a control arrangement with two functionally equivalent control units, each of which has a clock, as well as with a transmission arrangement connecting the control arrangement to the memories for optional use Interconnection of the storage and control units to form several operating combinations, each of which contains one of the control units and at least one of the memories, with an input-output arrangement connected to the control units and with blocking circuits, the transmission of command signals from a selected control unit for Block input-output arrangement, characterized by the following features: a) the data processing system has a time recording device (FIG. 57: part of 5703) which responds to output signals from the clock generator (FIG. 61: 6101) and records the time determined by the occurrence of output signals from the clock generator, and a Recording device (a plurality of locations in memory 103) responsive to the execution of particular series of programs and keeping a record of the work performed in executing the respective series of programs; 45 b) there is a circuit arrangement (143) for Generation of control signals during the execution of the program sequences and a further circuit arrangement (Fig. 57: a further part of 5703) which checks whether the control signals occur within predetermined time limits specified by the time recording device and which generates an error signal if the control signals do not occur within the specified time limits; c) a sequential circuit arrangement (5702, 4206, 4208) is connected to the further circuit arrangement which responds to the error signal and generates a combination of emergency measures control signals; d) an emergency measures control circuit ( Fig. 7: 501, 503; Fig. 22: 2205, 2208; Fig. 28: 2812, 6900; Fig. 55: PBA, PBO, AU) is coupled to the sequential circuit arrangement, which is based on the Responds to emergency measures control signals and the control units (CCl, CC 2) and rearranges the independent memories into new operating combinations, one of which comes into contact with the input-output arrangement and each other is inactive, the sequential circuit arrangement being designed so that it is independent of the output signals of the clock generators (6100,6101 ) and independently of the program generates the emergency measures control signals required to achieve the rearrangement initiated by the error signal. 2. Data processing system according to claim 1, characterized in that the sequential circuit arrangement (5702, 4206, 4208) is designed so that it triggers the execution of a basic test sequence after the formation of a new operating combination, which checks all functions of the new operating combination, that a time test circuit ( 57: 5703; Fig. 61: 6101) is provided, which checks whether the execution of the basic test sequence has been completed within a prescribed period of time and generates an error signal (61-704) if the prescribed period of time is exceeded, and that the control units if the basic test sequence is carried out, the time test circuit resets within the prescribed period of time. 3. Data processing system according to claim 2, characterized in that the time test circuit contains a digital counter (part of 6101) and an analog timer (part of 5703), both of which are reset when the basic test sequence is initiated in an initial state that the digital counter by output signals of the Clock is advanced and that the analog timer provides an output signal independently of the output signals of the clock for the prescribed period of time after its actuation. 4. Data processing system according to claim 2 or 3, characterized in that the sequential circuit arrangement (5702, 4206, 4208) generates additional groups of emergency control signals in the event of error signals due to the prescribed period of time being exceeded, through which another operating combination is interconnected, whereupon the Basic test sequence is triggered to determine the operability of the new operating combination. 5. Data processing system according to claim 4, characterized in that the sequential circuit arrangement has a recording device (F i g. 42: 4206, 4211) for registering successive excitations of the sequential circuit arrangement and that the sequential circuit arrangement is designed so that it groups of corresponding to the state of the recording device Emergency action control signals generated. 6. Data processing system according to one of the preceding claims, characterized in that each control unit contains further sequential circuits (4401, 4902, 4903, 4901, 5300, 5301, 5302, 5700, 5701) for performing repetitive control functions, that the further sequential circuits in the execution loading certain commands of the program are excited and a time-out counter (4109) is provided, which indicates faulty operation of the subsequent circuits and in the event of such a display Can generate error signal. For this purpose 27 sheets of drawings