GB1081811A - Data handling system - Google Patents

Data handling system

Info

Publication number
GB1081811A
GB1081811A GB41682/64A GB4168264A GB1081811A GB 1081811 A GB1081811 A GB 1081811A GB 41682/64 A GB41682/64 A GB 41682/64A GB 4168264 A GB4168264 A GB 4168264A GB 1081811 A GB1081811 A GB 1081811A
Authority
GB
United Kingdom
Prior art keywords
stores
program
processor
duplicate
buses
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB41682/64A
Inventor
Anton Henry Doblmaier
Randall William Downing
Michael Peter Fabisch
John Allen Harr
Harold Frederick May
John Stanley Nowak
Frank Finley Taylor
Werner Ulrich
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of GB1081811A publication Critical patent/GB1081811A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0751—Error or fault detection not based on redundancy
    • G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
    • G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1405—Saving, restoring, recovering or retrying at machine instruction level
    • G06F11/141—Saving, restoring, recovering or retrying at machine instruction level for bus or memory accesses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1633—Error detection by comparing the output of redundant processing systems using mutual exchange of the output between the redundant processing components
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
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    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G06F11/1645—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components and the comparison itself uses redundant hardware
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1654—Error detection by comparing the output of redundant processing systems where the output of only one of the redundant processing components can drive the attached hardware, e.g. memory or I/O
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1666—Error detection or correction of the data by redundancy in hardware where the redundant component is memory or memory area
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
    • G06F11/1687—Temporal synchronisation or re-synchronisation of redundant processing components at event level, e.g. by interrupt or result of polling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2023—Failover techniques
    • G06F11/2033—Failover techniques switching over of hardware resources
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
    • G06F11/2043—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant where the redundant components share a common memory address space
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
    • G06F9/3875—Pipelining a single stage, e.g. superpipelining
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
    • G06F9/4825—Interrupt from clock, e.g. time of day
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54541—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme using multi-processor systems
    • H04Q3/5455—Multi-processor, parallelism, distributed systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/42—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker
    • H04Q3/54—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised
    • H04Q3/545—Circuit arrangements for indirect selecting controlled by common circuits, e.g. register controller, marker in which the logic circuitry controlling the exchange is centralised using a stored programme
    • H04Q3/54575—Software application
    • H04Q3/54591—Supervision, e.g. fault localisation, traffic measurements, avoiding errors, failure recovery, monitoring, statistical analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2002—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant
    • G06F11/2007—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where interconnections or communication control functionality are redundant using redundant communication media
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Abstract

1,081,811. Automatic exchange systems. WESTERN ELECTRIC CO. Inc. Oct. 13, 1964 [Dec. 31, 1963], No. 41682/64. Heading H4K. [Also in Division G4] The central processor of the Bell System No. 1 Electronic Switching System has functionally equivalent first and second control circuits for writing in, obtaining information from and for executing sequences of program order words obtained from a number of independent memories; a number of independent trans. mission paths being provided for interconnecting the memories, controls, and the input-output apparatus governed by the processor; the controls, memories, and transmission paths being selectively associated to comprise two distinct or partially shared central processors capable of performing the same work functions concurrently but of which only one exercises active command. With the choice of associations available selectively to provide a processor it is possible to provide an active processor even though the system as a whole is subject to multiple fault. The possession of duplicate records in the separate processors allows normal working to be re-established in face of a fault. The control circuit of each processor assemblage can detect faulty responses in its own work functions and records trouble signals whenever its companion encounters a fault. All remedial action requires additional time in a work function, redundant codes needing time for correction and parity checks needing time for re-reading. Cross-couplings between the control circuits hold their clock circuits in phase and with the provision of matching circuits and maintenance decoders allows for the comparison of common points in both controls. A mode control register determines whether the controls pursue an " in-step " mode with one processor active and one at " stand-by while both execute the same function, or whether one processor pursues the functions active in governing the input-output apparatus while the other pursues a diagnostic exercise. The controls may follow a routine matching mode, with a matching capacity of two points in each machine cycle and governed by a matching cycle control, or they may follow one of a number of maintenance matching modes governed by a program sequence and a match control register instructed by the maintenance decoder. An emergency action sequencer or a program sequence executed in a central control switches from one processor to the other in the event that trouble is found to exist in the active control. An order, termed a WV order, is employed as a means of producing an interrupt in the standby control circuit so that it can be given specific tasks such as diagnostic tests. A stop sequencer circuit is employed to permit completion of the operational step of the program order word current in the order word register. The independent memories have operational checking circuits. Processes of error correction are counted so that periods of high error rate may be detected and dealt with. Transformer coupling between the various system units and transmission buses isolates the buses from faults in the units. In Figs. 3 to 6 is shown the total assemblage from which the processors are arranged. Central control circuits CC1 and CC2 are provided with independent program stores PS1 to PSN, which are permanent magnet wire stores providing non-destructive read-out, and independent call stores CS1 to CSN which are ferrite sheet memories. The program stores hold the permanent data while the call stores hold the transient data. Transmission buses 6400 and 6401, between the control circuits and the memories, are provided in duplicate. Duplicate buses 6400-0, 6400-1 transmit reading data to a program register selected from an address register. The duplicate buses 6401-0, 6401-1 transmit reading data to a selector call store. Buses 6500 and 6501, similarly in duplicate, transmit data invoked from the stores to the central controls CC1, CC2. A route register in each control circuit determines which, if any, of the duplicate sets of transmission paths shall be selectively associated, a bi-stable circuit AU determining which of the two central controls is active with actual command. The program and call stores receive selective read-out instructions and send data on buses selected according to the state of route registers such as 501, 601. Buses 6403 to 6406 transmit commands from the controls to the input-output equipment and a bus 6600 transmits input data to the controls. In each of the central controls there is an operational check circuit 460, a match circuit 360, and a trouble indicator TBL, which combine to govern a remedial action circuit 462. Information obtained from a call store is protected by parity bits while information from program stores is protected by both parity bits and Hamming codes. A program of high priority is called upon when a fault is detected so as to restore system abilities by any necessary switching and rearrangement of equipment, a lower priority program being commissioned to localize the fault and effect print-out of the details for maintenance personnel. Apart from routine checks on the information being processed the system also performs routine test programs of low execution priority which may be conducted on a scheduled basis or manually as required. Miscellaneous equipment.-Access to equipment required for instruction or inspection by the processor is provided by way of a high-speed translator termed a central pulse distributer. For security the distributer is duplicated. All enabling signals from the distributer require a verification signal sent back from the equipment enabled and are accompanied by a security signal which limits the time during which equipment is gated to an interconnecting bus in order to reduce the possibility of fault arising from noise on the bus. The distributer is called upon to exercise a direct command function where a high speed of supervision is needed, as with multi-frequency signal and digit senders over trunks, where local signal distributers are too slow. For the purpose of trouble diagnosis and maintenance a general picture of strategically chosen points is provided by a master scanner which is not in duplicate but comprises a number of individual scanners each of which may take charge of an associated scanner's function as well as its own in face of fault. Maintenance staff have the use of teletypewriter units to request limited system action and to update call stores with information relative to new lines, disconnections, and the like pending the corporation of such data in the program stores. The units print out instructions relating to trouble procedures. The teletypewriter units are each devoted to specialized functions and are not duplicated as they can be transferred readily from one function to another. Automatic message accounting is done in duplicate on tape units and a program card writer is provided for the preparation of program store cards. Direct control over the switching network requires controllers, scanners, and signal distributers associated with the network switching groups and each of these circuits is divided into independent halves which can each fulfil the functions of the whole if fault conditions so require. The type of network.-The two-wire paths set up over the system involving the connections of lines to lines via junctors, lines to trunks and trunks to trunks, and lines and trunks to tones, signal transmitters and receivers &c., are established on command from the processor in accordance with its record of busy and idle states of all network links and paths. Direct control of the network is exercised by control and supervisory circuits comprising the controllers which set up connections and carry out tests, scanners to determine the states of selected circuit elements, and distributers to operate and release selected magnetically latching wire relays in the junctors, trunk, and service circuits. Subscribers circuits may have touch tone or dial pulse sets and the type of set in use will normally be recorded in the program stores subject to countermanding information in the call stores. Supervision is made by a network unit scanner only for service requests as, once a connection is set up, supervision is transferred to the junctor or service circuit involved in the connection. Program stores.-Each of these stores has a maximum of 16 modules with a capacity of 8,192 words of 44 bits giving a total capacity of 131,072 words at 65,536 addresses. At least two such stores must be employed but no more than six. Each store is divided into halves, referred to as the G and H halves, and the recorded data is duplicated by having the data in the G half of one store repeated in the H half of another store. With a 4 x 4 array of modules access is had to word pairs in each store by means of two 1 out of 256 codes produced by translation of processor codes. An additional bit is needed to identify the wanted one of the pair. The processor codes are gated to the program stores by the central pulse distributer and by a sync. signal accompanying the code. The program stores are addressed over duplicate buses of 25 wire pairs each and respond over duplicate buses of 46 pairs each. The central control circuits of the processor may stand in any one of four modes in relation to the program stores these being the normal mode in which information is sought from it address in both the H and G duplicate segments, a maintenance mode in which only the H or G segment is addressed, a read control mode in which an information store is interrogated at 176 test points, and a write control mode which allows the insertion of instructions in the address and routing registers of the stores. A routing register in each store determines the address bus, store, response bus configuration, to determine from and to which of the duplicate buses H or G is concerned. Call stores.-Each stor
GB41682/64A 1963-12-31 1964-10-13 Data handling system Expired GB1081811A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US33487563A 1963-12-31 1963-12-31

Publications (1)

Publication Number Publication Date
GB1081811A true GB1081811A (en) 1967-09-06

Family

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Family Applications (7)

Application Number Title Priority Date Filing Date
GB41684/64A Expired GB1081813A (en) 1963-12-31 1964-10-13 Data handling system
GB41686/64A Expired GB1081815A (en) 1963-12-31 1964-10-13 System for detecting changes in supervisory states of a communication system
GB41688/64A Expired GB1081817A (en) 1963-12-31 1964-10-13 Communication switching system
GB41683/64A Expired GB1081812A (en) 1963-12-31 1964-10-13 Data handling system
GB41682/64A Expired GB1081811A (en) 1963-12-31 1964-10-13 Data handling system
GB41685/64A Expired GB1081814A (en) 1963-12-31 1964-10-13 Data handling system
GB41687/64A Expired GB1081816A (en) 1963-12-31 1964-10-13 Data handling system

Family Applications Before (4)

Application Number Title Priority Date Filing Date
GB41684/64A Expired GB1081813A (en) 1963-12-31 1964-10-13 Data handling system
GB41686/64A Expired GB1081815A (en) 1963-12-31 1964-10-13 System for detecting changes in supervisory states of a communication system
GB41688/64A Expired GB1081817A (en) 1963-12-31 1964-10-13 Communication switching system
GB41683/64A Expired GB1081812A (en) 1963-12-31 1964-10-13 Data handling system

Family Applications After (2)

Application Number Title Priority Date Filing Date
GB41685/64A Expired GB1081814A (en) 1963-12-31 1964-10-13 Data handling system
GB41687/64A Expired GB1081816A (en) 1963-12-31 1964-10-13 Data handling system

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Country Link
US (1) US3570008A (en)
JP (1) JPS514062B1 (en)
AT (7) AT271951B (en)
BE (7) BE654497A (en)
BR (4) BR6463330D0 (en)
CH (7) CH479992A (en)
DE (6) DE1474095B1 (en)
DK (4) DK114415B (en)
FR (7) FR1426972A (en)
GB (7) GB1081813A (en)
IL (7) IL22240A (en)
NL (8) NL6415241A (en)
SE (4) SE319926B (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723975A (en) * 1971-06-28 1973-03-27 Ibm Overdue event detector
US3737870A (en) * 1972-04-24 1973-06-05 Ibm Status switching arrangement
US3892928A (en) * 1973-10-09 1975-07-01 Bell Telephone Labor Inc Switching system equipped with line verification apparatus
US4053751A (en) * 1976-04-28 1977-10-11 Bell Telephone Laboratories, Incorporated Adaptable exerciser for a memory system
US4048452A (en) * 1976-05-28 1977-09-13 Bell Telephone Laboratories, Incorporated Automatic call distribution system
DE2849371A1 (en) * 1978-11-14 1980-05-29 Siemens Ag METHOD FOR TRANSMITTING INFORMATION BETWEEN FACILITIES OF AN INDIRECTLY CONTROLLED SWITCHING SYSTEM, IN PARTICULAR TELEPHONE SWITCHING SYSTEM
US4345116A (en) * 1980-12-31 1982-08-17 Bell Telephone Laboratories, Incorporated Dynamic, non-hierarchical arrangement for routing traffic
JPS57182858A (en) * 1981-05-06 1982-11-10 Japan Electronic Control Syst Co Ltd Monitor circuit for program runaway in computer
US4484030A (en) * 1982-04-19 1984-11-20 At&T Bell Laboratories Method and apparatus for identifying faulty communications circuits
US4577066A (en) * 1983-08-03 1986-03-18 At&T Bell Laboratories Telephone interexchange call routing
US4565903A (en) * 1983-08-03 1986-01-21 At&T Bell Laboratories Telephone interexchange carrier selection
US4555594A (en) * 1983-08-03 1985-11-26 At&T Bell Laboratories Telephone interexchange signaling protocol
ATE57288T1 (en) * 1985-08-14 1990-10-15 Siemens Ag CIRCUIT ARRANGEMENT FOR TELECOMMUNICATION SYSTEMS, IN PARTICULAR TELEPHONE EXCHANGE SYSTEMS, WITH INFORMATION REQUEST DEVICES CYCLICLY CONTROLLING REQUEST POINTS.
EP0213374B1 (en) * 1985-08-14 1990-01-31 Siemens Aktiengesellschaft Circuit arrangement for telecommunication exchanges, particularly telephone exchanges, comprising scanning joints which are cyclically controlled by information interrogation devices
US4660220A (en) * 1986-02-25 1987-04-21 Kraus Constantine R No answer mode for telephone systems
US4763191A (en) * 1986-03-17 1988-08-09 American Telephone And Telegraph Company, At&T Bell Laboratories Dial-up telephone network equipment for requesting an identified selection
US5289542A (en) * 1991-03-04 1994-02-22 At&T Bell Laboratories Caller identification system with encryption
US5329581A (en) * 1991-12-23 1994-07-12 At&T Bell Laboratories Target area calling system
US5444774A (en) * 1992-06-26 1995-08-22 At&T Corp. Interactive queuing sytem for call centers
US5521965A (en) * 1992-08-14 1996-05-28 Bell Atlantic Network Services, Inc. Apparatus and method for handling busy calls in telephone network
US6618474B1 (en) 1999-03-08 2003-09-09 Morris Reese Method and apparatus for providing to a customer a promotional message between ringing signals or after a call waiting tone
US8489915B2 (en) * 2009-07-30 2013-07-16 Cleversafe, Inc. Method and apparatus for storage integrity processing based on error types in a dispersed storage network
CN111618854A (en) * 2020-05-26 2020-09-04 中国人民解放军国防科技大学 Task segmentation and collaboration method for security robot

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1024124B (en) * 1953-03-30 1958-02-13 Lionel Roy Frank Harris Method for selecting one of several lines in telecommunication systems, in particular in telephone systems that work according to the time division multiplex method
BE571788A (en) * 1957-10-07
BE625636A (en) * 1961-04-25

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DE1474093A1 (en) 1970-07-09
CH477140A (en) 1969-08-15
DK114415B (en) 1969-06-30
NL140351B (en) 1973-11-15
DE1437577B2 (en) 1971-11-25
CH479991A (en) 1969-10-15
NL145065B (en) 1975-02-17
US3570008A (en) 1971-03-09
BR6463328D0 (en) 1973-06-26
BR6463327D0 (en) 1973-06-26
DE1437576C3 (en) 1972-03-16
SE312940B (en) 1969-07-28
NL137733C (en)
BE654494A (en) 1965-04-16
DE1474093B2 (en) 1972-09-07
GB1081816A (en) 1967-09-06
IL22239A (en) 1968-04-25
BE654493A (en) 1965-04-16
GB1081815A (en) 1967-09-06
IL22241A (en) 1968-04-25
IL22243A (en) 1968-04-25
NL6415240A (en) 1965-07-02
DK136878C (en) 1978-05-16
BR6463330D0 (en) 1973-06-26
AT269518B (en) 1969-03-25
NL6415241A (en) 1965-07-02
AT274056B (en) 1969-09-10
IL22242A (en) 1968-04-25
NL6415238A (en) 1965-07-02
DE1474094B (en) 1971-04-15
AT271951B (en) 1969-06-25
SE319926B (en) 1970-01-26
CH479992A (en) 1969-10-15
BE654492A (en) 1965-04-16
NL6415235A (en) 1965-07-02
GB1081813A (en) 1967-09-06
GB1081812A (en) 1967-09-06
CH479990A (en) 1969-10-15
AT274057B (en) 1969-09-10
FR1426971A (en) 1966-02-04
GB1081814A (en) 1967-09-06
DE1474095B1 (en) 1970-08-20
FR1442332A (en) 1966-06-17
AT272712B (en) 1969-07-25
SE334392B (en) 1971-04-26
BE654496A (en) 1965-04-16
NL6415236A (en) 1965-07-02
FR1426973A (en) 1966-02-04
AT273543B (en) 1969-08-11
DK115124B (en) 1969-09-08
FR1426972A (en) 1966-02-04
SE326990B (en) 1970-08-10
FR1446309A (en) 1966-07-22
FR1442298A (en) 1966-06-17
BE654497A (en) 1965-04-16
DE1437576B2 (en) 1971-08-12
GB1081817A (en) 1967-09-06
IL22240A (en) 1968-04-25
NL6415237A (en) 1965-07-02
DE1437576A1 (en) 1969-02-27
CH479993A (en) 1969-10-15
BR6463331D0 (en) 1973-06-26
DE1437577A1 (en) 1969-02-20
BE654495A (en) 1965-04-16
NL6415239A (en) 1965-07-02
CH476441A (en) 1969-07-31
JPS514062B1 (en) 1976-02-07
DE1474096A1 (en) 1970-07-09
IL22237A (en) 1968-04-25
BE657775A (en) 1965-04-16
AT271950B (en) 1969-06-25
FR1426970A (en) 1966-02-04
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CH476442A (en) 1969-07-31
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IL22238A (en) 1968-04-25
DK136878B (en) 1977-12-05

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