DE1474093B2 - Program-controlled data processing system - Google Patents

Description

The invention relates to a program-controlled data processing system with a large number of Store, a control arrangement with a first and second control that are functionally equivalent are, as well as a transmission arrangement connecting the memory to the control arrangement, with an input-output arrangement connected to the controls and responding to their commands and with circuits that control the transmission of commands from a selected controller to the Block input-output arrangement.

With the ever increasing complexity of data processing systems included of multi-purpose and special computing systems and the extraordinarily high operating costs of such Systems have grown the demands on reliability. Besides, it is increasing with the Occurrence of critical data processing operations, for example the control of critical industrial ones Operations such as the control of a production line, the control of a telephone exchange, and the control of critical scientific processes make the development extremely reliable Data processing systems have become imperative.

The advances in the speed of data processing circuits have led to an ever greater simultaneous use of data processing systems. This increases the demands on the reliability of such systems even further.
Data processing systems are used in many ways

3 4

Conditions used, which in principle on operating in the context of this solution is not possible. Reason for the input / output used in the system. In other data processing systems, a gangs devices and the respectively processed, specifically double data processors used by rush to distinguish data. The present which each display internal arrangements Invention does not depend on these distinctive 5 flaws. When an internal fault occurs away. Operation is mechanical or electrical

For explanation, however, a program switch from one data processor to the other is switched as an example. The difficulties in switching for an almost immediately responsive data processing from a normal to a reserve unit in solbeitungsanlage, because they are operating systems are based on the fact that the data naming requirements of the exchange processing capacity of the system during the subscriber and trunk lines must meet the delay interrupted without substantial switching in an intolerable manner. In addition, must be. In addition, recovery from such a switch that works to the satisfaction of the participants is often very difficult to achieve.
Telephone exchange system continuously in operation 15 To ensure uninterrupted existence. It is not possible to operate a remote operator, and all efforts must be made by the intercom exchange during the day or night in order to detect a possible malfunction, repairs or changes can be made early, and the recurrence of the line to be interrupted. Avoid telephony interference and, if a telephony malfunction has been identified, quickly identify the error in modern society, and serious people and fix it, so that the usability of emergencies, the use of a telephone make this facility safe in the event of a further malfunction, cannot be planned in this way.

that they only occur at times that are necessary for the The invention is based on the object of a

System or its monitoring staff to create inexpensive 25 data processing equipment that

are. It should be particularly emphasized that interrupted, functionally reliable operation is also possible with

enables the above-mentioned conditions for the operation to occur,

the system with reference to an almost instantaneous To solve this problem, the invention goes

speak and the demand for a permanent out of a data processing system of the initially

Operation not only for telephone exchange 30 mentioned type and is characterized in that

systems, but also for many other data- the transmission arrangement a variety of un-

processing facilities are important. has dependent transmission paths of which

In data processing systems, a number of methods each depending on the state of registers have been used to ensure accurate and selective switching with the first or second continuous data processing. 35 control and, depending on the state, known arrangements are, however, subject to further register circuits, each of which has severe individual restrictions. When storing memories are assigned, optionally with the Speistimmten arithmetic data processing systems is always connected, and that the so produced a group of work functions is repeated connections at least one operating combination and its results are compared. If the results do not match a controller, a transmission path, the working memory and at least one memory are included,
functions repeated once more. In this way, if an operational second and third result can match, the combination will be provided even if intermediate results are assumed to be correct. If several malfunctions have occurred in the system, but they do not match, operation is 45 unlike in pure parallel operation is stopped. Such an arrangement wastes a lot of time, so two systems can, for example, unacceptably reduce the data processing capacity, for example, control of one operating combination and the storage of a large telephone exchange system rather than the other operating combination. the remaining components to a new, undisturbed one

In the case of other data processing systems, 50 operating combinations will be put together,
three data processors are used, which are fed with the same input data at the same time. The net through circuits that are simultaneous. Output and output data of the three data processors are compared by the identical work functions, and if they ensure two or all three first and second controllers and match the following data processors, these 55 lowing components will contain: BeData is considered valid in each controller, and all three data drive checking circuits which process the operations of processors continue their work using parts of the control system and the correctness of the valid data as a new starting point. check the information read in the memory and this method is often referred to as "logical majority fault signals whenever a status arrangement" is referred to. The procedure, however, is 60 failure indication occurs; Circuits for overriding for other areas of application of data processing of disturbance signals to the respective other processing systems, for example a large telephone control and register circuits in each control switching system, not usable because not only for recording the disturbance signals transmitted from the other control an uneconomical use of equipment on the system and circuits are required due to the fact that three full 65 in each control, which are necessary on the basis of malfunctioning processing systems, carry out signals from both controllers, but also take identical control measures in the event of errors. .
one or more units a continuation of the In this way it is achieved that the control

5 6

In terms of the two operating systems that normally exist, the independent storage systems and the independent ones Combinations of identical work functions lead transmission paths to a new company combination. Accordingly, the two controls contain nation to be compiled. For example kaiin one same records, so that the co-data processors have an exceptionally high error circuit new, more capable company combination 5 when extracting information from the spinning nations is possible without a time delay. rather show, d. i.e. that if the data processor

There is the possibility of many types of errors, difficulties due to noise or other

to be determined during the operation of the data processor. whose balancing operations are exposed to

The data processor can take remedial measures to cause memory read errors, often still there

carry out to the effects of many ani- io possible the assigned work functions

to switch off the faults shown. Carry out all remedial measures. The speed at which this

however, require additional time to be performed via functions, but this may not be

which goes beyond what would normally be a definite reduction, since every error in the

assigned work function. If, for example, reading the memory requires reading again

way of displaying and correcting individual errors 15. Advantageously, there is also the

If a redundancy code is used, additional time occurrence of such high numbers of errors is the possibility

required to correct such errors the execution of program sequences to gain

perform. In a similar way, it is when a healthy operating combination of

use a parity check to protect against equipment.

Errors when reading a memory possible to arrange an ao In addition to the implementation of operational readings of the memory in the detection tests both within the controls as a parity error. For the renewed reading of the memory, also within the memory, a further development provides, however, in addition to the invention, that the first and second control times are required. If a malfunction in a tion has a large number of data sources and an operating combination occurs, it is not certain that the circuits which ensure the simultaneous execution of corresponding errors or a corresponding generation of identical work functions also malfunctions in the other combination. Contain circuits, the data words from selected - accordingly, the exchange of fault data sources within the two controllers provides signals between the first and second controller, compare and generate fault signals if the recording of control signals of the respective 30 compared data words are not identical,
If the commands that form the programs are divided into auxiliary measures due to either a malfunction detected in the control of the data processing system in command control or a malfunction signal, it is appropriate to ensure that the two lines are provided that the data sources in dependent controls simultaneously perform identical work functions depending on the class of commands executed. choose.

An additional development of the invention provides this arrangement ensures that critical data

before that the memory audit circuits and in particular data that are for a particular

have the internal operation of the memory class of instructions are critical to be compared,

test and generate a test signal and to the 40 An embodiment of the

transfer those control that described the eye invention with reference to the drawings,

Imaginable operational combination with the memory It shows

1 a general block diagram of a simultaneous execution of identical work functions telephone switching system as execution, the test signals-responsive re-45 example of a data processing system,
have register circuits and circuits that F i g. 2 the arrangement of information in the memory of the exemplary embodiment depending on the state of the register circuit,
gen generate interference signals. FIGS. 3 to 6 in the arrangement according to FIG. 73

It is not likely that identical STOE _me hr detailed block diagram of a continuous, while simultaneously in the independent memories 5 ° embodiment of the invention,
occur that operate the two controls. F i g. 7 a general block diagram of a program memory, however, if such identical faults occur,

and identical faulty signals to the control units are transmitted, there is the possibility to save the call,

that such disturbances go undetected. This becomes 55 Fig. 9 is a general block diagram of a

through the audit circuits of the memory control unit,

prevented. In addition, if a fault affects the Fi g. 10 to 63 in the arrangement according to FIG. 71

Disclosure of the operating mode makes it necessary for a detailed circuit diagram of a control

the two controls work synchronously is a unit,

the presence of independent operating check 60 Figs. 64 to 66 in the arrangement of Fig. 72 circuits in the memories are advantageous in order to ensure a schematic representation of the main message error-free operation. Connection paths of the exemplary embodiment,

For a large number of operating states, FIG. 67 is a schematic representation of the implementation normal work functions impairment for optional comparison of disability. In these cases, the control arrangement generates 65 that are within the first and second tion occur in the execution of certain program sequences control unit,

a large number of control signals for the controllers F i g. 68 a timing diagram with the used

and the independent memories to store the controls, basic pulses,

69 shows a timing diagram for the processing of three successive program instruction words;

F i g. 70 a table with the optional, additional Command options and features for the commands used in the exemplary embodiment,

71 to 73 the compilation of figures for the parts of the exemplary embodiment indicated above.

The main components of a telephone switching system as an embodiment of a data processing system are shown in FIG. 1 shown.

In Fig. 1 contains the as the central data processor Block 100 denotes the control arrangement 101 and the memory system with the program memory 102 and the conversation memory 103. The remaining elements in Fig. 1 form the input-output system of the embodiment.

The operation of a data processing system is illustrated generally in FIGS. 3-6. These Figures are intended to illustrate certain details of the control arrangement 101, the storage system 171 and the Explain transmission system 105-106 in more detail.

The control arrangement 101 has a first controller CC1 and a functionally equivalent second controller CC2 .

The memory system 171 contains a multiplicity of independent memories, namely a multiplicity of independent program memories PS1 to PSN and a multiplicity of independent conversation memories CS1 to CSN.

The transmission system 105-106, which connects the controllers CC 1 and CC 2 and the storage system 171, has a plurality of independent transmission paths 6400-0, 6400-1, 6500-0, 6500-1.

Instructions for obtaining information from one of the program memories PS1 to PSN are transmitted by the controllers CCl-CC 2 via the transmission path 6400, which consists of two independent multiple conductor transmission paths 6400-0 and 6400-1. As can be seen from FIG. 3, information originating from the program address register PAR and information originating from the auxiliary storage register ASR can optionally be fed to these independent multiple conductor paths. The controls CCl-CC 2 are optionally assigned to these transmission paths and all other transmission paths as a function of information in the path register 300 and the activity flip-flop 55 AU. As will be explained in more detail below, the controller can be set up (by setting the position register and the activity flip-flop) in such a way that it transmits instructions via one of the two transmission paths or neither.

The instructions transmitted via the transmission paths 6400 are supplied to all program memories PS1 to PSN. As shown in FIG. 64, these transmission paths can optionally be excited by both controls and are inductively coupled to each program memory. Each program memory PS1 to PSN is optionally assigned to the multiple conductor transmission paths depending on the setting of the individual program memory path register 501. As will be explained in more detail below, the state of the route register in each program memory and the type of instructions on the independent transmission paths determine the assignment of the transmission paths and the independent program memories. The program memories transmit responses to the controllers via the transmission path arrangement 6500 which includes a first multiplexer transmission path 6500-0 and a second multiplexer transmission path 6500-1.

Furthermore, independent transmission paths 6403 to 6406 connect the controls CCl-CC 2 the input-output system 170, and separate transmission paths 6600-0, 6600-1 transmit information from the input part 172 of the input-output system 170 to the controllers.

The transmission of commands to the input-output system from the selected control CCl or CC 2 takes place in accordance with the setting of the flip-flop 55AU of each control. As will be shown later, when the flip-flop 55 Λ U is set in the controller CCl, the corresponding flip-flop of the controller CC 2 is reset. Similarly, when the flip-flop 55 AU in the controller CCl is reset, the corresponding flip-flop of the controller CC 2 is set. The controller, whose flip-flop 55AU is set, transmits commands to the input-output system 170.

A basic feature of the embodiment is that a plurality of circuits it is provided that the simultaneous execution of identical work functions by the first and second control CCl or CC 2 ensure. These circuits include the operation check circuits 460, the comparison circuits 360, the malfunction flip-flop 461 and the remedial circuits 462. These circuits will be described in detail later. A brief explanation however, the general way of working should be given now.

In the F i g. 3 to 6, the arrangements are not shown, which the first and second control CCl and bring CC 2 into lock step at the beginning. The arrangements which initiate simultaneous Effect work functions in both controls will be discussed later in connection with the Fi g. 10 to 63 described, and it should be assumed for the following explanation that the two controls to perform identical work functions at a given starting point in time.

As previously indicated, the tax audit circuitry is included 460 a number of arrangements which indicate the incorrect operation of a processor. Such an ad directs Remedial measures a. So are in the embodiment from the program memory part of the Memory system encoded instructions in a redundancy code, which the display and Correction of individual errors and the display of several errors possible. When a single error appears is, the data processing must be briefly stopped or interrupted so that a sufficient there is a long time to correct the error. Similarly, if a must Multiple errors are displayed, processing is temporarily suspended, and action must be taken to try again by reading the memory system of the same address, get a correct reading. Since such errors usually only occur in a controller and that of you

occur at the moment assigned memory system, the display of a fault in one controller must be transferred to the other controller if the two controllers are to stay in step. Gate 463 and conductor 464 are typical examples of the arrangements used in the embodiment to transfer such information between the two controllers, and fault flip-flop 461 is an example of the circuitry which is responsive to this information . The occurrence of a fault output signal in the operation check circuit 460, which is transmitted from the controller CC 1 to the controller CC 2 via the gate 463 and the conductor 464, energizes the remedial circuits 462 of the controller in which the fault has occurred and that to the other Control transmitted signal sets the appropriate fault flip-flop 461. As a result, remedial measures are initiated in the second control which correspond to the remedial measures in the control in which the fault was indicated.

Central data processor 100

The central data processor 100 represents a centralized data processing device which has the following components:

1. Central control 101,

2. program memory 102,

3. Call memory 103.

The program memory 102 exists in the embodiment from a permanent magnet magnet wire memory (Twistor) and therefore enables a non-destructive reading of the information stored in it. The program memory 102, which is used by Semi-permanent in nature, is used to store the more persistent information in the system including using programs. Information is obtained with the help of the program memory card writer 146 written into the program memory 102.

The conversation memory 103 exists in the exemplary embodiment from a ferrite plate memory. Therefore information can be stored in the conversation log 103 or taken from it. Since the information in the conversation memory 103 allow themselves to be changed at the normal speed of the system, the more volatile ones become in it Information stored.

gen controls control and maintenance information on a mutually exclusive basis given to the rest of the system.

In the exemplary embodiment, the central controller 101 executes an instruction, except for a program jump, a reading of a program memory data word or a selection of work functions, for which special sequential circuits described below are required, on the basis of an instruction cycle of 5.5 y &Qc; this represents the time cycle of the program memory 102 and the conversation memory 103. A microsecond clock in the central controller 101 supplies pulses with a length of V2 \ isec and intervals of '/ 4 μεεα. These pulses give the central controller 101 the possibility of a sequence of successive functions within one command cycle, with a duration of 5.5 \ xsec .

Program memory 102

The program memory 102 provides a high-capacity memory system organized by words The number of memories in the program memory 102 is basically determined by the size of the switching system, d. H. the number of subscriber and trunk lines and the Control options, definitely.

30th

Central control 101

55

With regard to the reliability of the system, the central controller 101 has two independent functions Controls on. The independent controllers are both set up to perform all of the necessary operations run within the system. During normal operations, the two run independent Controls the same work functions based on duplicated input information by. This is called lockstep operation. However, only one can at any given time of the two controls change the status of the system or the execution of telephone functions steer. That is, the two independent program memories 102 include three larger ones Sections:

1. Magnet wire (twistor) memory elements with access and readout circuits for optional Acquisition of data,

2. Program memory control circuits and

3. Program memory maintenance circuits.

Any number of memories from 2 to 6 can be used in this particular embodiment will.

Call memory 103

The conversation memory 103 is a high capacity memory organized by words with arbitrary Access in which the more volatile information of the system is stored. In this embodiment becomes a ferrite plate memory organized by words as a memory element of the conversation memory 103 used.

As in the case of program memory 102, conversation memory 103 comprises three major sections:

1. A ferrite plate memory with access, reading and writing circuits for optional Obtaining data from the conversation memory 103 and entering data into the conversation memory 103;

2. Call memory control circuits and

3. Call log maintenance circuits.

Transmission buses and cables

The transfer between the main sections of the system is carried out with the help of a manifold

systems and with the help of multi-conductor cables, the discrete transmission paths between selected sections of the system. The busses and cables will be described in detail later.

The transmission within a main section of the system, for example within the central Control 101, could be done with the help of manifold systems. These internal manifold systems have a large number of single-track parallel routes and should not be included in the following Explanation fall.

By definition, a busbar system should comprise a large number of conductor pairs. A collecting line is a transmission device for the transmission of information from one or more Sources to a variety of destinations. A manifold is inductive to both the information source or sources as well as linked to the loads at the destination. The sources of information are connected in parallel to the bus wires, and the loads are with transformers connected, which are in series in the bus wires.

A manifold system generally has two double manifolds shown in the drawings are designated as manifold "0" and manifold "1".

In addition to the manifold systems, there are a variety of multiple conductor cables that represent discrete transmission paths between selected sections of the switching system.

Switching network 120

The switching network 120 is used to selectively connect subscriber lines via metallic paths To connect subscriber lines via connector circuits or subscriber lines with connecting lines, Connection lines with connection lines, subscriber lines and connection lines with sound sources, signal transmitters, signal receivers, Maintenance circuits and, in the case of subscriber lines, provides connections to coin monitoring switches etc.

The switching network 120 comprises only transmission paths, means for establishing the paths and Means of monitoring the paths. The central data processor 100 contains records relating to the busy and idle status of all intermediate lines in the network and a recording regarding the establishment of any established or reserved path through the network. These Recordings are in the conversation memory 103 of the central data processor 100. The record relating to the busy-free state of the network elements is generally referred to as a network storage map designated. The central data processor 100 interprets connection requests between certain components and defines a free path through the network by specifying the requirements the connection and the above-mentioned busy-free status of the possible routes.

The network is divided into two main sections, namely the subscriber line-link network, in which subscriber lines and connectors (both wire connectors and connector circuits) terminate, and the trunk-link network in which trunk lines and wire connectors, control circuits such as sound circuits, signal receivers, signal transmitters, etc. terminate.

The control of the network and the control and monitoring of those connected to the network Elements are made using a number of control and monitoring circuits. This control provides an effective and convenient buffer ίο between the central data processor 100 extremely high speed and the slower elements of the network.

Subscriber circuits

The subscriber sets such as 160, 161 are normal versions that are used in today's common telephone systems be used. That means they are connected to the office via a two-wire line,

so respond to normal ringing signals with 20 Hz and send either dialing impulses or impulsive tones. But you can also use it for manual operation be set up. The subscriber stations with one or more sets, such as 160, 161, all end at subscriber line connections of a subscriber line link network.

Central impulse distributor 143

The central pulse distributor 143 is a high speed electronic converter, the two Provides types of output signals on the basis of commands from the central data processor 100. The two Types of output signals are called unipolar signals and bipolar signals, and are respectively Assigned output connections of the central pulse distributor, which are used as CPD unipolar points and CPD bipolar points are indicated. Both types of signals consist of pulses from the CPD starting points are transmitted to the consumer devices.

In general, the unipolar signals are used to briefly a certain component, for example a network controller 122, a network scanner 123, and so on. Unipolar output signals are generally used to set the receiving circuit in the form of temporary gate signals to excite. However, they are also used in certain cases to set flip-flops and reset. Bipolar output signals are used to selectively turn flip-flops into both adjust and reset the receiving circuits. A bipolar signal is generated by a "WRMI" safety signal accompanies when it is used to control certain critical circuits will. A signal of one polarity is used to set a flip-flop, and a signal of the other Polarity to reset a flip-flop.

Main scanner 144

The main scanner 144 has a ferrod (ferrite rod) matrix in which the to be monitored Circuits end, and a facility to selectively on the basis of a command from the central Data processor 100 reports the monitoring conditions of a selected group of monitored circuits to the central controller 101 to transmit. That

The scanning element used is a so-called Ferrod arrangement. It includes a perforated rod ferromagnetic material with control, query and reading windings. The control windings are in Series connected to the electrical connections that determine the monitoring status of the monitored Specify circuit. For example, when a ferrod is used to monitor a subscriber line it will be in series with the veins of the partial

via various transmission facilities. That is, because the information is in the program memories 102 and the conversation memories 103 in separate memories of the storage system are duplicated 5 are available, the first central controller receives information from the first memory with the desired information Information and a first manifold of a manifold system, while the Second central control information from the subscriber line and the subscriber set connected to other memory with the desired information tet. When the subscriber set is suspended over the other bus line of the bus line State, no current flows through the system. If you assume Ferrod control winding, while in the unhooked that the from the two memories, either the State a current flows. The query and read program memory 102 or the conversation memory windings consist only of individual conductors, 15 103, information obtained is identical and which lead through the two holes of the ferrod that the transmission paths, d. H. the collecting line. In other words, both the query manager and the reading staff work without a hitch, the two central managers lead run through both holes of the ferrod. A len controls perform the same work functions. Interrogation consisting of a bipolar pulse- At any given time, however, only one signal generated when it is applied to the query conductor 20 central control the connections through the will change an output signal in the read conductor of any ferrod, system, or, more generally, the function a circuit monitors which are controlled inside the system. Only in a few exceptional cases State. When the Ferrod fells one, the other central control can be sidelined Circuit monitored in the unhooked state, will perform lying work functions by those due to the saturation of the ferrod, no read pulse 25 is different from that generated by the control system, the central control.

With the normal lock-step teletype unit discussed above In operation, the two controls work theoretically

with identical input information. Hence should

The teleprinter unit 145 represents a device 3 ° its function be identical. Agreement for the transmission of information from the maintenance of the functions of the two central controls

is carefully checked by a routine comparison of the data flow through each central controller. In the event that a mismatch 35 between the two central controls If flowing data is found, the system will be alerted.

In addition to comparing the data flow through the two central controllers, each central

Program memory 102 to encode. Information, 40 control a variety of tests concerning which are to be given to the magnetic cards are processed by the data. This is how the either a magnetic tape or the central program memory 102 and the conversation memory Taken from data processor 100. The card writing 103 information obtained with the help of parity calculator magnetizes the card magnets wherever bits are secured, and in the case of the program memory a 0 should be entered into memory and 45 102 will also use a demagnetizes the card magnets wherever Hamming coding secured the display

of errors and the correction of individual errors. In the event that one or the other central control either a single or 50 double errors in the from a program memory notices received information, the operation of the system is temporarily halted. With an individual Error the correction is carried out and in the case of a double error the information is repeated Magnetic tape stored. The tapes or the information from the program memory information source then one of the data is read on the tapes. In the case of the conversation memory causes a processing charge center fed, where the parity errors that the system stops briefly and Charge information for calculating the subscribers the information again from the call memory calculation can be used. is read.

60 At this point it seems useful to distinguish between error messages and errors and depict errors. An error should be defined as a disturbed function of components, which the system through a systematic logical

Both central controllers run the 65 operation and cannot repeat the operation while an error occurs balance work processes. Whenever possible, a disturbed function of components, which the central controls receive the same inputs the system through a systematic logical Repeatedly reproduce operational information from different sources and operations. When a

personal to the switching system and to transfer information from the switching system to the maintenance staff.

Program Memory Card Writer 146

The program memory card writer 146 is a device to read the information cards of the

a 1 should be entered in the memory.

Billing Tape Unit 147

Automatic billing 147 is implemented in used by the system to store telephone billing information. This information will be in a single complete record on one

General explanation

The central data processor 100 always contains two central controls. During the usual

Fault indication is detected first, it is not known whether this indication represents an error or an error. The system must therefore take action to make this determination. If, for example, as indicated above, an error in reading the call memory 103 or an address error or a double error in the case of the program memory 102 is indicated, the system stops briefly and reads the corresponding memory again. If the fault display persists, a possible error is displayed, while in the other case there is only a temporary error and the central controls continue with their tasks. It should be noted, however, that the central controller increments a binary counter each time an error is detected and that this counter is reset from time to time. At certain times before the counter is reset, however, the status of the counter is checked in order to ensure that the number of errors which have occurred in a fixed period of time have not exceeded a certain maximum value.

Component description

The drawings often show individual lines as connections between the blocks. The single ones However, lines are only symbolic and can contain numerous connections, such as a cable or a manifold described above.

In certain cases the binary states of a circuit are represented on a pair of alternately energized output conductors. Such an arrangement is called a two-track circuit, and binary circuits that provide individual "0" and "1" output signals are called two-track logic elements. In other cases only one of the two states of a binary circuit is used as an output signal, and such arrangements are called single-track circuits. Throughout the drawings, in many cases, gates, amplifier symbols, etc. may mean a plurality of gates or amplifiers with a number of channels equal to the number of individual signals to be transmitted. For example, in Figure 11, the energized AND gate 1104 transmits the ten bits of information A 0 through A 5, 51, 52, W and CM from the output of the cable receiver 1102 to the input of the symbolic multiple OR gate 1109. Accordingly, the cable receiver contains 1102 ten transformers and ten amplifiers. AND gate 1104 includes ten AND gates and OR gate 1109 includes ten OR gates. In addition, two types of AND gates are shown symbolically in the drawings. The first type corresponds to a conventional AND gate such as AND gate 3006 shown in Fig. 30. This symbol represents a plurality of AND gates the number of which is equal to the number of information paths in a cable. If the cable carries information on a single track basis, there is an AND gate per information bit. However, if the cable carries information on a two-way basis, the number of AND gates represented by the symbol is twice the number of information bits.

The second type of AND gate, which converts information from the single-track state into the double-track state, is shown symbolically in FIG. There the gate 3008 is shown as a conventional AND gate, in which, however, a horizontal line is arranged within the symbol.

Program memory 102 (Fig. 7)

The program storage system 102 includes a plurality of independent program memories. Each program memory is a large memory with random access and, in this exemplary embodiment, consists of a large number of Twistor modules and the associated control, access and reading circuits. Each Twistor module has a storage capacity of 8192 words with 44 bits each. The Twistor words are assigned to one another in pairs in the memory, and each module therefore has 4096 discrete information addresses. The selection of the appropriate 44-bit word from the pair of 44-bit words is made at the output of the twistor.

To allow the use of odd numbers of program memories within a storage system enable and still maintain a complete duplication of information, are the Information duplicated according to the pattern shown for the call memories in FIG. That that is, the information stored in the right half of the "0" program memory is in the left half of the "!" program memory doubled.

The information is obtained from the program storage system 102 by a command from the central controller 101 which designates an information group code name and an address which indicates the location of the desired information word within the designated information group.

The transmission busbar systems 105 with the address and control buses 6400 and the response buses 6500, which are assigned to the central controller 101 and the program memory 102 alone, are used accordingly to transfer commands from the central controller 101 to the program memory 102 and responses from the program memory 102 to be transmitted back to the central controller 101.

Figures 64, 65 and 66 are intended to provide an overview of the various address and control buses and give the response busses of the various units.

In the path register 501 of each memory there are seven flip-flops (not shown) which control the input signals from the bus lines and the output signals to the bus lines. Certain of these flip-flops are set or reset by output signals from the central pulse distributor 143 , while others are set or reset when the memory is operated in the write control mode. A table of these flip-flops, the source of information for setting or resetting the flip-flops and the meaning of the set or reset flip-flops is given below:

209 537/330

17 18

Source and meaning of setting the way flip-flops

Flip flop

Set and reset
by

meaning

RO

CPD

HSO

HSl

GSO

GSl

TBLO

TBLl

Write control

Write control

Write control

Write control

CPD

CPD

set - receiving from the bus line "0"

Sending of maintenance and control readings on the collective line "0"

reset - received from bus "1"

Sending of maintenance and control readings on the bus line "1"

set - transmission of normal readings from H on the manifold »0«

set - sending normal readings from H on the collecting line »1«

set - sending normal readings from G on the collective line "0"

set - sending normal readings from G on the bus "1"

set - Blocking of traffic with the trunk line »0« (both Sending as well as receiving)

set - Blocking of traffic with the trunk line »1« (both Sending as well as receiving)

These flip-flops are influenced by the central controller 101 in order to produce the desired memory bus arrangement to win.

The setting and reset signals for the flip-flops RO, TBLO and TBL1 controlled by the central pulse distributor are received via the bipolar cable 6700.

The "O" manifold shown in Figure 64 contains like the "!" manifold the following 25 bits:

A. 16 address bits A 0 to A 15;

B. 4COdBbItKObIS-O;

C. 4 operating mode bits CM, HM, GM, CR W and

D. 1 single synchronization bit.

Conversation memory 103 (Fig. 8)
The conversation mailbox system 103 comprises a plurality of independent conversation mailings. Each conversation memory consists of a bulk random access memory which, in this embodiment, comprises a ferrite plate memory with destructive reading and the associated access reading and access writing circuitry.

Information is obtained from the call recording system 103 by a command from the central Controller 101 retrieved which has an information group code name and an address denotes, which indicates the location of the desired information word within the designated information group. In a similar way, information written into the call storage system 103 by a command from the central controller 101, which is an information group code name, an address indicating the location for the data and indicates the encoded data to be written in the designated information location. In the program storage system 102, each information group is permanently assigned a discrete code name, and since a block of information is duplicated in both memories, both memories are in which this information is located, arranged so that it is on the information group code

address men. In the case of the program memory 102, it is not possible to store the information in the memories of the program storage system 102 to reorder. In the conversation memory 103, however, there is in the event of a fault in one or more storage tanks

the system has the ability to ensure the duplication of certain important information Reorder information. That is, certain information is in the conversation memories 103 of greater relative importance than other information

mations. Hence, it is in the event of a call heap failure within the call heap system 103 desirable the information to duplicate the more important information at the expense the duplication of less important information

Reassign. Accordingly, although each conversation memory is on two information group code names must address, only one of the code names is permanently assigned to a specific call memory assigned, namely the code name of the in the

left half of the memory permanently retained information group. That of information capacity the code name assigned to the right half of a conversation memory 103 can be obtained by a command in the write control mode of the

central controller 101 can be changed.

The transmission bus system 106 with the address and control buses 6401, the Data bus lines 6402 and the response

trunks 6501, which are assigned to the central controller 101 and the call memory 103 alone is used to transfer commands from the central controller 101 to the conversation memory 103. wear. In addition, write data from

the central controller 101 to the conversation memory 103 and responses from the conversation memory 103 returned to the central controller 101. In addition to these three own transmission paths

each conversation memory 103 receives information from the central controller 101 through output signals of the central pulse distributor 143.

The call log reply trunk system 6501 includes two buses "0" and "0" »1«, each containing 26 pairs of conductors.

As in the program memory 102, there is a route register with seven in each conversation memory 103 Control flip-flops (not shown) present. These are provided to receive the input signals from the Bus lines and the output signals to the

Control bus lines. Certain of these flip-flops are activated by output signals from the central Pulse distributor 143 discontinued or deferred while others discontinued in operation of the call store 103 in the write control mode or postponed. A table of these flip-flops, which are part of the controller 801, the source of information for setting or resetting the flip-flops and the meaning of the set or deferred flip-flops is listed below:

Source and meaning for setting the way flip-flops

Flip flop

Set and
postponed by

meaning

RO

CPD

HSO

HSl

GSO

GSl

TBLO

TBLl

Write control

Write control

Write control

Write control

CPD

CPD

set - receiving from the bus line "0"

Sending of warning and tax readings on the bus "0"

deferred - received from bus "1"

Sending maintenance and control readings on bus "1"

set - send normal readings from the Η side on the Collective line "0"

set - send normal readings from the Η side on the Collective line "1"

set - send normal readings from the G-side on the Collective line "0"

set - send normal readings from the G-side on the Collective line "1"

set - blocking of operation with the manifold »0« (both Receiving as well as sending)

set - Blocking of the operation with the manifold »1« (both (Receiving as well as sending)

These flip-flops are influenced by the central controller 101 to produce the desired memory bus combinations to obtain.

After this general overview, the operation of a call store 103, which is shown in FIG shown can be described at a number of operating conditions. In the lockstep mode of the central control 101, the central control system 101 transmits identical address and control information via the duplicated busses of the address bus system 6401, and if so a write command is to be carried out, identical data from the central control system 101 via the two call memory write data buses 6402 transfer. This identical information on the two manifolds of the system 6401 and 6402 can come from the central control that is in operation, or a collecting line each of the manifold systems 6401 and 6402 can be through the operational control center Control, while the other bus of each system is addressed by the in Central control in waiting position is addressed.

The connection of the address bus lines to a conversation memory 103 is shown in FIG. The bus line "0" contains, like the bus line "1" shown in Fig. 64, 26 bits:

a) 12 address bits AO to All,

b) 6 code bits KO to K5,

c) 3 operating mode bits HM, GM, CM,

d) synchronization bit 51,

e) 2 command bits R, W,

f) 1 parity bit,

g) synchronization bit 52.

Pulses on the five lines HM, GM, CM, R and W define the operation of the memory.

The data to be written into a defined word position are transmitted from the central controller 101 to the Conversation memory 103 via the conversation memory write data bus system 6402 and this information is given to data register 9016.

Central impulse distributor 143
(CPD from Central Pulse Distributor)

Commands are transmitted from the central controller 101 to a central pulse distributor in the form of pulses with a length of V2 μς, εο. The necessary to control a central impulse distributor

21 22

the relevant information is presented in three at a distance The central control system carries out data processing

from 1.25 \ lsvc successive groups over-functions according to program commands that carry. The bus selection information, which is mainly stored in the program memory 102 , indicates that the central pulse distributors are information. In some special cases the program either from the bus “0” or “1” of the 5 commands is also stored in the call memory 103. Address bus system 6403 receive the program commands are intended to be within the memory, is first placed in the first group to all cen- in ordered sequences. The program values for impulse distributors via the CPD bus line can be subdivided into two main classes, transfer bus line 6405 . The CPD-Sam- namely decision commands and non-decision line selection trunk 6405 has two Sam- ίο training commands.

line pairs »0« and »1«. The collective decision-making commands are generally

Connection selection information follows 1.25 usec later, a uses to execute the desired processes on the basis of address information on one of the busbars changing states either with reference to subgene "0" or "1" of the CPD address bus subscriber or connection lines that by the system 6403. Each of the two trunks of the 15 switching system are served, or with reference to CPD trunking system contains 34 parallel to arrange the maintenance of the system.
Couples. CPD address information is provided by the decision commands that dictate that a

central controller 101 is transmitted to a CPD in the form of a decision with reference to certain observed Zul-aus-8-, 1-aus8-, 1-ausl6 code, which is to be hit 32 levels, and the result of the 34 pairs of each of the CPD address bus 20 decision causes the central controller to require. In addition, each bus contains a test lead and a reset lead for the next command of those currently being handled. Sequence of command words to continue or to

The specific central impulse distributor of the multiple one command in another sequence of instruction number from central impulse distributors that jump to a word. The decision to respond to an on command is to jump with the help of a CPD. The other sequence can be connected to a further Be execution signal on one of the pairs of the CPD mood that the jump on execution cable 6404 is indicated. The pairs of out a particular one of a multitude of sequences of cables 6404 are individual central impulses to be taken. Decision commands are assigned discretely to distributors, and the signal on the is also called conditional jump commands.
CPD execution pair follows the CPD address information. 30 Non-decision commands are used to communicate with a distance of 1.25 μβεα units outside the central controller 101 in

The central controller 101 will establish the correct connection and both to give data from the receipt of the address information and the execution from one location to another and to logically process the execution of the command with the aid of confirmation signals. For example, the central impulse distributor can confirm which of 35 data with other data are being transmitted by the logical radio of a central impulse distributor to the central controls AND, OR, EXCLUSIVE OR, product range. concealment, etc., and also

In addition to the verification of the address information, data can be complemented, shifted and romation that can be fed by a central controller 101 .

has been transmitted to a central impulse distributor 40 non-decision commands carry out some data verifications, the central control also checks the generation and / or transmission processes, establishing the appropriate central impulse distributor. This and after the completion of these processes, most non-decision commands are reached with the help of a CPD execution response signal, which is sent from a central impulse distributor to the controller 101 to carry out the next operator central controller 101 via a discrete pair 45 errors in the sequence. A few undecided CPD execute response cable 6502 commands are called unconditional jump commands. The CPD response pair is only a script that stipulates that a jump from the extension of the CPD execution pair. For this reason, a momentary sequence of program command execution signals from a central controller is transferred to another sequence of command words.
carrier in a CPD and becomes the central control The central control 101 processes due to

tion 101 is returned, in which it is also generated by the command word sequences and data and received via a series-connected transmitter carries signals for the control of other units of the which is connected to the characteristic impedance of the transmission system. The control signals, called the commands, are completed. 55 are optionally transmitted to the program

_, _ - _M. ". . _Λ,. " _N gram memory 102, the conversation memory 103,

Central control 101 _{the central} i _mpu i _SVE rteiler 143, the Hauptab- (10 to 63 Fig.)

The central controller 101, which is shown in simplified buttons 144, the network units, such as for example in Fig. 9 and in detail in Fig. 10 to the network scanners 123, 127, 135, 139, the network 63, provides the data processing unit 60 factory. Control devices 122, 131 represent the network of the system. To illustrate, the central signal distributors 128, 136, 140, and the mixed control 101 can be divided into three main parts: Units such as the teletype units 145, the program memory card writer 146,

1. Basic data processing facilities; and automatic billing (AMA)

2. Equipment for the transmission of messages 65 147. ■ -. ' :

with input sources and output devices of the The central controller 101 provides a synchronous

central control; System in the sense that the functions within

3. Maintenance facilities. half of the central controller 101 under control

23 24

a polyphase microsecond clock source 6100, the central control of which takes place via the conductor 6111, which transmit clock signals for carrying out the amplifier 6112, the transmitter 6113 and a veraller logical functions within the system binding-transmission pair,
supplies. The from the microsecond clock source 6100 to a maximum data processing capacity

Derived clock signals are used with DC power to achieve 5 central controller 101, one signal from a number of sources is used in the instruction three cycle overlap. Combined in this working combination gate circuit 3901. In this way, the central control simultaneously executes the following details of the command combination gate switching processes:
device 3901 are not shown in the drawings,

since such a large number of details make the invention a. The operational step for a command;

The basic principles of the system are only obscured ß. Receiving the command from the program, memory 102 for the next operational step;

Work sequence of the central controller ^c - Sending an address to the program

store 102 for the next but one command.

All functions of the system are activated under 15

Execution of instruction sequences carried out from the This operating mode is shown in FIG. 69. the

Program memory 102 or the conversation memory cycle overlap is made possible by 103 can be won. Each instruction in a sequence has both an instruction word buffer register 2410 and a the central controller 101 initiates an operating and an instruction word register 3403 and their entry perform. One operating step can be provided for several speaking decoders, namely the Some of the above logical functions include instruction word buffer decoder 3902 and the instruction or a decision and the answer decoder 3904. A mixed decoder 3903 triggers witness and transmission of commands for developments between the program words in the their units of the system. Command word register 3403 and the command word buffer

The central controller 101 passes this through a fer register 2410. The auxiliary word auxiliary buffer register Command specified operating steps at times 1901 compensates for time differences in the program, determined by the phases of the microsecond clock memory response time.

source 6100 can be determined. Some of these operating The initial gate signals for the command X -

steps take place simultaneously within the central one, referred to here as the index cycle - are held in the controller 101, while others ·. 30 command word buffer decoders 3902 are executed in succession when the occurs. The basic machine instruction X in instruction word buffer register 2410, which in this embodiment conducts 5.5 nsec. Command X is (while it is still in regret, is divided into three main phases of roughly the same length, error word buffer register 2410 for the index cycle. For control purposes, it remains in sequence) during phase 3 of cycle 2, the operation within a main phase of the machine error word register 3403 supplied. After the cycle has been reached, each phase is further in V2 \ istc long Inier command word register 3403, the end gate intervals are subdivided, which are initiated ^{every 1} A y & zc. operations for the command X - here with execution

To designate the times, the main machine cycle is designated - with the help of the command word decon cycle (see FIG. 68) in ¹ U ys & c long intervals of the 3904 are controlled.

40 The duration of the index cycle and the execution interval are denoted by Γ0 to T 22 ver Cycle is each smaller than a machine cycle. The main stages will be stage 1, stage 2 of 5.5 \ xs & c. Called when executing operational step and phase 3. These phases lie in the th of a sequence of commands, for example the machine cycle of 5.5 \ l $ qc as follows: according to FIG. 69, each command remains 5.5 μββΰ im

_Λ ■ 45 command word buffer registers 2410 and 5.5 nsec in the

A. Phase 1 - Γβ to JS, ^ error word register 3403. The command word buffer deco-

B. Phase 2 - T 10 to 1 16 which are 3902 and the command word decoder 3904

C. Phase 3 - Γ16 to 1 22. DC combination circuits. To simplify the following description current output signals of the decoders, time periods 50 selected pulses from the microsecond clock are denoted by bTe , where b is the number that corresponds to the source (from the ones shown in Fig. 68) is assigned to the command point in time at which a time period combining gate circuit 3901 combines begins, and e is the number assigned to the point in time. This circuit 3901 accordingly generates the correct net at which a time period ends. Sequence of gate signals to carry out the in-

According to FIG. 61, each central control cycle and the execution cycle of each sequence has a clock oscillator 6106 for 2 MHz. The of commands in the order in which they occur first in the clock oscillator 6106 of the active central control command word buffer register 2410 and then in the operating mode of the microsecond clock source 6100 both in the error word register 3403,
the active central control as well as the reserve The implementation of the operational steps for certain central control. The oscillator 6106 of the active 60 commands requires more time than an operating step central control is at the input of the microsecond period, ie more than 5.5 μεεΰ. This additional time requirement for the clock source 6100 of the active central controller can be an essential property via the AND gate 6108 and the OR gate of the instruction. In other cases demand 6110 is switched on. The AND gate 6108 is determined by additional time, but by an indicated interference signal on the command line header AU (Fig. 61) 65, which is excited upon execution, which indicates that the activity flip of an instruction is occurring. When an instruction indicates that flop 55 AU (Fig. 55) is in the "1" state. The fact that its execution takes longer than an operating step output signal of the oscillator 6106 is to the period, the additional processing time can

25 26

for this command obtained in the following way 5301 energized for a correction or re-reading

are: of the program memory 102 at the previously addressed

1. Implementation of the additional data processing unit. This sequential circuit represents tion during and immediately after the index - an example of a sequential circuit that is carried out by cycle of the command and before the execution 5 a fault display is activated and the control cycle of command; the central controller 101 excluding the

2. Implementation of the additional data processing decoder takes over.

processing during and immediately after the command-command sequential circuit 4902, the

normal execution cycle of the command. Network commands to the switching network

The implementation of these additional work functions 120 and the mixed network units, i. H. With the help of a large number of sequential switches, the main scanner 144, the charge recording entries within the central controller 101 it is 147 and the card writer 146 transmits, enough. These sequential circuits are individual structures, represents an example of the sequential circuits that which by assigned program commands or interference after their excitation over the degree of overlap indicators are energized and serve the 15 in F i g. 84 shown, i.e. i.e. that the Time for the operating step beyond the normal, shown in FIG. Transmission of network commands to the Aus-69 the operating step period shown extends beyond the execution cycle of the command, which allows the network expansion, work command command follows.

The subsequent circuits take on the control,. , "'

the data processing within the central office- 20 response of the central controller

tion 101 with the decoders, i. H. the command word program command word

Buffer decoder 3902 (BOWD), the command word de- Fig. 9 shows a simplified circuit diagram of the central

coder 3904 (OWD) and the mixing decoder 3903 central control 101 and facilitates understanding

(MXD) . For commands where the additional of the main operational steps carried out by the central

Work functions before the start of the execution cycle 25 Control 101 based on various program

klus are carried out, the sequential circuit controls command words to be carried out. Every program

the central controller 101 excluding the de- command word contains an operating field, a data address

coder BOWD, OWD, and MXD. For commands, however, field and a Hamming error display and correction

for which the additional work functions can be selected.

30 There are groups of optional, additional becycles of the command, control the failures present by each of the Sequential circuits and the decoder together and program instruction words can be determined, at the same time the central controller 101. In the latter, the operational step of each command consists of one In this case, a number of restrictions apply to the particular group of tag functions that can be used which follow a command that contains the processing of in the central controller 101 makes a sequential circuit necessary. These ten data and / or for the exchange of informa restrictions ensure that the elements of the functions between the central controller 101 and centralized Control, the units of the system through the sequential circuit. If an optional are controlled, not at the same time by the pro-additional possibility by the executor program command words can be controlled. 40 program command is determined, an additional

Each sequential circuit has a counting circuit, the data processing in the operating step from which States that are executed by the sequential circuit. The special gate functions and those for Define leading tag functions. The excitement carried out every optional additional option a sequential circuit consists in the fact that its counter data processing is described elsewhere Gear is brought. The output signals of the 45 ben. Part of the 14- or 16-bit operating field Counting levels are defined with other information signals of a program command word, i.e. the proin the central controller 101 and with selected program command, and the remaining part of the field can Clock pulses for generating gate signals in one or more of the additional ones to be executed select the command combination gate circuit 3901 korn options.

amated. These gate signals carry the required 50 ..,,, __,, ', "" "",., -.

Gate functions of the sequential circuit by ^capping and comparable ^'and complement circuit 2000 (M & C)

start the counting circuit, its sequence of internal The internal data processing is based on two

States to go through. Multi-conductor collecting lines, the uncovered

A few examples are intended to explain the usefulness of the 2014 follow-up line (UB) and the hidden busbars. A program command that is used to transfer a multi-bit data word to 55 line 2011 (MB), which is a connection element for reading data from the program memory 102, requires an additional group of flip-flop registers to be carried out Period of two 5.5 ^ isec machine cycles. represent another group. With this type of instruction, the additional two from the index registers 2601 (BR), 5801 (FR), 5802 cycles are obtained by assuming the 60 (JR), 4001 (KR), 2501 (XR), 3001 (YR ) and 3002 immediately following command is delayed and (ZR) and the logic register 2508 (LR).
that the additional work functions after the end of the index cycle and before the execution (M & .C) connects the uncovered bus UB cycle of the command currently being processed through- with the hidden bus MB and provides one. 65 Device for the logical processing of the data

If errors are made when reading words from the uncovered manifold UB to

occur in the program memory 102, the program will go to the concealed collecting line MB. From-

gram - memory - correction - re-read sequential circuit supplying logical processes, namely a co-

27 28

incidence concealment (AND), a mixed concealment has been given the name "displacement".

(OR), an exclusive OR masking (exclusive The gate-

siv-OR) and complementing are made by the function based in part on the bits of the last six

Operating field of the program command prescribed, digits of the number contained in the index adder 91 ^ 1

which occurs either through the instruction word buffer decoder 5 at the point in time in which the shift

BOWD or the command word decoder OWD deco. The bits of the last five digits

dated represent a number representing the amount of shift

The cover and complement circuit indicates M&C , and the 6th bit determines the direction of the

(2000J, the shift shown in more detail in Fig. 20. A "0" for the 6th bit is used as a shift

is also a convenient means of connecting io interpreted to the left and showing the remaining 5 bits

The size of this shift is indicated by the data buffer register 2601 and the index. A "1" for that

adder output register 3401 with the hidden 6th bit is interpreted as a shift to the right,

Show manifold 2011 are. And the complements to one of the remaining 5 bits

τ, ^. λκμ ζ, ™ · * ir τ -i , vT n ^ \ the size of the shift to the right. Even though

K-Register 4001 (KR)) K-Lo ^ k (KLOGy, _with shifts to the right the bits of the last five

First Ems Indicator Circuit 5415 (DFO) Digits the complements to 1 for the size

The if register KR, the X logic KLOG and that of the shift will form the number with 6-bit first-one display circuit 5415 (DFO) , which will be treated in the following as if it were a second important internal data processing device and has a size
tion. The Z logic KLOG has input and output 20 A shift by one to the left leads to output circuits which surround the register 4001 that the content of each flip-flop in the register KR . The K logic KLOG contains the iL4 input to the flip-flop output register 3502 adjacent to the left-hand side, the i&B input register 3504 , when the register corresponds to FIG. 40 the X input logic 3505, which is considered if-logic-homogeneous. (The bit of the highest digit digit ity circuit 4502 and at the output of the üC register 25 of the if register KR, the bit 22, is on the 4001 the rotary shift circuit 4500 and the extreme left side, the bit of the lowest digits -X- Register homogeneity circuit 4503. The K-lot , bit 0, is located on the rightmost gik KLOG can be output signals from the command side.) A "0" replaces the content of the lowest bit combination gate OCG to carry out a digit position of the if register KR (to the right of which four logical operations on two operators 30 flip-flop of the "O" digit position is not preceded by a flip-flop. An operator is the content of the hand), and the bit of the highest digit position becomes if register KR; the other is the information on shifted out of the register, ie the flip of the hidden bus MB. The command word flop for bit 22 is not a flip decoder OWD on the left and the if register sequence circuit Flop is adjacent, and the information is lost. (Part of SEQ) generate signals that cause the if logic 35 Shift by two to the left corresponds to two KLOG , the two operators by successive shifts by one after functions AND, OR, Exclusive-OR or left, etc. A shift by one link to the right addition. The result of the logic means that the content of each flip-flop of the if-ReVerknüigung word can be given either 40 flip-flop according to gisters KR to the command on the right side adjacent to the command in the command word register OWR. A "0" replaces the content of the if register KR or the homogeneity of the bit of the highest digit of the if register KR, control circuit CH and the sign control circuit and the original bit of the lowest digit CS . of the if register KR is consequently dropped.

A word on the hidden busbar MB A logical function similar to displacement

can in some cases directly to the if register KR 45 is the function »Rotation«. As with the different

can be given via the if logic KLOG . The K- practice will use the 6 bits of the index adder IA as

gister KR can be treated in this way as simply determining the direction and magnitude of the rotation, such as

data registers are used like those described above for the shift,

other flip-flop registers in the central controller,. A rotation by one to the left is

for example XR, YR, ZR etc. 50 shift identical to one, with the exception of the

When performing the addition function in the control of the two end flip-flops of the if register if logic KLOG , the two operators are considered to be with KR. When rotated one to the left, the signed numbers are treated as 22 bits. The content of bit 22 is not the same as with the shift. The 23rd bit of each operator is the sign bit. loren, but replaces the content of the O bit of the If this bit has the value "0", the number is positive, 55 lowest digit of the if register KR. One and its size is indicated by the remaining 22 bits. Rotation by two to the left is identical to two. When the sign bit is a "1", it is consecutive rotations one to the left. The number is negative, and its size is determined by the complex. Another logical gate function is the elements of 1 of the remaining 22 bits (the size of the mood in the content of the if register KR am is determined by inverting each of the 22 bits). 60 rightmost »1«. This is achieved. The adder circuit within the if logic KLOG by the content of the first-one display circuit can use all positive and negative operators as long as DFO to the F register Fi? Add correctly over the uncovered line, such as how the size of the algebraic line UB, the cover and complement shawl sum of the two operators is equal to or less than line M&C and the concealed line MB as2 ²² -1. ■■ 65 is fed. The transmitted number is a binary

The if logic KLOG and the Z register KR can number with 5 bits that are assigned to the first cell (from the right

also see other logical functions with the content) in the if register KR , which corresponds to a "1"

of the if register KR . One of these radio stops. If the bit of the lowest digit of the

29 30

K register KR is a "1", the number 0 is fed to the word either only "O" values or only "1" values F register FR . If the first contains "1" of, the homogeneity control flip-flop 5020 is set in the next digit as seen on the right. In the other case, the flip-flop, the number 1 is fed to the F register FR. When postponed. The sign control circuit CS has a single "1" in the K register KR in the highest 5 maintains the sign of the data word. The prefix is the number 22 to the F register character control flip-flop 5413 is set, if given. If the K register has no "1" values or the word is negative, and if that holds, the F register Fi? nothing fed. Word is positive.

_T , ,,. , j, ·> The homogeneity control circuit CH and the

lnaexaaaierer \ ia) ^ Sign control circuit CS will be for some

A third main data processing arrangement uses decision instructions in such a way that the

within the central controller 101 , the index output signal of a selected index register is on

adder IA, which is used for the following purposes: the uncovered collecting line UB, through which

1. Formation of a value which is designated here as a ^{DAR word reached by a dec} *: ^and complement circuit M&C on the ver-Indexvfrfahren- ¹ ^ ^covered busbar MB and from there m <üe net and from the sum of the DA field of the Homogem ats SteuerschaltungCHunddieVorzeichenausgeführten program instruction word and the control circuit CS are given this content consists of an index register, which in one ^{of the} ™ ^em £ ^s ^ r seven index register,, ° j processed decision instruction is given by τ- _c,., m Command is aneeeeben; , _TT . ^ ... _ .. JS , -n ^ n jj · Λ

2. Performing the role of a general purpose adder. ²⁰ the homogeneity flip-flop 5020 and the pre-The operators can be identified from the character control Fhp-flop 5413 in this case. Wei contents of two index registers or the DA ^te F? ^ ¹¹⁶¹ * ¹¹ ? ^? ^{1 m} Y ^erb ™ ^dun g * for an En field and the contents of an index register request command lead to the jump or the For-

. ⁶ output according to the output signals of the escape

25 DECL elimination logic .
Decision Logic 3906 (DECL) Similar homogeneity and sign circuits

During execution, the central controller 101 runs a part of the K-logic KLOG and represents a decision command in a sequence of devices for a class of decision commands either in the current sequence of commands, a jump or a continuation commands continue or jump to a new sequence of 3 ° according to combinations of homogeneity and commands. The decision is initiated by the decision sign of words with 23 bits in the K register formation logic 3906 (DECL) according to the command, KR.

which is currently being processed. The command _{x T,.} , _x .... . ,,. ,

provides the information to be checked and the basis for message transmission between the central

the decision to. The information can be obtained from the 35 controller 101 and connected units
Homogeneity control flip-flop 5020, the homogeneity A second main function of the central control

ity control circuit CH, the sign control 101 is the message transmission to and the flip-flop 5413 of the sign control circuit CS messages received from various other inputs or from selected output signals of the K logic, such as the various memories KLOG will. The basis for the decision 40 within the central data processor 100, the decision can consist in the fact that the checked information switching network 120, the main scanner 144, mation (not or at least) arithmetically zero, smaller than the central pulse distributor 143 , etc.
Is zero, greater than zero, and so on. A Progress Decision The message traffic comprises three general ones

manure interferes with the instantaneous sequence for the gain types. The first type does not concern the acquisition and execution of instructions. A de- 45 program command words, which command the sequence from the preliminary decision to jump to a new sequence of commands within the central controller 101, is coordinated in accordance with the determined one. Program instruction words are primarily coupled with a determination of whether a line is obtained from program memory 102 . However, if the jump is an "early jump" or in special cases, programs will also be a "late jump". Accordingly, if the decision is to jump, 5 ° command words for restricted processes are obtained from an ent call memory 103 . The second type, neither the ETR early jump ladder nor the late jump ladder, comprises the acquisition of data (not energized LTR program ladder and thus the jump sequence command words) from the storage units within device 4401 being activated . Jump signals from the central data processor 100, and the third of these conductors cause the jump 55 third type relates to the generation and transmission of address to the program address register PAR. Commands to the various network units. This register causes the next program command word, such as the switching network 120, for example, to be obtained from a new sequence of command words to the main scanner 144, the central pulse. divider 143 etc.

Two input sources of information for the 60 The various memories within the central decision logic are in the output signals of the data processor 100, namely the program memory homogeneity control flip-flops and the sign 102, the conversation memory 103, the auxiliary buffer register control flip-flops Flops are present that are used to register 3105, 3118, 3605, 3617, 4103, 4603, 5105 to 5107, homogeneity and sign information from 5500, 5902, 6205, 3206, 3703 to 3708, 4206, 4211, a number of digits . Example- 6 ₅ 4717, 2725, 5201, 5209 to 5211, 5604, 5605, 60Ö2 _: wise a data word with 23 bits can be written on the cover- 6003, 6302 and 6307 (ABR-I ... ABR-N), and pray Collective line MB to the homogeneity control agreed other locations within the central control circuit CH are transmitted. When the data- ing 101 is treated as a storage unit, and

certain blocks of addresses are individually assigned to each of the memories. There are a number of memory commands for the selective extraction of information from the abovementioned memories and used to enter this information into selected registers within the central controller 101 will. These are memory read commands. There are other memory commands that can be used optionally Transfer of data from designated registers within the central controller 101 one of the above-mentioned memories can be used. These are memory write commands. In this way the command structure is simplified, since all of the above-mentioned memory locations can be accessed using a single memory address format.

A memory code address within the central controller 101 always contains a word with 20 bits, consisting of:

1. a code to define an information block and

2. an address within the specified block.

Program instruction words

The transfer between the central controller -101 and the program memory 102 for obtaining program command words can be understood with the aid of FIG. 9 and in greater detail with the aid of FIGS. 10 to 63 and the timing diagram in FIG. 69. The program address register 4801 (PAR) and the auxiliary storage register 4812 (ASR) are optionally used to transfer commands to the program memory 102. The program address register 4801 is used in the absence of uncorrectable program memory read errors. The auxiliary storage register 4812 is used whenever a program memory 102 must be read again. When a command is transferred from the program address register 4801 to the program memory address bus system 6400, the code address of the command is also given to the auxiliary storage register 4812. The auxiliary storage register 4812 therefore temporarily stores the code address used to perform the Hamming error checks. These checks are applied simultaneously to the returned command and the address used to obtain the command. Instructions to the program memory 102 for reading information from the memory itself as opposed to addressing test points within the memory access and control circuits contain 25 bits as follows:

A. 16 address bits A 0 to A 15,

B. 4 code bits KO to K 3,

D. 4 operating mode bits CM, HM, GM, CRW,

C. 1 single synchronization bit SYNC.

The code bits KO to K 3 define the information block in which the selected program memory word is located, and the address bits A 0 to A 15 define the memory location within the defined information block.

The 4 operating mode bits define the operating mode of the program memories as follows: Note that the program memory 102 in obtaining program instruction words and system operating data words is always operated in the normal way of working. The two maintenance procedures and the Read control and write control operations are for extracting information from program memory reserved to be treated as maintenance data.

The code and address parts of the program memory commands are obtained from the program address register 4801 or the auxiliary memory register 4812 and the 4 operating mode bits and the synchronization bit from the command cable 3900. The 4 operating mode bits must optionally deviate from "0" in all operating modes except the normal one, and in these operating modes they are defined by the executed program instruction words.

The program memory transfer bus select gates 3300 are divided into two groups, those used to transfer to the "O" bus 3306 of the program memory address bus system 6400, and those used to transfer to the "1" bus 3307 of the program memory - Address bus system 6400 are assigned. The command information is optionally fed to the "O" bus of the program memory address bus system 6400 according to the set of program memory central control buses used. When information is transferred from the central controller 101 to the program memory 102 over the "0" bus 3306, the AND gates 3302, 3303 and 3312 and the amplifier 3310 are used. However, when commands are transmitted over the "1" bus 3307, AND gates 3303, 3309 and 3313 and repeater 3311 are used.

The program memory transfer bus select gates 3300 are selectively energized according to the setting of the state and path register flip-hops 55 AU, 55 PBO, 55 PBA and 55 PBT (FIG. 55) controlled by the central pulse distributor. The state of the flip-flops 55 AU indicates which of the two units is the active central control. The flip-flops 55 PBO, 55 PBA and 55 PBT have the following meaning (with the exception of commands for read or write control or maintenance data):

PBA PBT Active Receive Reserve- Receptions PBO Central control 0 Central control 1 0 0 Send Send 0 0 1 0 0 1 1 0 0 0 1 0 0 I. 1 0 0 & 1 X 0 J. 0 1 0 & 1 X 1 1 1 1 0 & 1 1 X 1 0 & 1 0 X 1 0 1

209 537/330

33 34

In the table, the character X means that the program memory reserve central control is accordingly neither on the "0" - nor the reply bus selection gate 1200 through on the "!" Bus, since the active Zen command cable signals on the PSB conductors 0 and PSB 1 central control on both collecting lines. excited in the period 19 Γ 8. This will make the

The state and path flip-flops 55 AU, 55 PBA 5 reception of the full pulse width (about 0.5 μβεσ) of the 55 PBO and 55 PBT are ensured by pulses choice program memory response. The mode set and postponed by the zengram memory response bus selection gatetral impulse distributor 143 via selected pairs ter 1200 are optionally energized to accept the response of the bipolar cable 6700, the transmitter 1707 from the "O" bus 6500-0 or by the amplifiers 1708 and 1711, AND gates 1709 and io "!" - bus 6500-1 of the program memory 1712 and the CPD cable 1719 can be received. Response manifold system 6500 to receive

The flip-flops 55 PBO, 55 PBA and 55 PBT in gen. The specific gates that are energized are controlled by two central controllers according to the setting of the through the same CPD points, ie when the flip- central impulse distributor controlled status and flop 55 PBO in the first central controller set a 15 way flip-flops.

is set, its counterpart is 55 PBO in the The response word with 44 bits is also set via the other central controller. OR gates 1209 and cable 1210 carry flip-flops 55 AU (active unit) in both the center and auxiliary command word buffer registers 1901 and central controls are also entered through a single command word buffer register 2410. The bipolar signal point of the central pulse distributor 20 bits 0 to 20 (the data address field) and the bit 37 are controlled. The bipolar signal that causes the setting up to 43 (the Hamming coding bit) are transferred directly to that of the flip-flop 55 AU in the first central control command word buffer register 2410 via AND gates, however, represents the flip-flop 55 AU in 1907 and 1906 and OR gates 2428 and 2425 returned to the second central controller. In similar give. The bits 21 to 36 (the operating field) are input in the manner the CPD signal causes the flip-flop 25 to reset the auxiliary command word buffer register 1901 via the 55 AU in the first central controller, AND gate 1905. The synchronization setting of the flip-flop 55 AU in the second signal is transmitted via the OR gate 1211 to central control. and used the AND gates 1905, 1906 and

The to excite the determination of the code address of a pro-1907, which serve to the received

The information required for the program memory command is stored in 30 words with 44 bits in the auxiliary command word buffer register.

the program address register 4801 via one of ster 1901 and the command word buffer register 2410

three possible routes fed, with the selected feed.

Way is determined by the sequence of events, the all-seeming signal represents when it is of the

which is received to determine the desired address "O" trunk 6500-0, the

and lead the code. The desired code address 35 flip-flop 1214 in its "1" state and, if

is optionally derived from the "!" manifold 6500-1 with the help of one of the following verbs, the

drive won: Flip-Flop 1213 enters its "1" state. The flip

A. When executing a sequence of program flops 1213 and 1214, two input signals are provided command words and in the absence of a jump for the error display and correction circuit 2400 The decision will be the code address of the next 40. On when a program memory response word is received the consequence of increasing the code word missing all-seemingly good signal shows a possible address of the previous command word to the borrowed disturbance within the program memory 102 Count 1 won. This increase will help with. Hence the validity of the answer is questionable.

of the add-one register 4304 and the add-one

Logic 4305 effects. 45 data words

B. The second source of program memory code address words is the index add output register. As discussed above, extensive information is available at 3401 (Fig. 34). This register is provided to store functions as data words as opposed to Prodas DAR word, as described above. The contents of the index add output register 3401 50 in the conversation memory 103 and the program are stored via the cable 3402, the AND gate 4307 and memory 102. The information going faster via the OR gate 4808 to the program memory is mainly transferred in the register 4801. This information transfer call memory 103 stored during the conference is achieved by energizing the command cable liter bileren information in the program memory 102 431 RPA . 55 are saved. In addition, maintenance data,

C. The third source of code address information, which is internal to the control and access circuits, is the concealed bus line 2011, the contents of which are stored in program memory 102 and the conversation memory in program address register 4801 via cable 103 and in the reserve central control 4313, AND gate 4308 and the OR gate are treated as data for message traffic 4808 at time 3 T 5 by energizing the command cable 60.

Head of MBPA is fed. This way can be done in data words by executing

The case of interruptions is used to program instructions called "memory instructions"

gramme address register 4801 Code address words are read from, from a memory location or into a

to the interrupt address source 3411, the memory location can be written. Under these and is also used for early jump commands.

det to read the contents of the / register 5802 or the write commands «. Memory commands cause the

Z register 3002 the program address register Generation and transmission of commands to the

4801 feed. different locations as follows:

35 Storage reading
command write
command Call memory 103
Memory itself
Control and access
Program memory 102
Memory itself
Control and access ..
Reserve central control 101 ..
Auxiliary buffer register X I XX XX X
X
X
X
X

The table above shows that both memory read and memory write commands relate to many of the Let data storage be used. However, memory write commands cannot refer to the actual memory of the program memory 102 can be used, and memory read commands can also cannot be used with reference to the reserve central controller 101.

Call memory storage commands

Memory read (write) commands which extract data from (store in) the call memory 103 contain call memory read (write) commands as part of their operational step. The operation step of such commands is indicated by the example of the command X in FIG. In this example, call storage commands are generated and transmitted during phase 3 of the index cycle. If X is a memory read command, the chat memory response is transferred from chat memory 103 to data buffer register 2601 during phase 1 of the execution cycle. If X is a memory write command, the word to be stored is transferred from data buffer register 2601 to conversation memory 103 during phase 1 of the execution cycle.

When executing a call memory command, the code address is always in the index adding output register 3401 which is sent to the talk memory transmission trunk selection gates 1000 is switched on via cable 3402. Bits 17 to 12 of the index add output register form the code part of the command and bits 11 to 0 form the address part of the command.

That generated as part of the call log command Parity signal is generated by the index-adding parity generator 2415 on the basis of the at the outputs of index add output register 3401 and transmitted to it via cable 3402 Code address generated.

The talk memory transmission trunk selection gates 1000 are divided into two groups, namely those intended for transmission on the "O" bus 1004 of the memory address bus system 6401 can be used, and those belonging to the "l" trunk linel003 of the call store address bus system 6401. The command information is optionally connected to the "O" manifold 1004 or the "!" manifold 1003 according to the The compilation of the conversation memory 103 used is transmitted to the central controller 101.

The call memory transfer bus selection gates 1000 are selectively energized according to the setting of the state and path register flip-flops 55 AU, 55 CBO, 55 CBA and ^r 55 CBT controlled by the central pulse distributor.

Call memory read commands

When executing call memory read commands, the response contains a data word

ίο 24 bits, an all-seemingly good signal and a synchronization signal, which occur as pulses with a length of ' ¹ Zs μεεο on the call memory response bus system 6501. The word with 24 bits contains 23 information bits, which are to be used for data processing within the central controller 101, and a data parity bit. The chat log reply signals appear in parallel at the input terminals of the chat log reply bus select gates 1300. The gates 1300 are selectively energized to receive the reply from the "O" bus 6501-0 or from the "1" bus 6501-1. The excitation of the gates is determined according to the setting of the state and path flip-flops controlled by the central pulse distributor.

The information received from the data buffer register 2601 and the special flip-flops 1313 and 1314 is single-track. Therefore, the data buffer register 2601 and special flip-flops 1313 and 1314 are reset prior to the time the information is received. The energization of command line conductors 26 REBR and 26 REBRP resets data buffer register 2601 and a signal on command line conductor RECER resets special flip-flops 1313 and 1314.

Call memory error indicator circuit 2200

When data is obtained from the conversation memory 103 on the basis of memory read commands, the DA parity generator 2609 is used to check the parity of the received data and the address transmitted to obtain this data. The status of conductor 2418 indicates the parity of the code address with 18 bits, and the content of the data buffer register 2601 with the 24th bit provides the remaining input signals to the DA parity generator 2609. The parity of the returned data including the address used to obtain the data should be odd. In the event of a parity error, a signal is transmitted on the PF conductor 2607 to the call log error indication circuit 2200.
The call log fault indicator circuit 2200 sums the assembly tests performed in executing call log commands. The inputs to the chat memory error indication circuit 2200 are provided on the chat memory sync signal conductors CSS 1 and CSS 0 to the chat memory all-bill conductors ASWCSO and ASWCS1, the parity error conductor 2607 and the command wire conductors CSCK READCK . The call log error indicator circuit 2200 is actuated by a signal on the command line conductor CSCK, and when a parity check of a data reading is to be performed, the command line conductor READCK is also energized. If one or more of the above

If the assembly test fails negative, the call log fault indicator circuit 2200 energizes the output conductor CERI. A signal on the CERI line sets the C&E / flip-flop 2201 which then energizes the memory re-read sequencer 5700, the function of which will be described later. The AND gate 2700 is energized by a signal on the command wire conductor CSX and transmits the error indication on the conductor 22 CERI to the

Cross-connection of error signals in the
central control 101

speech memory commands excited. It is used for maintenance, control read and control write commands not aroused.

Auxiliary buffer register storage instructions

Memory read and write commands can also be a selected one of the auxiliary buffer registers, such as DR 0 (3118),

The central controller 101 is duplicated, 5 and at each point in time there is one of the two units referred to as the "active unit" and the other as the "reserve unit". The active unit leads the all call processing and most of the maintenance program sequences. That other central control. The call memory io means that in most cases the control of the Error indicator circuit 2200 is used for normal telephone switching systems on the execution

of program sequences within the active control unit is based. It is possible that the reserve central control unit executes the same program sequences, but does not transmit any CPD commands or network commands and therefore has no direct impact on the operation of the telephone switching system. If there are difficulties operating the central Data processor 100 by one or more

Address ARO (3105), DR 1 (3617) etc. In such cases, the DAR word is a code address which, if remedial maintenance programs are required, corresponds to the selected auxiliary buffer register. These changes, in which it can be shown that the difficult code address appears in the index-adding report within the active central control unit output register 3401 and is used to transfer data. If this is the case, the emergency measure "switches" the data buffer register 2601 to a selected one of the sequence circuit 5702 or a program sequence carried out in the active auxiliary buffer register for data write commands to the central control

the units around. That is, the active central control unit is made the backup unit, and the backup control unit becomes the active unit at the same time. This switchover takes place via a CPD command which switches the CPD-controlled status flip-flops 55AU in both central control units at the same time. The state of this flip-flop brings the associated central control in

the generation and transmission of "commands" affects the reserve or active state. An active central control is switched to the reserve state by feedback to the central pulse distributor 143, the adjustment of the flip-flop 55 AU. In the absence of malfunctions, the different, duplicated units (the central controller 101, the program memory 102, the conversation memory 103 and connecting address and response bus systems) can be put together in two separate or partially shared duplicates of a central data processor to transmit the impulse distributor 143 are. These will be. The active central control unit is the core. Errors are referred to here as »CPD commands«, an »active central data processor«, and the and the commands assigned to these commands, central reserve control, are used in the »reserve are referred to as» CPD commands «. Other data processors «. The duplicated central command commands generate information on the data processor are more advantageous in the system-network command bus 6406. These 50 are used in two ways. The first type is called "network command commands", and operates the duplicated data processors in the generation of information on the network "lock step". This means that the active and the re-command trunk 6406 are referred to as “network serve data processors carry out the same pro commands”. Network command program sequences (from the same or duplicated sample commands are used to transfer information 55 gram storage units), read and write not only to the switching network 120, but also data (from the same or duplicated calls to all units used to the central control storage units ), but only the active central station 101 via the network command collection data processor controls the central pulse distribution line 6406, such as the ler 143 and the network command units. In the case of the main scanner 144, the teletype unit 145 etc. 60 of the second operating mode, the active control center carries out program sequences for the sake of simplicity , while the reserve data processors are called "network command units". The network carries out diagnostic tests using the plant command command, uses the CPD command 65 from other program sequences and only with not used to designate a specific network-common units of the duplicated central command unit that respond to the network command to the data processor.
should speak. In the first working method, the double is off

carry or data from a selected one of the auxiliary buffer registers to the data buffer register 2601 for To transmit memory read commands.

Message traffic with the help of command commands

The third main type of message traffic is

medium network 120, the main scanner 144, etc. These commands are used to control the aforementioned Units used in both performing telephony and maintenance functions.

The central controller 101 uses program commands, here called “command” commands, for generation such commands. Certain of these commands are referred to here as "CPD" commands,

39 40

Execution of program sequences within the central or when executing CPD commands and / Data processor 100 uses this information in order to detect the occurrence of or a network command Disturbances transmitted by a periodic comparison of to the second central control unit strategic data processing hubs. For the complete production of the »transverse two central control units. (With 5 binding «a similar information transfer occurs Embodiment are two word pairs supply from the second central control unit compared in a cycle of 5.5 μεβΰ.) The first unit takes place.

Identical nodes contain the uncovered cross-connection of fault information

Collecting line 2014, the concealed collecting line only makes sense if the two central

2011, the index adding output register 3401 and io controls are running in lockstep. When the zen

the data buffer register 2601, the program-independent data processor from independent programs

address registers 4801, which carry command word buffer registers, no comparisons are made. at

2410 and sequential circuit checkpoints. this independent way of working are of a central

If malfunctions in one unit of the central control unit are transmitted to the other,

Data processors occur and a change in the 15 information information is irrelevant and must be disregarded.

Effect data processing, this change leads to remain tet. This is done by setting the CPD

to a mismatch of two deflated status FIip-Flops 55 DI reaches that,

speaking nodes in the doubled zen - as described later, the cross-connection

central data processors. The display of non-switched.

Correspondence leads to a level C maintenance 20 The module tests of program or interruption and to program sequences that include data words that are directed by the central controller 101 that they determine the malfunctioning unit. can be read from the program memory 102. It should be noted that this comparison method can only be used in the error display and correction circuit if the duplicate program sequences are carried out in the 2400. Check-in-step will also be carried out there. This means that program words from the conversation are generated by a pro memory 103 during a lagging execution. If a correctable sequence is indicated as being non-error compared to its counterpart, a signal will appear on the 1-cores of equal nodes on rectifier wire 2420. If an error requiring re-reading due to different data processing steps is indicated, a signal is occurring and not due to disturbance. That 30 on the 1 re-reading lead 2421.
would lead to a level C maintenance interruption. A signal on conductor 2420 represents the 1-Correction and on to the above-mentioned program correction flip-flop 2312, and a signal follows on the conductor. Not only are these measures unnecessary, the 1 re-read flip-flop 2313 a. The flip probes can also lead to a longer interruption of the conversation of assembly tests within the central processing, which is disturbing for the subscribers Flops 2312 and 2313 show the negative result, only to be carried out in order to control unit. The setting of one or more comprehensive program sequences after one of these two flip-flops does not exist leads to one of them looking for a fault. Signal via the OR gate 2317 and the

As noted above, some or all of the error display and correction scarf conductors 2322 are dependent Transmission loops between the two 40 device 2400 is transmitted, which then generate signals from the central control units and two or more, leading to the necessary correction or ren units in the program memory 102 and / re-reads.

or the conversation memory 103 is present. There are signals on the conductors 2420 and 2421 but it is possible that an error in one of these loops occurs via the AND gates 2302 or 2303, but not a corresponding error in 45 signals on the command cable conductor 23 PSX during the the second loop. For example, a central control unit 12 T 14 of the cycle of 5.5 seconds can carry an error when reading, in which the reading of the program memory of program words or data is determined and checked. These signals are thereby rendered as the second unit contains a valid program or V2 μββΰ long pulses via the cable driver 2304 data word. In such cases a zen- 50 and 2305 and the bus 2300 to the remote data processing unit adds one or more ren central control units. The collecting cycles of 5.5 μ% & ο in order to correct the program or line 2300 in each central control unit or read the data word again. To bus 2301 in the other central control the two program sequences to enable the unit. The V2 μβεϋ long signals that keep corresponding comparisons in step, the second 55 to the conductors 2420 and 2421 in a central control unit must also be generated one or more cycles unit, occur on the bus of 5.5 μεεΰ insert. The two central data 2301 of the other central control unit are processed by the "cross connection" of are kept in step with error information via the cable receivers 2310 and 2311 zen- 60 2314 and the E-new read flip-flops 2315 transferred, central data processors due to assembly The setting of one or the other of these two pen disruptions are initiated, which causes a signal via the OR in one of the flip-flops -both central data processors was found- gate 2317 and the conductor 2322 to the error. This means that if a negative display and correction circuit is found, 2400 is given. In this way, errors that occur when reading tests in a central control unit when reading program or data words from the Prolesen or writing words into the program memory 102 or from program words from the program memory 102 or the conversation memory 103 the conversation memory 103 in a central control

41 42

unit to the other central 2205 to the head PUEE. If the flip-flop controller transmits so that the program 55 DI is not set, the signal on PUEE memory-correction-reread sequencer 5301 or through AND gate 5218 to the setting in the call memory sequencer 5302 is passed to the maintenance interrupt source flip -Flops in both units the; same number of machi- 5 52PUEE transferred. The setting either inserts number of cycles and thus the program execution 52PUEI or 52PUEE leads to a level F Warrung keeps in step. processing interruption and interruption program - If the duplicated central data processors follow, which carry out difficulties in the transmission of different program sequences, CPD commands or network commands must first see the flip-io in both central control units.

Flop 55 DI can be set. Then a continuous The command WV energizes either the output

ierliche signal on the instruction cable Dl lead to the AND gates 4701 to 4715 act accordingly and is via the OR gate 2316 to the reset inputs of the ^ correction and DAR word generated when this command is executed. The DAR word is carried by the Index E reread flip-flops. This reset 1.5 adding output register 3401 via the cover and signal covers all of the error signals emitted by the other central complementary circuit 2000, the conductor 2017, the control, so that the insert cover circuit 2109 and the OR gate error display and correction circuit 2400 to 2106 transferred to the data buffer register 2601, does not respond to extremely generated disturbance signals. The transmission through AND gates 4701 bis

A similar cross-connection is made for reading 20 4715 with the aid of a signal on the command or writing data from or into the cable controller WV. The signals at the output of this speech memory 103 are present. In this case, gates are used to carry out test functions, the negative results of assembly tests through the transmission of maintenance signals both in the call memory error display circuit 2200 within the central controller, which sum up the WV and occur as signals on the CERI output executes, as well as to the other central output conductor 2220, which sets the CSEI flip-flop 2201 control and to the network command units and uses the AND gate 2700 and the.

Cable driver 2701 to bus 2706 via signals in bit positions 6, 8 to 11, 13 and 14

will wear. The bus line 2706 in each zen lead to V2 μβεο long pulses that are sent to the remote control unit with the bus line 2208 30 ren central control via the cable 4723, which is connected to the other central control unit. This will be transmitted to cable driver 2701 and cable 2706 in the form of a V2 ^ sec pulse. The cable 2706 is connected to the cable 2208 in the AND gate 2700 of a central controller and the other central controller. Consequently, the call log error signal testified that these signals are received in the cable receivers 2205, cable receivers 2205 of the other central control 35 and other points within the range to the CERE conductor 2212 and to the setting up their central control via the conductors 2218 and input of the CSEE flip-flops 2202 transmitted. The 2219 and the cable 2221 are fed. Similar adjustments to either the CSEI or CSEE flip bindings are made by the second central controller. Flops means that a signal is established through the OR to the first to transmit a two-way transfer gate 2203 to the conductor CER. 40 using the WV command. A signal on the lines CER leads to the CER- Certain of these cross-connected signals are stimulated by the call memory-reread-sequence circuit- but only transmitted from the active central control to the device 5700. Reserve central control. If the loading

The setting of the flip-flop 55 DI leads to the failure of WV executed in the reserve central control that a signal occurs continuously on DI and 45, the internal functions specified by this command via the OR gate 2209 to the reset input are carried out, but the corresponding CSEE flip-flop 2202 is given. The incoming cross-connection signal is blocked. The setting of 55DI switches off the cross-connection of the signals for which this restriction applies, the call log error information. on the ladders ISTBY, MSRS, ISTBY-ST,

As part of the execution of CPD commands 50 ISTBY-RS, IESTOP and IFSTOP. These signals and network commands are also transmitted via the AND gate 2707, the connection of information with regard to negative in the active central control provided by a signal on the results of assembly tests. the command wire conductor AU is energized.
These commands and the assembly test signals in one or more of the bit positions

are executed under control of the command command 55 7 to 9, 11, 12, 15 to 18 generate V2 μβεΰ long Im sequential circuit 4902. After completion of the pulse signals to carry out various gate functions within a CPD command or a network command of the central control, the mandos are all negative outputs from the construction VW command. The individual gate function group tests in the form of a ¹ It μεεϋ long interior are carried out in the following way:
pulses summed up on the command line header 60 " _cc

PUEI occurs and via the collecting line 5205 with ^{ISTBY 5 Mb> RS}

the setting input of the maintenance interruption A signal on this line in the active

source flip-flops 52 PUEI is connected. The same central control energizes the command wire conductor

The signal is sent via the cable driver 2701 and the MSRS in the reserve central control. This

Bus 2706 to the other central control 65 signal is sent via OR gate 6104 to the transfer unit. The signal goes to the collective reset input of the millisecond clock source

line 2208 of the other central control unit and 6101 transmitted to the phase of this clock source

readjust within this unit by the cable receiver.

IACT MS RS

IESTOP IF STOP ISTBY-ST

f * ^d ?

A signal on the IACTMSRS line in the active central controller energizes the command wire conductor MSRS to re-phase the millisecond clock source 6101 in the active central controller. "

c ^ f7ftS CSPSRESET and CSRSRESET

around the command word buffer register 2410, the command word register 3403 and all subsequent circuits Än ^OFF T ™ ^ l ^S ^ ^art ; ^Sto PE ° ^gesc i ^a \ T ^{g 4} * Z ^m * of the emergency measures follow-up formwork

5702 in the reset or inactive state or to leave it in this state.

OLIR and OL 2 R

An excitation of this line transmits a reset signal via the conductor 4731 to the flip-flops 55 OLl and 55 OL 2. If these flip-flops are set in the active central control, the transmission of CPD and network commands to the corresponding bus systems is blocked. If the same flip-flops are set in the reserve central control, this unit can send Kornmandos to the CPD selection bus <? 405, the CPD address bus system iS5 ' _n . ^the CP ^D output cable 6404, the CPD input synchronization cable 6702 and the Netewerk command busbar system 6406.

PKCKR

A signal on a chosen one of these lines causes the information not only is transmitted from the active central control to the reserve control, but causes also that the flip-flop 4725 is selectively set or reset.

A signal on this line excites the command cable conductor ADD and KLKR to the contents of the KA -Eingangsregisters ^ in the 3502 - Register ₄₀₀₁ ^ _give j _n this case generates the X-input logic 3505 the sum of its two input signals, but only the content of iL4 input register 3502 is transferred to .K register 4001 because the content of KB-Rq register 3504 consists only of zero values.

^or

IFSTOP wxrd transmitted from the active central control to the reserve central control in order to stop the processing of program commands in the reserve unit by energizing the STOP sequential circuit 4400 in this. Both signals are also given via the OR gate 4724 to the flip-flops 4725 Einstelleingangdes Accordingly serves dieJEmstellung this Fhp-flops as a display in the active central control that signals for stopping the standby central control ^sm been transferred ■

Similarly, a signal on the ISTBY-ST line in the active central control system causes a signal to "start" the standby central control to be transmitted. This signal also resets flip-flop 4725, indicating the new state of the standby central controller.

An excitation of the conductor ISTBY-RS in the active central control causes a pulse to the OG input cable conductor ^ ray- ^ of the reserve central control to be transmitted. If the standby central control gestopt "" been (ie, the stop sequence circuit 4400 is in the reserve unit excited), XLAs signal on Estby-RS excites the command cable conductors A signal on this line excites the command command sequencer 4902 to command command-gate functions to be carried out as described above.

17.18

_g . _d ^ _{DEQ Au leit the order} _

_Q J _{more 4? 14 and 4?} f _g ⁸ _stdlen ⁸ _{optionally that}

Flip-flop 4717 on or back. The 1-exhaust line MOIA of this flip-flop becomes the ^ f | _{£ for interruption of S} sequential circuit

4901 blouses, and the command W gives the possibility to set the flip-flop 4717 either on or back.

Signals on the lines HNT-O and HNT-I lead to the transmission of Va yßec long pulses to the lines EINT-O and EINT-I of the other central _{controller, and the signals there on tre} border are via the lines _{2218 and 2219 m the} transmitted flops 56CCC-O and 56 CCC-I - _{Einstellei än% r} maintenance - interrupt sources - flip. The one ^ _digser ^ _the ^ _zen _

^ control makes it is the requirement for _dn interrupt program at level G.

WV commands therefore represent a means of _{causing an interruption in the other central controller and thereby challenge the other central controller} .

_{control to} carry out certain maintenance tasks

_{as in the case of the} transfer of income

results of diagnostic tests or initiation

^ _n p _rogrammfo 1 _gen; ^P _to start or stop

Sequential stop (4400)

_{Signals can be transmitted from the active} central control to the reserve central control in order to selectively

1. to stop or start the processing of program command words in this,
2. to reset certain flip-flop registers and internal status counters of a number of sequential circuits within the reserve central control.

45 46

Comparison circuits and the maintenance decoder do not allow programs to work in any other way

(4608), or the investigation of the interior

State of the other central control in the

In most cases, the two central search for malfunctions result. The control of the Controls the same program sequences, and 5 routine comparisons and the selection of the »routine both Units carry out the same program command "Compare Operation" or one of a large number at the same time. of "maintenance-comparison-working methods" that still

Means not specified here are to be described, based on which work signals are generated and transmitted by the microsecond control register (MOCR) 4603.
the clock source 6100 of each central controller for io If a routine comparison is specified, the clock source of the other central controller is located. The two microsecond clock sources keep this additional control information in the control signals. if the comparison control register (MACR) 4103 supplies the clock pulses of the other central control unit, additional information occurs.

tion coincide. With the help of one of several the maintenance decoder 4608 receives signals from the

Programs or devices are started the two centrally mentioned registers via the connecting collective controls with the same selected code lines 4607, 5113 and 4107. Signals on the address that is entered in their program address error cable lines 4600 supply microsecond clock register. This leads to a simultaneous 20 pulses and DC control information with entry into the same sequence of program instructions. With regard to the status of the decoder and subsequent switching, each central controller then runs in lockstep. Tax information is also passed from with the other. The same data are read from the CPD-controlled status flip-flops 55 B-TST of the memories and scanners, the same and 55 V-BIT are transmitted over the lines 5501. Data processing steps are carried out, and on the basis of these input signals the Wardie generates decisions in both units, the decoder 4608 output signals on the OCG are the same. Further, when the cross-connection of cable lines 4610 is to transfer information from one fault information as described above through registers to another via the bus system shown in Fig. 67 the resetting of the disconnection flip-flop 55 DI . Furthermore, the insertion of additional cycles in the 30 output signals of the maintenance decoder 4608, occurring on program execution of a central control for the maintenance decoder cable 4609, correction or re-reading of the insertion have the following effect:
same additional cycles in the other central
Control accompanied.

This mode of operation just described is called 35 (1) creating the possibility of information in the "Lock-step mode" denotes and uses to enter comparison registers;

In order to provide a continuous assembly test of the _{(2) transfer of} information from the internal to the central controls. This test comparative busbars "0" 4900 and "1"

consists in repeatedly comparing common _34Q * _{over the} and ^^ ₂₇ 02 and 2704 too

Points in both central controls to 4 ° _{the cable drivers 2} 703 and 2705;

to enable immediate display of faults in both central controls. The repeated (3) setting of one of the maintenance-interruption comparisons are carried out with the aid of the comparative switch-source flip-flops 52MM10, 52MM11, 52BP1

gen and the maintenance decoder 4608. ^{or 52 TR} 1 depending on the used

The details of the comparison circuits in 45 Matching Operation If Mismatches central controller 101 are indicated with references or other specific states.

10 to 63 and which will be shown.

F i g. 67 explains the transfer to be compared

Information within and between the central routine comparison working method

Controls. 50

The extensive access of the comparison circuits In the routine comparison mode of operation,

In a central control, the two internal comparisons are made via the internal two 5.5 ^ sec-Z) 'klus through use-comparison busses INTMB 0 (4900) and two comparison circuits , from INTMBl (3400) and the transmission connection, each of which makes a comparison possible Machine cycle between the central controls, which can be carried out from the 55. All equal information registers AR 0 (3105), DR 0 (3118), AR 1 to be compared become one of the two internal connections (3605) and DR 1 (3617), the external comparison pass collecting lines INTMBO or INTMBl collecting lines EXTMB 0 (2210) and EXTMBl (Fig. 67) of each central controller. The in (2211), interconnecting cable drivers 2703 and information on internal comparison busses 2705, busses 2706 and 2208, and the 60 lines are passed to internal comparison registers of cable receivers 2206 and 2207. DRO or DRl (Fig. 67) and via the external

This access allows frequent “routine comparison manifolds EXTMBO or EXT comparison” of many strategic points within MB 1 to the external comparison registers AR 0 or both central controls. In addition, there will be - -. AR 1 transferred to the other central control, through the basis for an effective diagnosis 65 The output signals of the / 4i? 0- and Di? 0 comparison possibility created, which can be carried out in conjunction with pro registers 3105 and 3118 via the collective chart sequences, and transfer lines 3107 and 3119 to the "(k comparison switching control center for checking internal points generation 3122. This compilation of

Circuits and the associated transmission busses are referred to as comparison circuitry "0". A similar combination results from the AR 1 and DR 1 comparison registers 3605 and 3617, the "!" Comparison circuit 3621 and the associated transmission busbars. This combination is referred to as comparison circuitry "1".

F i g. 67 shows the points checked in the routine fitting operation. There are:

A. the uncovered manifold UB (2014),

B. the concealed collecting line MB (2011),

C. the index add output register
AOR (3401),

D. the data buffer register BR (2601),

E. the program address register PAR (4801),

F. the command word buffer register
BOWR (2410),

G. selected sequential circuit and decoder outputs EM1 (29 SEM 1).

Since only two points are allowed per machine cycle, the sequence of comparisons is in the routine comparison mode of operation determined by the comparison cycle control flip-flops 5105 and 5106 and the maintenance decoder 4608 according to the following requirements:

1. Comparison of the data buffer register and the Index add output register when a call memory write error is performed.

2. Compare the hidden buses and the index add output register, if one Call memory read command or a command command is performed.

3. Compare the command word buffer register after reading or correcting one from the Program memory 102 obtained word, if requirement 1 or 2 is not met must become.

4. Comparison of the uncovered busbars when executing jump commands (scanning each "return address" transferred to the / register 5802) and comparison of the Program address register in the first and second machine cycle after the transfer, to confirm that both central controls are transitioning to the same new program sequence have performed. If requirements 1, 2 or 3 are to be met, the comparison is made according to requirement 4 postponed.

5. If none of the above requirements have to be met, a routine cyclical comparison is carried out

carried out with a period of four machine cycles. This comparison is called the "4-cycle comparison" designated.

The requirements listed above are selected so that the following conditions are met:

Every malfunction within the central controller 101 is indicated at least at the point in time which the effect of the disturbance is transmitted to other units in the system.

Signals on the command wire ladders 4600 indicate which of the above listed requirements are to be met, and the maintenance decoder 4608 then sets or resets or causes one of the compare cycle control flip-flops 5105 (51 £ C, 51RE, 51WR and 51PU) that the comparison cycle control binary counter 5106 is reset or advanced. The comparison cycle used and the points compared are listed in the following table. In this table, the time interval for each comparison is one of the intervals 0 8, 10 T 16, 16 T 22, which are the three main data processing sections of each machine cycle. The adjustment time is provided in order to gain the timing of information related to the process that selects the comparison cycle. For example, when checking a chat memory write command for mismatches, the data buffer registers are compared during 10Γ16. As a result, a comparison of the data transmitted to the call memory 102 is carried out after it has been entered into the data buffer register 2601.

State Comparison carried out Comparison carried out State and requirement the in the comparison in the comparison Comparison cycle control circuit arrangement »0« circuit arrangement »1« Call memory 51 WR = I Data buffer register 2601 Index adding output Write command (1) (10 T16) register3401 (10ri6) Conversation memory 51RE = I. Concealed manifold Index adding output read command (2) 2011 (10ri6) register 3401 (10716) Command command (2) 51Pi / = 1 Concealed manifold Index adding output 2011 (10-16) register 3401 (10716) Program memory 51 £ C = 1 Bit 19 to 0 of the command Bit 20 to 43 of the command reading corrected or word buffer register 2410 word buffer register 2410 reread (3) (10-16) (10-16) Jump the program Resetting the Program addresses Uncovered collection control (4) Comparison cycle control register 4801 (10 T 16) management 2014 (OT 8) Binary counter 5106 and Start of the 4-cycle equal (51MC0 = 1)

709 537/330

(Continuation of the table above)

State Comparison carried out Comparison carried out State and requirement the in the comparison in the comparison Comparison cycle control circuit arrangement »0« circuit arrangement »1« First cycle of the Resetting the Program addresses Uncovered collection ^ -Cyclic comparison (5) Comparison cycle control register 4801 (10 Γ16) management 2014 (0 Γ 8) Binary counter 5106 and Start of the 4-cycle ver equal (51MCO = 1) Second cycle of the Advancing the counter Program addresses Uncovered collection - ^ - cycle comparison (5) in the second state register 4801 (10 Γ16) management 2014 (16 T 22) (51MCl = 1) Third cycle of the Advancing the counter Concealed manifold Selected decoders and 4-cycle comparison (5) in the third state 2011 (10-16) Sequential circuit (51 MC 2 = 1) Outputs (10T16) Fourth cycle of the Advancing the counter Concealed manifold Additional chosen ^ • cycle comparison (5) in the fourth state 2011 (10-16) Decoder and subsequent (51MCO = 0 circuit outputs 51MC1 = 0 (10 Γ16) 51MC2 = 0)

As indicated above, when the two central controllers are in lockstep, different program and call storage units and different buses are used in most cases to transfer information between the central controllers and the program memory 102 and the conversation memory 103. For example, if a central controller receives a garbled reading from memory, both units will employ the necessary number of correction and / or re-reading cycles to keep the two central controllers in step. Although the first reading may be different in the two central controllers, the remedial action should result in matching readings. Therefore, the display of transmission disturbances of this type in the central data processor 100 not only initiates the necessary remedial action, but also blocks the routine comparison mode of operation until a new reading or re-entry is achieved until the required module tests have been passed. If the repeated attempt turns out negative, the routine comparison is still blocked by the resetting of the CPD-controlled state flip-flop 55 V-BIT. This gating function is carried out by the program memory correction reread sequencer 5301 or the conversation memory reread sequencer 5700 if one of the two sequencers detects an error in the execution of a repeated store command.

Each comparison status is displayed on the / 4M0 conductor 3123 or the / 4M1 conductor 3622. When using the routine comparison mode of operation, each comparison is queried by checking this ladder. A mismatch indicated by energization of the v4M0 conductor 3123 or the / 4M1 conductor 3622 results in the setting of the maintenance interrupt source flip-flops 52MM 10 or 52MM 11. The setting of these flip-flops results in a maintenance interruption at level C and an entry into the corresponding program sequences that determine the type of fault and also determine whether one of the two central controls has a circuit fault.

Selection of comparison working methods
30th

The comparison operations include the routine comparison operation and a variety of maintenance comparison operations that correspond to the contents of the operation control register 4603 can be chosen.

Directed comparison working method

Directed comparison operation can also be used when the central controls run in lockstep, and produce a repeated comparison of one or two chosen ones Points determined by the state of the comparison control register 4103.

maintenance

A commercial telephone switching system is judged on the satisfactory service of the participants and based on economic considerations. The one chosen as an example Data processing system contains many larger elements or subsets, and in general will be these larger elements or subsets of the system simultaneously from a large number of participants and the maintenance functions of the system. Accordingly, a malfunction in one of the major elements or subgroups result in a complete system failure or a serious one Result in impairment of operation.

In known electromagnetic telephone switching systems, such as coordinate selector systems, is a variety of control circuits, d. H. Markers, available in large enough numbers to meet traffic requirements the switching center to suffice. Each marker is made up of a large number at the same time used by subscriber and trunk lines. With such arrangements, however, every mar-

kier service every subscriber line or connection line, and the failure of a single marker or a relatively small number of markers in the group only leads to a reduction the traffic capacity of the system, and such a degradation does not cause the failure of the Systems.

Satisfactory service to the subscriber requires that conversations be correct and without excessive Delays are processed. Furthermore, there must be a commercial telephone switching system be continuously operational during all hours of the night and day.

Before a description of the measures that are envisaged in the present case, in order to obtain a satisfactory Achieving the service of the participants in an economically viable system is necessary define a number of terms that will be used in the following description should:

The expression "reliability of the system" used here is a measure of the ability of the system the correct implementation of the assigned functions (both call processing and maintenance) to continue even if component and system subgroup failures occur.

The term "maintainability" used here is a measure of the ease with which failures components and sub-assemblies of the system can be viewed, examined and repaired.

Operational safety of an individual part, d. H. of a component (as opposed to a subgroup of the Systems), is a measure of the likelihood that the component will perform a certain function for a required Time span met without failure.

The reliability of the system requires that even if there are failures of components and Subgroups in the system show the presence of such failures operating a subscriber not touched.

Maintainability directly affects profitability a switching system because a system that is easy to maintain is a minimum of operating staff required. In addition, the maintainability is directly related to the reliability of the Systems together. That is, if a system has a high level of maintainability, those are Components of the system and its sub-groups only out of operation for very small times, and it was recognized that the downtime of subsets of the system must be very small when doubling the institution should be effective. That is, statistically two subsets of the system at the same time or fail within an extremely short period of time. Hence it is great Meaning that if an error of a subgroup has been detected, this error is eliminated and the Subgroup of the system is made ready again to provide effective redundancy of the subgroups to contribute.

The reliability of the system described here is economical by a number of Measures have been achieved which will now be described. Some of these measures are Similar to methods used in known systems. As can be seen from the following description results, even where similar measures are used, there are improved methods of implementation these known measures have been developed.

The first and easiest measure to achieve reliability of the system is redundancy or duplication of subsets of the system. As in any telephone switching system, there is one some redundancy or duplication of equipment inherently in subsets of the system available. For example, a telephone switching system inherently provides redundancy both in the switching routes that serve the individual subscriber lines, as well as in connecting lines and control circuits which are always provided in groups so large that they meet the traffic requirements of the system.

Note that, as with other telephone switching systems It is customary for facilities that are individually assigned to a participant not to be duplicated, as this would fail Facilities only touches the operation of a single participant. Besides, the devices are that only are available for each participant, are generally extremely tough and reliable and therefore do not pose a difficult problem in terms of the reliability of the system represent.

In the embodiment described here, entire subsets of the system or parts of Subgroups doubled to create a reliable system. The following explanation is a summary of the various subgroups of the switching system as an embodiment of one Data processing system and the duplication used with respect to each of these subsets of the system dar:

1. Central control 101. The central controls are always available in pairs. In addition, the more important input and output message transmission paths (bus lines) are doubled, and provision has been made to switch between certain doubled bus lines within a basic cycle of 5.5 μ5 & o.

2. Program memory 102. Program memories are semi-permanent according to the required Storage capacity of the system provided. However, there are always at least two program memories used in a system to have duplicate copies of the information stored. Also, as in the Central control case, both the inbound and outbound communication routes (the busses that connect the program memory to the central control) doubled, and there is precaution taken to quickly switch between both input and output busses can.

3. Call memory 103. The number of call memory used depends on the required, temporary caching in the system. However, there will always be at least two call memories are used in one system, and without the occurrence of malfunctions are all stored information is duplicated. Also, both the entrance and

53 54

the output message transmission paths combine one of the two transmission paths of a pair of

double. doubled transmission paths without switching delay

4. Network units. Include the network controls.

and monitoring units include the network in addition to the redundancy of equipment plant control devices 122, 131, the network output 5 is in the execution button according to the invention 123, 127, 135, 139. And the network game uses a number of other measures to Signal distributors 136, 140. The network control, reliability and maintenance devices are paired to enhance this ability of the system. These measure pairs are each relatively small - can be divided into two large classes, assigned to a section of the network. One io each of which has a number of subclasses on the control unit a couple controls normally assigns. The two classes are (1) assembly dimensions approximately one half of the network measures assigned to it and (2) program measures, work section, while the other control both classes include tests of equipment device of the couple usually the rest of the genes that provide fault indications, and as well Part of the network section controls. For a 15, both class remedial steps include such Failure of one unit of the pair can, however, be calculated that a system also exists if the other unit to control the whole, its a fault remains in operation. The program assigned Network part used measures still contain measures that are. not just failures on a particular system or

20 subsets of the system, but rather

The way in which the doubled also includes a failure within a subset of the The system's facilities are brought into operation. The system is precisely localized. These individual prods, differs in an advantageous manner essential grammatical measures have a direct effect on the warlich based on the functionality of the system used in known systems and thus as above Orders. In known telephone exchange 25 explained, indirectly on the reliability of the system, systems and data processing systems are because of the fast localization of malfunctions duplicate subsets of the system in general for quick recovery provided as operational and reserve units, and in this way duplicated subsets of the system these subgroups are either with the help of for a high percentage of the time the operation Manual switches or multi-contact relays are available at the Un- 30.

Subgroups of the system are switched on or the assembly tests are separated from them. Such arrangements have been prescribed for the various subordinates System unsatisfactory because they are used to switch the system, and it was between the subgroups of the system of notes that program reviews are also used for Naturally the time required for the practical loading of faults can be used. Assembly drive is too long, as not only the data processing checks and program checks lead to overcapacity or show the traffic capacity of the system, called the »indicated fault«, is significantly reduced, but also a loading The processes involved in by assembly tests Significant loss of important, temporary and program checks indicated malfunctions and input data can occur. For example, if 40 are taken, they are completely different. Both however, the dial pulse or burst tone scanning as long as events meet at the point of is interrupted that a switchover from Un- sequence, where a jump to a non-displaceable subgroups of the system is done by hand with the help of a re-error detection program, lais is possible, conversations are garbled, and if the indicated disturbance is the operation of a the service to the participants is unsatisfactory. 45 call memory 103 or a program memory If a switchover of subgroups 102 is concerned, a “retry” is popped in the system with the help of mechanical contacts called subsequent function passed over, and if a Interfering noises on the switched lines result in a retry of a successful conversation or testify that is accompanied by errors in the operation of the system program memory function will be the being able to lead. 50 active combination of the subgroups of the system, in the present system a number of d. H. the call memory, the program memory, individually assigned transmission-collective of the central controls and the collective lines, piping systems the required input and viewed as usable, and the instantaneous Output transmission paths to the various series of program functions are continued. Subgroups of the system, and this transmission 55 Note, however, that even if a Gewege are inductive to both the sources and retry speech memory or program memory connected to the burdens of the subgroups. was successful, the fact that a retry The coupling with the help of transformers causes the necessary storage and that Separation of errors of the subgroups from the large number of retries within one Transmission paths that these subgroups serve - 60 a limited period of time that leads to maintenance functions, from the connected subsystems and from which are calculated in such a way that the reason for the recurring doubled unit of this subsystem. brought conversation memory and program memory as well enables the use of an in-read mistake or call memory write mistake Coupling of the transmission paths is found differently. When the conversation memory denen Subgroups the system made a particular 65 or program memory retry unsuccessful The transmission route without any switching delay is labeled a route leading to the warning to address, and enables the addressing function to result in an interruption Subgroups of the system, commands via source flip-flop is set. Same radio

55 56

tion is carried out when the displayed malfunction is limited to the elimination of the faulty Call memory or program memory subgroups of the system from the active communication was. It is used to serve a variety of interruption combinations of subgroups. The first radio source flip-flops and these flip-flops are non-deferrable error detection the various sources of interference individually 5 program is the determination of whether the indicated assigned. Disturbance represents an error or an error.

The setting of an interrupt source flip- When the fault occurs with the help of the error detection flop energizes the interrupt follower circuit 4901, program cannot be reproduced, the the failure indicated the interruption of the current pro-viewed as an error, and that The program sequence and the storage of data from the io system returns to call processing. before however, a number of registers of central control will return to call handling a record is made in a reserved area of the call log indicating that a 103 causes. This data retention error occurred because this information is required in certain cases a subsequent return is borrowed to determine if there is a high number of goings-ons to the interrupted program, if a 15 tümern occurs or not. As can be seen from the above Such a return is both easy to carry out and yields, whenever an error occurs, is also advisable, and in other cases provides information required, about an error detection program mations that are to be skipped in the course of the error detection program, and this jump sets the grams can be of use. call processing capacity of the central control

If the set interrupt source flip down 20. Therefore, a large number of decreases

Flop indicates that the fault in one of the elements erroneous the effectiveness of the central data management

of the central data processor 100, namely worker 100.

the central controller 101, the program memory If the error detection program the indicated

102 or the conversation memory 103, the emergency display can reproduce fault, it is

measures-40-msec clock circuit in the immediate tester 25 to an error, and the error detection pro-

5703 energized before a transition to the error gram proceeds to set the error to a sensitive

recognition program takes place. If the set agreed to isolate subset of the system. Man

Interruption source flip-flop a malfunction. Note that the error is either in the active or in the

shows that are not found in the central data processor 100 of the reserve subgroup of the system

is, the transfer takes place on the error detection 30 can and that various program functions

program immediately without excitement of the emergency measures required to process the call

Clock circuit. Regain system. If the error is in a

If the indicated fault is either in the central controller 101, a call log entered controller 101 or in call memory 103 103 or a program memory 102 occurs there is a jump to the error detection 35 only for a limited period of time (40 msec) for the program that is in the program memory 102 error detection program available to the finds. However, if the fault indicated in the Pro error is limited to a certain subgroup memory of the program 102 lies, measures will be identified. If the error detection program corrects the mistakes, to the central controller 101 with the help of a ler not within the prescribed period of time To operate a program that is in conversation memory 4 ° on a certain subgroup of the system cup 103 is located. and it is known that the error is in

That is, if there is a fault with respect to one of the central controllers 101, the conversation memory

Program memory 102 is displayed, it appears 103 or the program memory 102 is located, stores

not expedient, the execution of an error- the error detection program a request

recognition program to try to run on a 45 for the subsequent initiation of a postponed

from a program memory 102 derived Infor error detection program that the error to a

mation is based. Therefore a relatively short-term subgroup is restricted and then classified

zes error detection program from the conversation - the error detection program that cannot be postponed

memory 103 won. The call memory fault - the compilation of the components of the central

The recognition program sequence is generated by arousal 50 data processors with reference to the subset of the

of the call buffer sequencer 5302 system, i.e. the central controller 101, the

initiated. Call memory 103 or the program memory

If a malfunction is detected with the help of program checks that have shown an error,
If the error detection cannot be moved to the error detection program, which is indicated by the 55 program, the error is displayed on a specific malfunction. It is not a group of the system is restricted, it must be determined that an interruption has to be initiated, such as whether the subgroup has failed in the active or in the case of a combination of components serviced by an assembly test and a malfunction was required. appropriate measures must then be taken

The error detection programs are in the 60s. If the active unit fails, it switches

system has the highest execution priority, program the reserve unit in the active combination

since they are used to reclaim the call storage nation of components, since this change is used for

processability of the system are provided. Regaining the ability to edit

The error detection programs are, however, required by the system.

kept as short as possible to avoid an interruption of the 65 After a faulty subgroup in the re-

Avoid call processing and are switched to the service state or after

Steps that the faulty subgroups of the Sy- has been determined that a reserve subgroup

isolate stems, and the required control function is faulty, actuates the error detection pro-

57 58

gram error-indicating flip-flops within the points within the level H program, des

faulty subgroup or relocated in the case of the level / program or the basic level execution

a network control device 122, 131 or a security program to handle the call

gnalverteilers 128, 136, 140 to set the faulty sub-unit in motion. If it is found that

group into a quarantine operating state. 5 it is possible to access the interrupted program

In addition, the error that cannot be postponed is marked - the return sequence is used to return

detection program a flag in the dem 5300 energized, which with the help of pre-wired switch-

call processing started again when the error detection program assigned to it was pushed

Working supervisory register, the task of which it sets.

is to determine the malfunction within the faulty sub- io An example of a situation in which it is the purpose of the system. is moderate to return to the interrupted program-After the call processing ability of the is then given when it is determined that a reserve subgroup of the system is failed-reordering of element assemblies of the len with the help of a system according to the program. Then no corruption of data central data processor 100 either to reform 15 or misleading or misinterpretation of Systemkomgistrierung the request for a shifted mandos is possible. An example of a state, in the case of an error detection program or after which it is not advisable to revert to an interrupted program sequence of the error to a specific subgroup, is given when it has been recovered, the error detection program has established that an active one Central control frame the emergency measures 40 msec clock circuit 20 tion has failed. Then difficulties 5703 can return. This had been excited after it was determined on the exact return to the interrupted one that a disturbance existed, the program occurred. If the transition from one of the elements of the central data processor concerns an error detection program to the call processing 100. If the call processing capability is regained with the help of the restart program instead of with the speed of the system before the expiry of the clock circuit 25 with the help of the return sequence circuit 5300, 5703 , the program carries out certain emergency functions similar to those carried out on others Place described, the sequential circuit 5300 on a wired basis, to a program interruption at level B That is, the interrupt activity flip-flop and successive rearrangements of the is reset, and the program determines central controller 101, the program memory 102 30 then a suitable reference point in one of the pipes and their connecting manifolds. Call processing levels H, J or L to restart the call processing if the emergency measures 40 msec cycle. The program gives the code address of the reference point and the error detection program jumps into the program address register 4801 and goes to a »restart program«. The Restart-Pro- 35 then click on the program,
In accordance with prescribed rules, the program determines whether it is expedient and advisable to recover the conversation and not to return to the interrupted program on the reference point. If the return to earlier operations is required, such as where the interrupted program is not advisable, the case when the restart program is reverted to an interrupted program sequence selects one of several reference 40s.

In addition 24 sheets of drawings

Claims (6)

Patent claims: 1. Program-controlled data processing system with a large number of memories, a control arrangement with a first and second control, which are functionally equivalent, and a transmission arrangement connecting the memory to the control arrangement, with an input-output arrangement connected to the controls and responding to their commands and with circuits which block the transmission of commands from a selected controller to the input-output arrangement, characterized in that the transmission arrangement (6400, 6500) has a plurality of independent transmission paths (6400-0, 6400-1, 6500-0, 6500- 1), each of which, depending on the state of register circuits (Fig. 3: 300, Fig. 55: 5500, PBA, PBO, PBT) optionally with the first and second control (CCl, CC 2) and depending on State of further register circuits (Fig. 5: 501), which are each assigned to individual memories, optionally connected to the memories (PS1, PSN) n, and that the connections established in this way form at least one operating combination that includes a controller (CCl or CC 2), a transmission path (6400-0, 6500-0 or 6400-1, 6500-1) and at least one memory (PSl to PSN) . 2. Program-controlled data processing system according to claim 1, characterized in that the controls (CCl, CC 2) and the memory (PSl to PSN) are connected as signal sources in parallel and as signal consumers in series on the transmission paths (z. B. 6400-0) . 3. Program-controlled data processing system according to claim 1, characterized by circuits which ensure the simultaneous execution of identical work functions by the first and second control (CCl, CC 2) and contain the following components: in each control (CCl, CC 2) audit circuits (Fi g. 4: 460), which check the operations of parts of the control system and the correctness of information read from the memories and generate fault signals whenever a fault indication occurs; Circuits (e.g. the cross-connection fault circuit according to FIGS. 22 and 23) for transmitting fault signals to the respective other controller and register circuits (Fig: 23: 2314, 2315) in each controller for recording the fault signals and circuits transmitted by the other controller (462) in each controller, which carry out identical control measures due to fault signals from both controllers. 4. Program-controlled data processing system according to claim 3, characterized in that the memories (PSl to PSN) have operational check circuits (F i g. 7) which check the internal operation of the memory and generate a test signal and transmit it to the controller that corresponds to the current Operation combination with the memory belongs, and that the circuits which ensure the simultaneous execution of identical work functions, to the test signals responsive register circuits (Fig. 12: 1213, 1214) and circuits (Fig. 24: 2400) have, which are dependent generate fault signals from the state of the register circuits. 5. Program-controlled data processing system according to one of the preceding claims, characterized in that the first and second control each have a plurality of data sources (the different registers, e.g. the BR register 2601, and other data sources, e.g. Fig. 47, which can be optionally transferred to the internal Comparison bus lines 4100 and 3900 can be connected) and that the circuits, that ensure the simultaneous execution of identical work functions, circuits (Fig. 31 and 36: 3122, 3621) contain the data words from selected data sources within of the two controls (CCl, CC 2) and generate fault signals if the compared data words are not identical. 6. Program-controlled data processing system according to claim 5, in which the programs forming commands for controlling the data processing system are divided into command classes are identified by circuits (Fig. 39: 3901, 3902, 3904) which the data sources depending on the class of commands executed.