DE3175779D1 - Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure - Google Patents

Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure

Info

Publication number
DE3175779D1
DE3175779D1 DE8181106121T DE3175779T DE3175779D1 DE 3175779 D1 DE3175779 D1 DE 3175779D1 DE 8181106121 T DE8181106121 T DE 8181106121T DE 3175779 T DE3175779 T DE 3175779T DE 3175779 D1 DE3175779 D1 DE 3175779D1
Authority
DE
Germany
Prior art keywords
conductive
substrate
level metal
interconnection pattern
superposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181106121T
Other languages
English (en)
Inventor
Joseph Skinner Logan
Iv John Lester Mauer
Laura Beth Rothman
Geraldine Cogin Schwartz
Charles Lambert Standley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3175779D1 publication Critical patent/DE3175779D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/7688—Filling of holes, grooves or trenches, e.g. vias, with conductive material by deposition over sacrificial masking layer, e.g. lift-off
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
DE8181106121T 1980-08-18 1981-08-05 Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure Expired DE3175779D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/179,145 US4367119A (en) 1980-08-18 1980-08-18 Planar multi-level metal process with built-in etch stop

Publications (1)

Publication Number Publication Date
DE3175779D1 true DE3175779D1 (en) 1987-02-05

Family

ID=22655405

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181106121T Expired DE3175779D1 (en) 1980-08-18 1981-08-05 Planar multi-level metal-insulator structure comprising a substrate, a conductive interconnection pattern and a superposed conductive structure and a method to form such a structure

Country Status (4)

Country Link
US (1) US4367119A (de)
EP (1) EP0046525B1 (de)
JP (1) JPS5745952A (de)
DE (1) DE3175779D1 (de)

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Also Published As

Publication number Publication date
JPS5745952A (en) 1982-03-16
EP0046525A2 (de) 1982-03-03
EP0046525A3 (en) 1984-07-25
EP0046525B1 (de) 1986-12-30
JPS6244812B2 (de) 1987-09-22
US4367119A (en) 1983-01-04

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Legal Events

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8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee