DE3175507D1 - Process for selectively forming refractory metal silicide layers on semiconductor devices - Google Patents

Process for selectively forming refractory metal silicide layers on semiconductor devices

Info

Publication number
DE3175507D1
DE3175507D1 DE8181104336T DE3175507T DE3175507D1 DE 3175507 D1 DE3175507 D1 DE 3175507D1 DE 8181104336 T DE8181104336 T DE 8181104336T DE 3175507 T DE3175507 T DE 3175507T DE 3175507 D1 DE3175507 D1 DE 3175507D1
Authority
DE
Germany
Prior art keywords
semiconductor devices
metal silicide
refractory metal
selectively forming
silicide layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181104336T
Other languages
German (de)
English (en)
Inventor
Joseph John Fatula
Stanley Roberts
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3175507D1 publication Critical patent/DE3175507D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H10D64/01308—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal
    • H10D64/01312—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon the conductor further comprising a non-elemental silicon additional conductive layer, e.g. a metal silicide layer formed by the reaction of silicon with an implanted metal the additional layer comprising a metal or metal silicide formed by deposition, i.e. without a silicidation reaction, e.g. sputter deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6302—Non-deposition formation processes
    • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
    • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
    • H10P14/6308—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials of Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/14—Schottky barrier contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/147—Silicides
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/911—Differential oxidation and etching
DE8181104336T 1980-06-30 1981-06-05 Process for selectively forming refractory metal silicide layers on semiconductor devices Expired DE3175507D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/164,464 US4285761A (en) 1980-06-30 1980-06-30 Process for selectively forming refractory metal silicide layers on semiconductor devices

Publications (1)

Publication Number Publication Date
DE3175507D1 true DE3175507D1 (en) 1986-11-27

Family

ID=22594608

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181104336T Expired DE3175507D1 (en) 1980-06-30 1981-06-05 Process for selectively forming refractory metal silicide layers on semiconductor devices

Country Status (4)

Country Link
US (1) US4285761A (enExample)
EP (1) EP0043451B1 (enExample)
JP (1) JPS5730328A (enExample)
DE (1) DE3175507D1 (enExample)

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US4472237A (en) * 1981-05-22 1984-09-18 At&T Bell Laboratories Reactive ion etching of tantalum and silicon
US4378628A (en) * 1981-08-27 1983-04-05 Bell Telephone Laboratories, Incorporated Cobalt silicide metallization for semiconductor integrated circuits
US4398341A (en) * 1981-09-21 1983-08-16 International Business Machines Corp. Method of fabricating a highly conductive structure
US4394182A (en) * 1981-10-14 1983-07-19 Rockwell International Corporation Microelectronic shadow masking process for reducing punchthrough
DE3211752C2 (de) * 1982-03-30 1985-09-26 Siemens AG, 1000 Berlin und 8000 München Verfahren zum selektiven Abscheiden von aus Siliziden hochschmelzender Metalle bestehenden Schichtstrukturen auf im wesentlichen aus Silizium bestehenden Substraten und deren Verwendung
JPS59100520A (ja) * 1982-11-30 1984-06-09 Fujitsu Ltd 半導体装置の製造方法
US4443930A (en) * 1982-11-30 1984-04-24 Ncr Corporation Manufacturing method of silicide gates and interconnects for integrated circuits
US4411734A (en) * 1982-12-09 1983-10-25 Rca Corporation Etching of tantalum silicide/doped polysilicon structures
JPS59129471A (ja) * 1983-01-14 1984-07-25 Toshiba Corp 半導体装置の製造方法
US4514893A (en) * 1983-04-29 1985-05-07 At&T Bell Laboratories Fabrication of FETs
US4454002A (en) * 1983-09-19 1984-06-12 Harris Corporation Controlled thermal-oxidation thinning of polycrystalline silicon
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JPS60132353A (ja) * 1983-12-20 1985-07-15 Mitsubishi Electric Corp 半導体装置の製造方法
JPS60130844A (ja) * 1983-12-20 1985-07-12 Toshiba Corp 半導体装置の製造方法
US4673968A (en) * 1985-07-02 1987-06-16 Siemens Aktiengesellschaft Integrated MOS transistors having a gate metallization composed of tantalum or niobium or their silicides
US4660276A (en) * 1985-08-12 1987-04-28 Rca Corporation Method of making a MOS field effect transistor in an integrated circuit
JPS6252551A (ja) * 1985-08-30 1987-03-07 Mitsubishi Electric Corp フオトマスク材料
JPH0616556B2 (ja) * 1987-04-14 1994-03-02 株式会社東芝 半導体装置
JPS6489470A (en) * 1987-09-30 1989-04-03 Mitsubishi Electric Corp Manufacture of semiconductor device
US4833099A (en) * 1988-01-07 1989-05-23 Intel Corporation Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen
US4774201A (en) * 1988-01-07 1988-09-27 Intel Corporation Tungsten-silicide reoxidation technique using a CVD oxide cap
JP2624797B2 (ja) * 1988-09-20 1997-06-25 株式会社日立製作所 アクティブマトリクス基板の製造方法
JPH0265695U (enExample) * 1988-11-08 1990-05-17
US5093274A (en) * 1990-02-02 1992-03-03 Mitsubishi Denki Kabushiki Kaisha Semiconductor device and method for manufacture thereof
KR950003233B1 (ko) * 1992-05-30 1995-04-06 삼성전자 주식회사 이중층 실리사이드 구조를 갖는 반도체 장치 및 그 제조방법
US5334545A (en) * 1993-02-01 1994-08-02 Allied Signal Inc. Process for forming self-aligning cobalt silicide T-gates of silicon MOS devices
KR100190105B1 (ko) * 1996-10-24 1999-07-01 윤종용 게이트전극의 제조방법 및 그에 따라 제조된 게이트구조
US6897105B1 (en) * 1998-09-16 2005-05-24 Texas Instrument Incorporated Method of forming metal oxide gate structures and capacitor electrodes
US6448140B1 (en) * 1999-02-08 2002-09-10 Taiwan Semiconductor Manufacturing Company Laterally recessed tungsten silicide gate structure used with a self-aligned contact structure including a straight walled sidewall spacer while filling recess
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KR100297738B1 (ko) 1999-10-07 2001-11-02 윤종용 챔퍼가 형성된 금속 실리사이드층을 갖춘 반도체소자의 제조방법
US6372618B2 (en) * 2000-01-06 2002-04-16 Micron Technology, Inc. Methods of forming semiconductor structures
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US7125815B2 (en) * 2003-07-07 2006-10-24 Micron Technology, Inc. Methods of forming a phosphorous doped silicon dioxide comprising layer
US7056780B2 (en) * 2003-07-18 2006-06-06 Intel Corporation Etching metal silicides and germanides
US7510966B2 (en) * 2005-03-07 2009-03-31 Micron Technology, Inc. Electrically conductive line, method of forming an electrically conductive line, and method of reducing titanium silicide agglomeration in fabrication of titanium silicide over polysilicon transistor gate lines
EP2683792B1 (en) 2011-03-11 2019-09-25 FujiFilm Electronic Materials USA, Inc. Novel etching composition
TWI577834B (zh) 2011-10-21 2017-04-11 富士軟片電子材料美國股份有限公司 新穎的鈍化組成物及方法
US8709277B2 (en) 2012-09-10 2014-04-29 Fujifilm Corporation Etching composition
US10741560B2 (en) * 2017-10-26 2020-08-11 International Business Machines Corporation High resistance readout FET for cognitive device

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GB1501114A (en) * 1974-04-25 1978-02-15 Rca Corp Method of making a semiconductor device
US4180596A (en) * 1977-06-30 1979-12-25 International Business Machines Corporation Method for providing a metal silicide layer on a substrate
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Also Published As

Publication number Publication date
EP0043451B1 (en) 1986-10-22
US4285761A (en) 1981-08-25
JPS5730328A (en) 1982-02-18
JPS6152595B2 (enExample) 1986-11-13
EP0043451A2 (en) 1982-01-13
EP0043451A3 (en) 1984-07-25

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee