DE3172331D1 - Method and device for transmitting logic signals between micro chips - Google Patents

Method and device for transmitting logic signals between micro chips

Info

Publication number
DE3172331D1
DE3172331D1 DE8181430018T DE3172331T DE3172331D1 DE 3172331 D1 DE3172331 D1 DE 3172331D1 DE 8181430018 T DE8181430018 T DE 8181430018T DE 3172331 T DE3172331 T DE 3172331T DE 3172331 D1 DE3172331 D1 DE 3172331D1
Authority
DE
Germany
Prior art keywords
logic signals
transmitting logic
micro chips
chips
micro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181430018T
Other languages
English (en)
Inventor
Armand Brunin
Hervilly Guy D
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Compagnie IBM France SAS
International Business Machines Corp
Original Assignee
Compagnie IBM France SAS
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Compagnie IBM France SAS, International Business Machines Corp filed Critical Compagnie IBM France SAS
Application granted granted Critical
Publication of DE3172331D1 publication Critical patent/DE3172331D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/018—Coupling arrangements; Interface arrangements using bipolar transistors only
    • H03K19/01806—Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/21—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
    • H03K19/212—EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
    • H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/12—Compensating for variations in line impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
DE8181430018T 1981-06-25 1981-06-25 Method and device for transmitting logic signals between micro chips Expired DE3172331D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP81430018A EP0069183B1 (de) 1981-06-25 1981-06-25 Verfahren und Vorrichtung zum Übertragen logischer Signale zwischen Mikrochips

Publications (1)

Publication Number Publication Date
DE3172331D1 true DE3172331D1 (en) 1985-10-24

Family

ID=8188590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181430018T Expired DE3172331D1 (en) 1981-06-25 1981-06-25 Method and device for transmitting logic signals between micro chips

Country Status (4)

Country Link
US (1) US4495626A (de)
EP (1) EP0069183B1 (de)
JP (1) JPS585062A (de)
DE (1) DE3172331D1 (de)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0611143B2 (ja) * 1986-08-29 1994-02-09 シャープ株式会社 通信インタフエ−ス回路
US4724340A (en) * 1986-11-21 1988-02-09 Motorola, Inc. Output circuit in which induced switching noise is reduced by presetting pairs of output lines to opposite logic states
US5063887A (en) * 1989-08-14 1991-11-12 Yamaha Hatsudoki Kabushiki Kaisha Exhaust control valve system for parallel multi-cylinder two-cycle engine
US5241564A (en) * 1989-08-30 1993-08-31 Digital Equipment Corporation Low noise, high performance data bus system and method
US5264744A (en) * 1989-11-21 1993-11-23 Hitachi, Ltd. Complementary signal transmission circuit with impedance matching circuitry
JP2902016B2 (ja) * 1989-11-21 1999-06-07 株式会社日立製作所 信号伝送方法および回路
US5498976A (en) * 1990-10-26 1996-03-12 Acer Incorporated Parallel buffer/driver configuration between data sending terminal and data receiving terminal
US5282173A (en) * 1991-05-07 1994-01-25 Sony Corporation Semiconductor memory device with high speed transmission of address signals between a predecoder and a main decoder
FR2690541B1 (fr) * 1992-04-28 1994-06-17 Bull Sa Procede d'elaboration automatique d'une representation implicite des impliquants premiers d'une fonction.
US5424653A (en) * 1993-10-06 1995-06-13 Advanced Micro Devices, Inc. Gradual on output buffer circuit including a reverse turn-off apparatus
US5874833A (en) * 1997-02-03 1999-02-23 International Business Machines Corporation True/complement output bus for reduced simulataneous switching noise
KR100272171B1 (ko) * 1998-08-19 2000-12-01 윤종용 저전류 동작 출력 회로 및 입출력 시스템과이를 이용한 데이터입출력 방법
KR100296787B1 (ko) 1998-11-06 2001-10-26 구본준, 론 위라하디락사 액정표시장치용러쉬커런트방지회로
KR100313243B1 (ko) 1998-12-31 2002-06-20 구본준, 론 위라하디락사 데이터 전송 장치 및 그 방법
JP3592943B2 (ja) * 1999-01-07 2004-11-24 松下電器産業株式会社 半導体集積回路及び半導体集積回路システム
KR100669095B1 (ko) 1999-12-28 2007-01-16 엘지.필립스 엘시디 주식회사 데이터 송/수신 방법 및 장치와 이를 이용한 액정표시장치와 그 구동방법
GB0024226D0 (en) * 2000-10-04 2000-11-15 Lsi Logic Corp Improvements in or relating to the reduction of simultaneous switching noise in integrated circuits
US7142612B2 (en) * 2001-11-16 2006-11-28 Rambus, Inc. Method and apparatus for multi-level signaling
US7113550B2 (en) * 2002-12-10 2006-09-26 Rambus Inc. Technique for improving the quality of digital signals in a multi-level signaling system
KR100546214B1 (ko) * 2003-11-13 2006-01-24 주식회사 하이닉스반도체 반도체 소자의 데이터 및 데이터 스트로브 드라이버 스트랭쓰 제어 회로
US7302631B2 (en) * 2004-07-16 2007-11-27 Rambus Inc. Low overhead coding techniques
US20060126751A1 (en) * 2004-12-10 2006-06-15 Anthony Bessios Technique for disparity bounding coding in a multi-level signaling system
US7656321B2 (en) * 2005-06-02 2010-02-02 Rambus Inc. Signaling system

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1162374A (en) * 1966-06-14 1969-08-27 Ass Elect Ind A Circuit Arrangement for Reversing the Polarity of Electrical Wave-Form Samples
SE408362B (sv) * 1976-12-29 1979-06-05 Philips Svenska Ab Sett att vid en fjerrskrivanleggning reglera strommmen samt anordning for utforande av settet
US3560856A (en) * 1966-12-29 1971-02-02 Nippon Electric Co Multilevel signal transmission system
DE1774832B1 (de) * 1968-09-17 1971-03-18 Licentia Gmbh Verfahren zur verminderung der durch die informations stroeme in einem kernspeicher verursachten verlustleistung
NL6818490A (de) * 1968-12-21 1970-06-23
NL163350C (nl) * 1971-09-04 1980-08-15 Philips Nv Matrixgeheugen met middelen voor het al dan niet geinverteerd inschrijven van woorden.
JPS579261B2 (de) * 1973-03-31 1982-02-20
JPS5260511A (en) * 1975-11-14 1977-05-19 Nec Corp Parallel transmission circuits
JPS5494812A (en) * 1978-01-11 1979-07-26 Hitachi Ltd Information transfer system

Also Published As

Publication number Publication date
JPS585062A (ja) 1983-01-12
EP0069183B1 (de) 1985-09-18
US4495626A (en) 1985-01-22
EP0069183A1 (de) 1983-01-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee