DE3162991D1 - Method for planarizing non-level silicon dioxide in semiconductor devices - Google Patents

Method for planarizing non-level silicon dioxide in semiconductor devices

Info

Publication number
DE3162991D1
DE3162991D1 DE8181109170T DE3162991T DE3162991D1 DE 3162991 D1 DE3162991 D1 DE 3162991D1 DE 8181109170 T DE8181109170 T DE 8181109170T DE 3162991 T DE3162991 T DE 3162991T DE 3162991 D1 DE3162991 D1 DE 3162991D1
Authority
DE
Germany
Prior art keywords
silicon dioxide
semiconductor devices
level silicon
planarizing
planarizing non
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE8181109170T
Other languages
German (de)
English (en)
Inventor
Narasipur Gundappa Anantha
Harsaran Singh Bhatia
John S Lechaton
James Leo Walsh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of DE3162991D1 publication Critical patent/DE3162991D1/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31051—Planarisation of the insulating layers
    • H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
    • H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
  • Silicon Compounds (AREA)
DE8181109170T 1980-12-16 1981-10-29 Method for planarizing non-level silicon dioxide in semiconductor devices Expired DE3162991D1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/217,077 US4389281A (en) 1980-12-16 1980-12-16 Method of planarizing silicon dioxide in semiconductor devices

Publications (1)

Publication Number Publication Date
DE3162991D1 true DE3162991D1 (en) 1984-05-10

Family

ID=22809590

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8181109170T Expired DE3162991D1 (en) 1980-12-16 1981-10-29 Method for planarizing non-level silicon dioxide in semiconductor devices

Country Status (4)

Country Link
US (1) US4389281A (enExample)
EP (1) EP0054164B1 (enExample)
JP (1) JPS57107037A (enExample)
DE (1) DE3162991D1 (enExample)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4576900A (en) * 1981-10-09 1986-03-18 Amdahl Corporation Integrated circuit multilevel interconnect system and method
US4511430A (en) * 1984-01-30 1985-04-16 International Business Machines Corporation Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process
JPS60214532A (ja) * 1984-04-11 1985-10-26 Nippon Telegr & Teleph Corp <Ntt> パタ−ン形成方法
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
USH204H (en) 1984-11-29 1987-02-03 At&T Bell Laboratories Method for implanting the sidewalls of isolation trenches
JPS61144639A (ja) * 1984-12-19 1986-07-02 Hitachi Ltd 放射線感応性組成物及びそれを用いたパタ−ン形成法
US4662986A (en) * 1985-06-27 1987-05-05 Signetics Corporation Planarization method and technique for isolating semiconductor islands
US4655874A (en) * 1985-07-26 1987-04-07 Advanced Micro Devices, Inc. Process for smoothing a non-planar surface
US4665007A (en) * 1985-08-19 1987-05-12 International Business Machines Corporation Planarization process for organic filling of deep trenches
US4749440A (en) * 1985-08-28 1988-06-07 Fsi Corporation Gaseous process and apparatus for removing films from substrates
US4654120A (en) * 1985-10-31 1987-03-31 International Business Machines Corporation Method of making a planar trench semiconductor structure
US5324536A (en) * 1986-04-28 1994-06-28 Canon Kabushiki Kaisha Method of forming a multilayered structure
JPS6377122A (ja) * 1986-09-19 1988-04-07 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
EP0312965B1 (de) * 1987-10-23 1992-12-30 Siemens Aktiengesellschaft Verfahren zur Herstellung eines planaren selbstjustierten Heterobipolartransistors
US4836885A (en) * 1988-05-03 1989-06-06 International Business Machines Corporation Planarization process for wide trench isolation
JPH02167671A (ja) * 1988-12-21 1990-06-28 Disco Abrasive Syst Ltd カーボン入り電着砥石
JPH04223876A (ja) * 1990-12-26 1992-08-13 Mitsubishi Materials Corp レンズ研削用砥石
DE4239075C1 (de) * 1992-11-20 1994-04-07 Itt Ind Gmbh Deutsche Verfahren zur globalen Planarisierung von Oberflächen integrierter Halbleiterschaltungen
US5275973A (en) * 1993-03-01 1994-01-04 Motorola, Inc. Method for forming metallization in an integrated circuit
JP3072876B2 (ja) * 1993-09-17 2000-08-07 日曹エンジニアリング株式会社 エッチング液の精製方法
JPH08250486A (ja) * 1996-03-08 1996-09-27 Semiconductor Energy Lab Co Ltd 半導体装置
KR100242466B1 (ko) * 1996-06-27 2000-02-01 김영환 채널스탑이온주입에 따른 좁은폭효과 방지를 위한 소자분리 구조를 갖는 반도체장치 및 그 제조방법
US7323417B2 (en) * 2004-09-21 2008-01-29 Molecular Imprints, Inc. Method of forming a recessed structure employing a reverse tone process
US7547504B2 (en) * 2004-09-21 2009-06-16 Molecular Imprints, Inc. Pattern reversal employing thick residual layers
US7205244B2 (en) * 2004-09-21 2007-04-17 Molecular Imprints Patterning substrates employing multi-film layers defining etch-differential interfaces
US20070077763A1 (en) * 2005-09-30 2007-04-05 Molecular Imprints, Inc. Deposition technique to planarize a multi-layer structure
JP4645492B2 (ja) * 2006-03-17 2011-03-09 セイコーエプソン株式会社 金属パターン形成方法
JP2010021532A (ja) * 2008-06-12 2010-01-28 Sanyo Electric Co Ltd メサ型半導体装置及びその製造方法
JP2009302222A (ja) * 2008-06-12 2009-12-24 Sanyo Electric Co Ltd メサ型半導体装置及びその製造方法
US10879108B2 (en) * 2016-11-15 2020-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Topographic planarization method for lithography process
JP2023009762A (ja) * 2021-07-08 2023-01-20 東京エレクトロン株式会社 エッチング方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3976524A (en) * 1974-06-17 1976-08-24 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
GB1539700A (en) * 1976-05-14 1979-01-31 Int Plasma Corp Process for etching sio2
JPS5456985A (en) * 1977-10-14 1979-05-08 Mitsubishi Chem Ind Ltd Gas-separaing membrane
US4307179A (en) * 1980-07-03 1981-12-22 International Business Machines Corporation Planar metal interconnection system and process

Also Published As

Publication number Publication date
EP0054164B1 (en) 1984-04-04
JPS57107037A (en) 1982-07-03
US4389281A (en) 1983-06-21
JPS637458B2 (enExample) 1988-02-17
EP0054164A1 (en) 1982-06-23

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Legal Events

Date Code Title Description
8339 Ceased/non-payment of the annual fee