DE3106359C2 - - Google Patents

Description

The invention relates to a solid-state video camera according to the preamble of the claim.

A conventional measure for detecting a signal charge, by photoelectric conversion in one Solid-state image recording device or an image sensor, which, for example, is a charge-controlled component (CCD) is used, achieved, and its derivation is used as the output signal, is intended in the following are explained.

Fig. 1 shows a circuit diagram of an embodiment of a conventional signal transmitting and Signalaufnehmerschaltung for a CCD image sensor. According to this example, the operating system for the CCD image sensor is an image transport system, and the minority carriers stored as information are formed by electrons. In the example of FIG. 1, the portion to the left of a dash line P constitutes the CCD image sensing device formed on the chip of an integrated circuit (IC), and the portion to the right of the dash line B constitutes a sample memory circuit which serves as a wave shaping circuit.

Fig. 1 shows generally an image recording device 1 and an output terminal 1 a of the output signal deriving or the receiving circuit. The image pickup device 1 has a light or photosensitive surface 2, a storage area 3 of the photosensitive surface 2, a read-out register 4 for the storage area 3 and an output gate having an output diode section 5, which is reverse biased.

The signal charge generated in the photosensitive area 2 is transferred to the memory area, such photoelectric conversion taking place in the photosensitive area 2 that the signal charge temporarily stored in the memory area 3 is transferred to the readout register 4 for each line in the horizontal direction and in time sequence via the Output gate and output diode section 5 is output. The output terminal of the output gate and output diode section 5 is grounded via a capacitor 6 and is also connected to the source of an FET (field effect transistor) 7 , the drain of which is supplied with a direct voltage E _R and the gate of which is precharged P _a (see FIG. 2A) is supplied, which is synchronized with the transfer clock for the readout register 4 . The connection point between the section 5 and the capacitor 6 is connected to the gate of an FET 8 , the drain of which is supplied with a DC voltage E and the source of which is connected to the output terminal 1 a .

Thus, in the above output signal deriving circuit, during a time interval T _P during which the pulse Pa is at a high level, as shown in FIG. 2A, the FET 7 turns on; and thus capacitor 6 is precharged to voltage E _R. When a time interval T _S during which the pulse Pa is at a low level begins, the FET 7 blocks, which is why the voltage across the capacitor 6 becomes low depending on the output signal charge. Therefore, when the voltage E _{R is taken} as the reference level, the voltage across the capacitor 6 in the interval T _{S represents} the signal level.

In this case, since the pulse Pa is synchronized with the transfer clock for the readout register 4 , as mentioned, there occurs a charge detection output voltage V Vor at which the precharge level and the signal level repeat at every single stage section of the readout register 4 , that is, in a clock interval on the capacitor 6 ; this voltage V ₀ is fed to the output terminal 1 a via the FET 8 , which forms a buffer amplifier (see FIG. 2B).

In this embodiment, the pulse Pa enters the signal path via the stray capacitance between the gate and the source of the FET 7 , so that a voltage component E _P is therefore superimposed on the output voltage V ₀, which occurs at the output terminal 1 a , as shown in Fig . 2B is shown. However, since the voltage component E _P is approximately constant, no deterioration occurs even if a signal higher than the level E _R by the voltage E _P is taken as the reference level for the signal level. Therefore, no deterioration actually occurs even if the voltage E _R + E _P , which is higher than the normal precharge level by E _P , is taken as the precharge level.

The output voltage V ₀ thus supplied to the output terminal 1 a is fed to a scan memory circuit 10 or the drain of an FET 11 for scanning. This FET 11 is supplied at its gate with a sampling pulse Pb , which leads to a high level in the signal level interval T _{S of} the output signal voltage V _O , as shown in FIG. 2C, so that the FET 11 switches through within the high level interval of the pulse Pb , whereby the signal level of the output voltage V ₀ is sampled. A capacitor 12 for holding or storing in the circuit 10 is thus charged or discharged to the signal level of the sampled signal, which is why the signal level is held or stored on the capacitor 12 . A voltage V _H thus fixed or stored on the capacitor 12 is fed via an FET 13 , which forms a buffer amplifier, to an output terminal 1 b . Load resistors 9 and 14 for FET 8 and 13 are also shown in FIG. 1.

If the charge stored in the CCD image sensing device is dissipated after being converted into a voltage in the manner mentioned, it is necessary that when the minority carrier is the electron, as mentioned, the capacitor is charged every bit. During the precharge operation, noise signals such as the internal noise of the FET 7 , the supply source noise for the FET 7, and the like are generated, and the reference precharge level fluctuates by the noise signals. Furthermore, a level N of the noise signals generated in the precharge interval is held or stored by the capacitor 6 in a clock interval τ _B = T _P + T _S , or the noise is output in the form of the stored signal. As a result, as shown by the broken line in Fig. 2B, the output voltage V _O fluctuates due to the noise, which is why the signal level also fluctuates in the interval T _S. Consequently, when the signal level portion of the output voltage V ₀ is sampled and stored only as in the conventional embodiment shown in FIG. 1, the noise component is mixed into a signal component S and therefore output as an output signal.

It is also a sampling circuit for a charge coupled device Establishment known (GB-PS 14 13 036), at which clamped a reference level to a certain level and then the respective signal component is scanned and held. By application this measure, however, there is a risk that with high probability of the respective sampling pulse Circuit output and thus a fault evokes.

There are also an image sensor and a method for Operation of this image sensor known (DE-AS 25 43 083).  In this known image sensor, one is indeed Isolation and signal amplifier stage containing differential amplifiers used. This circuit measure is sufficient however, not to ensure largely trouble-free operation a solid-state video camera.

After all, it is already a solid-state imaging device have been proposed (DE-OS 29 38 499), in which a fixed interference pattern of a so-called MOS imaging device is eliminated. It also happens an operation comparable to a subpoena; at this Circuit arrangement used, however timed in terms of sampling so that those determined by the disturbance pattern in question Faults are eliminated. However, it has been shown that this does not eliminate the disadvantages those in connection with the conventional ones considered at the beginning Signal delivery or pickup circuits have been shown.

The invention has for its object a solid To further develop video camera of the type mentioned at the beginning, that with a relatively low effort overall disturbing influence of the noise during the pre-charging operation is effectively reduced or eliminated.

The above problem is solved by the specified in the characterizing part of the claim Measure.

The invention is illustrated below with the aid of drawings for example explained in more detail.

Fig. 1 shows in a circuit diagram a conventional charge detection circuit which is used as an output signal deriving circuit in a solid-state CCD image recording device.

Figs. 2A to 2C show waveforms for explaining the operation of the charge detecting circuit shown in FIG. 1.

Fig. 3 shows a systematic representation of a signal recording circuit.

FIG. 4A to 4C show waveforms for explaining the operation of the Signalaufnehmerschaltung shown in Fig. 3.

Fig. 5 shows in a circuit diagram the essential parts of an embodiment according to the invention.

FIGS. 6A to 6G show waveforms for explaining the operation of the embodiment shown in Fig. 5 according to the invention.

A conventional circuit has already been explained with reference to FIGS. 1 and 2.

The present invention is essentially based on the fact that the noise level is constant in a clock interval τ _B and that there is no signal component in the precharge interval T _P ; it eliminates the noise by maintaining the level difference between the levels of the precharge interval T _P and the signal level interval T _S.

Before going into the present invention in more detail, reference is first made to FIG. 3, in which a signal pick-up circuit is shown which can be easily connected to the circuit part to the left of the dashed line P in FIG .

In the circuit arrangement shown in FIG. 3, the output voltage V ₀ (see FIG. 4A) derived at the output terminal 1 a is fed to a delay circuit or line 15 in which it _is delayed by t _d (0 < τ _d < τ _b ) , resulting in a signal V _{0 d} ( Fig. 4B). This delayed signal V _{0 d} is fed to the inverting input connection of a differential amplifier 16 , which is supplied with the signal V ₀ at its non-inverting input connection, as can be seen. Therefore, the differential amplifier 16 generates a differential output signal between the two signals V ₀ and V _{0 d} .

The output signal of the differential amplifier 16 is fed to the sample storage circuit 10 in a manner similar to that shown in FIG. 1. In this circuit arrangement, the sampling memory circuit 10 is supplied with a sampling pulse SP ₀ ( FIG. 4C), whose period is τ _B and which assumes the level "1" in the precharge interval T _P 'of the signal V _{0 d} , which is why the value of the output signal of the differential amplifier 16 is stored in the period T _P '.

In this case, an input signal V ₀ for the differential amplifier 16 is given by the signal component and the noise component during the precharge period T _P 'of the signal V _{0 d} , and the other input signal V _{0 d} is only the noise component, so that the output signal of the Differential amplifier 16 in this period T _P 'is such an output signal in which the noise component is subtracted from the original output signal V ₀ or removed therefrom. Consequently, the signal level from which the noise has been removed is stored in the sample and hold circuit 10 and then supplied as an output signal b to the output terminal. 1 In Figs. 4A and 4B, the broken lines respectively show noise detected signals containing.

In the circuit arrangement shown in Fig. 3, in order to effectively perform the subtraction operation of the noise component from the signal component containing the noise component in the differential amplifier 16, it is desirable that the above operation be performed in the last part of the signal level period T _S at which the signal level becomes correct. Therefore, a value τ _d ≈ T _S - (length of T _P ) is optimal as the delay time τ _d for the delay line 15 .

Of course, if the pulse width of the sampling pulses SP ₀ is within the period T _P ', the pulse width of the pulses SP ₀ could be shorter than T _P '.

An embodiment of the invention is shown in FIG. 5. In this embodiment, instead of the delay line 15 shown in FIG. 3, a sample storage circuit is used to delay the signal V ₀.

In particular, the output signal V ₀ (see. Fig. 6A), which occurs at the output terminal 1 a , a scan memory circuit 17 , which is supplied with a sampling pulse SP ₁ ( Fig. 6B), which has the period τ _B , the increase - or leading edge compared to that of the precharge interval T _{P of} the output signal V ₀ is delayed by τ _d = τ _B - T _P and the pulse width is equal to the period T _P. Therefore, the signal level portion of the output signal V ₀ is stored in the sample storage circuit 17 as a stored or held output signal H _S , as shown in Fig. 6D. From there, this stored output signal H _S is fed to the inverting input terminal of a differential amplifier 20 .

The output signal V ₀ is also fed to a sample storage circuit 18 , which is also supplied with a sampling pulse SP ₂ ( FIG. 6C), becomes "1" during the precharge interval T _{P of} the signal V ₀. Therefore, the level of the signal V ₀ in the interval T _{P is} stored in the sample storage circuit 18 . A stored output signal H _{N 1} ( FIG. 6E) is fed from there to a further scan memory circuit 19 , which is also supplied with the scan pulse SP 1. Therefore, the stored output signal H _{N 1} is stored in the sample storage circuit 19 . A stored output signal H _{N 2} (see FIG. 6F) is fed from there to the non-inverting input connection of the differential amplifier 20 .

Pulsating voltages E _P 'in the respective stored output signals H _S , H _{N 1} and H _{N 2} , which are shown in FIGS. 6D, 6E and 6F, are introduced pulse components which are generated in that the sampling pulses SP ₁ and SP ₂ each get into the output signal via the capacitance between the gate and source of the FET 11 ( Fig. 1) in the sample memory circuit 10 .

Since the stored output signal H _S from the sample memory circuit 17 is the sampled value of the output signal V ₀ in its signal interval T _S , the output signal H _S thus contains the signal component and the noise component. In contrast, since the stored output signal H _{N 1} from the sample storage circuit 18 is the sampled value of the output signal V ₀ in its precharge interval T _P , the output signal H _{N 1} does not contain a signal component, but only the noise component. Consequently, the noise component can be removed by subtracting the output signal H _{N 1} from the output signal H _S. However, since both output signals H _S and H _{N 1 are} stored output signals of the output signal V ₀ at different times, there is a phase difference between the introduced pulses in the respective output signals, as can be seen from FIGS. 6D and 6E. As a result, if the difference between the output signals H _S and H _{N 1 is} maintained, the introduced pulses occur as they are.

In the embodiment shown in Fig. 5, however, the output signal H _{N 1 is} further stored by means of the sampling pulses SP ₁, so that the introduced pulses occurring in the stored output signal H _{N 2} from the sample storage circuit 19 are in phase with those in the stored output signal H _S occur. That is, the sample memory circuits 18 and 19 perform the same operation as the delay line 15 in the embodiment shown in FIG. 3. Therefore, the differential amplifier 20 generates an output signal S _out and outputs it to the output terminal 1 b ; this output signal has no noise components and the pulses introduced in the scan memory operation are sufficiently suppressed, as shown in Fig. 6G.

As explained, according to the invention this can be done in the pre-charging generated noise in the output stage of the charge detection circuit reduced or removed.

In the illustrated embodiment of the invention, since the minority carrier, which is stored in the CCD image sensor as information, is the electron, the capacitor is previously charged to the reference level upon detection of the charge and then discharged depending on the charge. However, if the minority carrier is a "hole", the stored charge in capacitor 6 is previously discharged to the reference level and then capacitor 6 is charged depending on the charge. In the latter case, the noise generated during discharge can of course be removed or reduced in a manner as in the case where the minority carrier is the electron.

 Of course, the invention is not only in the mentioned CCD image sensor applicable, but it is also applicable to other charge transport elements, such as a bucket chain device (BBD) or the like, and to achieve the same Effect.

Furthermore, the invention can also be used in a so-called interline CCD image recording device which differs from the image recording device 1 shown in FIG. 1.

Claims (1)

Solid-state video camera with a solid-state image recording device ( 1 ) of the charge-coupled type (CCD type), comprising photodetector elements arranged in a matrix, with a vertical shift register which shifts the charges generated in the photodetector elements in a vertical direction,
with a horizontal shift register which shifts a charge from the vertical shift register in a horizontal direction and generates a pulsed video message signal,
with a noise elimination circuit comprising: a first sample-and-hold circuit ( 17 ) connected to the horizontal shift register, which receives a first clock signal with the same frequency as a clock signal controlling the horizontal shift register,
a second sample and hold circuit ( 18 ) connected to the horizontal shift register and connected in parallel to the first sample and hold circuit ( 17 ), which receives a second clock signal with the same frequency as the clock signal controlling the horizontal shift register,
a third sample-and-hold circuit ( 19 ) connected to the output of the second sample-and-hold circuit ( 18 ), which receives a third clock signal with the same frequency with which the clock signal controlling the horizontal shift register occurs,
and a differential amplifier (20) connected at its inverting input (-) is supplied with the output signal of first sample hold circuit (17) and at its non-inverting input (+), the output signal of the third sample hold circuit (19),
characterized,
that the horizontal shift register is connected on the output side to a precharge circuit ( 6-8) with a capacitance ( 6 ) which, via a precharge transistor ( 7 ), occurs due to a precharge pulse ( Pa ) occurring at the same frequency as the clock signal controlling the horizontal shift register during which duration is kept at a reference voltage and is subsequently discharged to the level of the video message signal,
that the first and third clock signals ( SP 1 ) are in phase with one another and have the phase corresponding to the signal component of the output signal of the precharge circuit ( 6-8 ) corresponding to the voltage of the capacitance,
and that the second clock signal ( SP 2 ) is out of phase with the first and third clock signals ( SP 1 ) and has a phase corresponding to the reference voltage part of the output signal of the precharge circuit ( 6-8 ).