JPS6178284A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To remove stably a reset noise by sample-holding, per picture element, a reference potential and video signal component of an output signal at a floating diffusion-type charge detecting part (FDA) having a reset MOSFET and obtaining the difference of the both sample-held values. CONSTITUTION:The output charge of a photoelectric transfer part is transferred by a scanning part composed of charge jointing elements, and given to an FDA having a reset MOSFET. The output signal of the FDA is inputted from a terminal 27, and amplified into a signal l by a buffer amplifier 28. By sampling pulses 1(m) and 2(n) supplied to terminals 44 and 45, a reference voltage (tN period) and a video signal component (tS period) of the signal l are sample-held. These sample-held voltages (o) and (p) are subtracted by a differential amplifier 39. Thus, a fluctuation VN due to a reset noise can be stably removed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention uses a charge-coupled device in the horizontal readout section, a stray diffusion type charge detection section in the signal charge detection section, and a floating diffusion amplifier (Floating Diffus).
ion Amplifier).

Conventional Structures and Their Problems In recent years, solid-state imaging devices have been actively researched and developed as new imaging devices, and are rapidly reaching the stage of practical use.

Television cameras using solid-state image sensors have many superior characteristics compared to conventional image pickup tube-based TV cameras, such as long life, robustness, afterimages, burn-in, and stability. A MOS that reads out signals by dressing the position of the photoelectric conversion element by scanning pulses output from a CCD type or shift register for vertical and horizontal scanning, which is obtained by transferring the signal charge from the photoelectric conversion element.
There are many methods such as types.

Among these solid-state image sensors for television cameras, considering various performances such as sensitivity and pseudo signals, interline CCD type solid-state image sensors (hereinafter abbreviated as IL-COD) that use COD for both vertical and horizontal transfer are the best. It is considered advantageous.

The configuration and operation of IL-COD will be explained below.

FIG. 1 is a diagram showing the configuration of IL-COD.

In FIG. 1, 1 is a photodiode (hereinafter abbreviated as PD) as a photoelectric conversion element, 2 is a vertical transfer register, and this vertical transfer register 2 is a vertical transfer gate) 3, 4.
, 5.6. Reference numeral 7 denotes a signal readout gate, which is used to read out the signal charge of PDl to the vertical transfer gate 3 or 5. 8 is vertical transfer pulse φ
It is a supply terminal for (1) to (phi)4, and 9 is a supply terminal for signal readout pulses (phi)F1t (phi)F2. Reference numeral 10 denotes a horizontal transfer register, and this horizontal transfer register 1o is composed of horizontal transfer registers 11, 12, 13, and 14. 1
5 is a supply terminal for horizontal transfer pulses φH1 to φH4.

Reference numeral 16 denotes a charge detection section which converts the signal charge transferred from the horizontal transfer register into a signal voltage. This charge detection section 1
6 is usually a stray diffusion type charge detection section, a floating diffusion amplifier (Floating Diffusi
on Amplifier (hereinafter abbreviated as FDA). 17 is a signal output terminal.

The operation of the IL-COD configured as above will be explained next.

The photodiode 1 photoelectrically converts incident light from a subject and accumulates signal charges. After the signal charge is read into the vertical transfer gate 3 or 5 via the signal readout gate 7, it is sequentially transferred in the direction of the horizontal transfer register 1o by the vertical transfer pulse supplied from the vertical transfer pulse supply terminal 8. Each horizontal line is transferred to the horizontal transfer register.

Here, in the first field, a signal read pulse is supplied to φF1 of the signal read pulse supply terminal 9,
The signal charge of the horizontal column PD1 connected to the vertical transfer gate 6 is read out, and in the second field, a signal readout pulse is supplied to φF2 of the signal readout pulse supply terminal 9 to read out the signal charge of the horizontal column PD1 connected to the vertical transfer gate 3. Two-to-one interlaced scanning is performed by reading out signal charges.

The signal charge transferred to the horizontal transfer register 1o is a horizontal transfer pulse φ supplied from the horizontal transfer pulse supply terminal 15.
The signal charge is sequentially transferred to the charge detection unit 16 by H1 to φH4, and converted into a signal voltage by the 70-signal delay in the charge detection unit 16, and is obtained as a point-sequential signal from the signal output terminal 17. A video signal is generated by processing the received point-sequential signal using an electric circuit.

The IL-COD with the above configuration is the most common configuration, and includes a mechanism for reading signal charges accumulated in PDl into the vertical transfer stage, an operating mechanism of the vertical transfer stage, and a signal from the vertical transfer stage to the horizontal transfer stage. The charge transfer mechanism, the operation mechanism of the horizontal transfer stage, and the operation mechanism of the charge detection section e are already known, so their explanations will be omitted; however, since the present invention is closely related to the operation of the charge detection section, The operations of the horizontal transfer stage and charge detection section will be briefly explained using FIGS. 2 and 3.

FIG. 2 is a sectional view showing the structure of the horizontal transfer stage and charge detection section in FIG. 1, and parts having the same functions as those in FIG. 1 are given the same numbers.

18 is a p-type substrate, and a part thereof has an n+ diffusion layer 19.
and 2o are provided. An electrode 11 made of polyconductor is formed on a p-type substrate 18 via an insulating oxide film S10221.
14, each of which is connected to 'Ht-φH2 of the horizontal transfer pulse supply terminal 16, and further connected to the electrode 2.
2.23 is formed. The electrode 22 is an output gate to which a DC voltage v1 is applied, and the electrode 23 is a reset electrode φR and is connected to the reset pulse supply terminal 24. The diffusion layer 20 is a reset drain, and a DC voltage v2 is applied thereto. The diffusion layer 19 is a floating diffusion (rotating diffusion) that is not directly connected to a DC power source. This diffusion layer is connected to the gate of FET 25, the drain of FET 26 is applied with DC voltage v2, the source is connected to resistor 26, and the output terminal 17 is connected to the source. j 9,20.2
2 to 26 form a floating differential amplifier of the charge detection section 16.

Next, the operation of the horizontal transfer stage and the charge detection section will be explained using FIG.

Figure 3a further simplifies the horizontal transfer stage and charge detection section shown in Figure 2, and shows a potential model at each time from t1 to t5 in Figure 3.
11φH2, φH3, φH41φ, signal waveform diagram. At tl in Figure 3a, the state is on the verge of horizontal transfer;
In other words, this is the state immediately after signal charges are transferred from the vertical transfer stage to the horizontal transfer stage.

First, at time t1, when the φH1 + φH2 voltage is applied, the potential voltage under the φH1 + φH2 electrodes becomes high, and the signal charge transferred from the vertical transfer stage to the horizontal transfer stage is φ
It is trapped under the H1 and φH2 electrodes. At this time, the potential of the floating diffusion (hereinafter abbreviated as FD) 19 maintains the state shown in FIG. 3 when the A pulse of the φR pulse is applied to the φR terminal. In other words, φ is connected to the φR terminal.
When the R pulse A is applied, the potential of the FD19 becomes approximately 1, and the potential 1 is maintained unless a charge is applied to the FD19.

The reason why φR is applied even during the horizontal retrace period when no signal charge is injected into FDl 9 is to prevent the potential of FDl 9 from changing due to dark current.

Next, at t2 in FIG. 3A, a state is shown in which the signal charge is transferred in the direction of the charge detection section by one electrode of the COD. At this time, the potential of FDI 9 is maintained at ■1.

At t3 in FIG. 3a, the signal charge moves toward the charge detection section by C
Since only one electrode of OD is transferred and the φR pulse is applied to the φR terminal, the potential of FDl 9 becomes ■1.

At t4 in FIG. 3a, the signal charge moves toward the charge detection section by C
Since only one electrode of OD is transferred, part of the signal charge is captured under the φR4 electrode, and the rest is transferred to FD19,
The potential of Dl 9 decreases.

At t6 in FIG. 3a, the signal charge is further transferred in the direction of the charge detection section by one electrode of COD, so all the signal charges trapped under the φH4 electrode are also transferred to FDl9, so that the signal charge of FDl9 is The potential further decreases to a potential of ■P.

This potential Vp of FDl9 is held until a φR pulse is applied to the φR terminal.

FIG. 4 shows the relationship between the φR pulse and the output signal in the charge detection section of the horizontal transfer stage with the operating principle as described in 2.

In FIG. 4, φR is the same as φR shown in FIG. 3, and the waveform actually shown in the diagram showing the output signal is P
This is the output signal waveform when the signal charge from the PD is zero, and the waveform shown by the broken line is the signal waveform when the signal charge from the PD is present.

Further, vR is the φR pulse appearing at the gate of the FET 25 through the φR gate 23 and the stray capacitance of the FD19.

By the way, in order to convert the signal charge from the PD into a charge-voltage by the charge detection unit and extract it as a signal voltage, the potential of the FD must be reset to vl every time the signal charge for one PD is detected, as described above. However, when resetting the FD, noise such as internal noise of the charge detection section is generated.
The reset potential of the FD fluctuates due to noise. (Hereinafter, this noise will be referred to as reset noise.) This reset noise is held in the capacitor of the FD until the FD is reset next time, that is, the reset noise is output in a sampled and held form.

Therefore, the periods B and C shown in FIG. 4, that is, the reset period and the signal output period both fluctuate due to the reset noise. Therefore, if this output signal is simply processed to produce a video signal, the result will be a signal mixed with the reset noise.

The reset noise has a power of 1 whose power is inversely proportional to the frequency.
/f noise. Since the frequency of the 1/f noise in the charge detection section is less than or equal to the output signal frequency, there is little variation in the 1/f noise over several bit periods of the output signal, and it is considered to be almost constant.

1/f noise appears randomly in the form of horizontal bands on a television screen, and therefore significantly impairs the image quality.

A conventional example of removing reset noise focusing on the characteristics of the 1/f noise described above will be explained using FIGS. 5 and 6.

Figure 5 shows the correlated double sampling method (hereinafter abbreviated as CDS)
1 is a block diagram of 1/f noise removal called 1/f noise removal.

The operating principle of this correlated double sampling method is the charge transfer device; Translated by Yoshiyuki Takeishi and Susumu Kayama of Kindai Kagakusha, P49-P2
O, P 111-Pl 12 and the 1984 TV Society National Conference Proceedings P59-Peo provide detailed explanations, so a brief explanation will be given here.

FIG. 6a is a schematic diagram of the output waveform of IL-COD using FDA. In the actual output waveform, the edges of each part have a gentler slope.O1 is a seven-node period, tw is an FDA reference voltage period, and t8 is a signal period. The above-mentioned 1/f noise is KTC noise caused by thermal noise of the reset switch (FIG. 2, 23) caused by FDA's φR.

Here, K is Portzmann's constant, T is temperature, and C is the capacitance of the floating diffusion. This KTC,%1
The sound i appears as a variation VH of the reference voltage. Therefore, it can be seen that this noise can be removed by subtracting the noise component vN from the signal voltage vs.

Figure 6 shows the reset pulse waveform supplied to the FDA.
Figure C shows a clamp pulse supplied by the clamp circuit of the CDS circuit, and Figure 6d shows a sampling pulse supplied to the sample hold circuit of the CDS circuit.

If the pulses shown in FIG. 6 c and d are supplied to the CDS circuit shown in FIG. can. This signal with suppressed fluctuations in the reference voltage is supplied to a sample and hold circuit to obtain a sampled and held signal.

However, in reality, as explained in the above-mentioned literature, 1/f noise has not yet been completely eliminated.

The main reason is that the switch in the clamp circuit is not an ideal switch, and there is leakage current in the clamp capacitor. This is because the impedance on the receiving side of the clamped signal is not infinite, and furthermore, there is aliasing noise of high frequency components included in the output signal of the solid-state image sensor.

Furthermore, a high degree of stability is required for the phase and pulse width of the clamp pulse. However, in reality, clamp pulses are often generated using a mono-multivibrator or the like, in which case there is a possibility that the clamp circuit may malfunction due to temperature changes or changes over time.

OBJECTS OF THE INVENTION An object of the present invention is to provide a solid-state imaging device that can stably remove reset noise contained in a solid-state imaging device output signal.

Structure of the Invention The present invention provides a stray diffusion charge detection unit (FDA
) is formed on the same chip.The FDA output signal of the optical image element is supplied to the first and second sample and hold circuits, and the reference potential of the FDA is determined by the first sample and hold circuit. The video signal component is sampled and held for each pixel by a second sample and hold circuit, and the video signal component is sampled and held for each pixel.
By subtracting the output signal of the second sample and hold circuit, a video signal from which reset noise has been removed is obtained.

DESCRIPTION OF EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIGS. 7 and 8.

FIG. 7 is a diagram of one embodiment of the present invention.

In FIG. 7, 27 is a signal input terminal to which an FDA output signal of the solid-state image sensor is input.

28. 37 and 38 are buffer amplifiers having high input impedance and low output impedance characteristics. 40.
42 is an analog switch, 41 and 43 are capacitors, and the analog switches 40 and 42 are opened and closed by sampling pulses (1) and (2), respectively. Sampling pulses (1) and (2) are supplied from sampling pulse supply terminals 44 and 45, and the analog switches 40 and 42 are closed when the sampling pulse is at high level and open when the sampling pulse is at low level. 39 is a differential amplifier, and 36 is a signal output terminal. 40,41.37
and 42°43.38, each of which constitutes one sample hold circuit.

The output terminal of the buffer 7 amplifier 28 is an analog switch 40
．． 42, and the other end of the analog switch 40.42 is connected to a capacitor 41.43 and a buffer amplifier 37.38. One end of the capacitor 41, 43 is grounded. The output terminals of the buffer amplifiers 37 and 38 are connected to the input terminals of the differential amplifier 39, respectively. 36 is a differential amplifier output terminal.

A sampling pulse is supplied to the analog switch 40.42 via a sampling pulse supply terminal 44.45.

Next, the operation of this embodiment will be explained using FIGS. 7 and 8.

An example will be described in which a subject whose entire surface is white is imaged.

The FDA output signal of the solid-state image sensor is input to the analog switch 40.42tl via the input terminal 27° buffer amplifier 28.
C is supplied. The waveform of the FDA output signal, ie, the signal applied to the analog switches 40 and 42, is shown in FIG. 8f. In the signal waveform of FIG. 8, tr is the reset period, tN is the FDA reference voltage period, t8 is the signal period, and the reset noise is shown as the reference voltage variation ■N. Therefore, in order to remove this noise, the objective can be achieved by subtracting the noise component vN from the signal voltage ■s.

Therefore, the 8th pulse is connected to the sampling pulse (1) supply terminal 44.
A sampling pulse shown in the figure is supplied to sample and hold a part of the tH period of the input signal. The buffer amplifier output signal at this time is shown in FIG. 8i. That is, the waveform in FIG. 8i shows the change in the FDA reference voltage and shows the reset noise component.

Next, the sampling pulse (2) is connected to the supply terminal 46 in FIG.
1 of the input signal by supplying the sampling pulse shown in .
Sample and hold part of one period.

The output signal of the balance amplifier at this time is shown in FIG. 8k.

This waveform shows a change in the signal during the t8 period, and this change in signal component is due to reset noise. Therefore, by subtracting the waveform 1 from the waveform shown in FIG. 8, the reset noise can be removed. That is, by supplying the output signals of the buffer amplifiers 37 and 38 to the differential amplifier 39 and subtracting them, a video signal from which reset noise has been removed can be obtained from the output terminal 36.

Furthermore, according to the invention a sampling pulse (1).

All noises correlated to the period (2) can be removed.

It is possible to remove it by

Further, according to the present invention, since there are two sampling pads 18, fatal malfunctions as shown in the conventional example do not occur.

Next, a specific reset noise removal circuit according to the present invention will be described in the ninth section.
This will be explained using figures.

In FIG. 9, 27 is a signal input terminal, 48 is a transistor, and 47 resistors are connected to the emitter of the transistor 46. 48 is a resistor, one end of which is connected to the emitter of the transistor 4e, and one end of which is connected to one end of the capacitor 49. One end of the capacitor 49 is grounded. 50 and 53 are FETs whose drains are commonly connected to the emitter of the transistor 46;
The sources of each are connected to the gates of FETs 61 and 6i4, respectively. Capacitors 61 and 62 are connected to the gates of FETs 61 and 54, respectively, and one end of each of these capacitors is grounded.

Diode 63°6 is installed on the gate of FET50, 53 (7)
6 are connected, and the cathodes of each diode are commonly connected to the connection point between the capacitor 49 and the resistor 48. Furthermore, a capacitor 54,5 is connected to the gate of FET50,5319.
One end of each capacitor is a sampling pulse supply terminal 45. This serves as a sampling pulse supply terminal 44.

Source resistors 52 .
55 is connected, and one end of the source resistor is grounded. Further, the drains of the FETs 54 and 51 and the collector of the transistor 46 are connected to the power supply line V. Connected to C.

Capacitors 58 and 59 are connected to the sources of the FETs 51 and 54, and one end of each capacitor is connected to the (→ input terminal and (→ input terminal) of the differential amplifier 60. power supply line and grounding line,
It has an output signal terminal 36.

Transistor 46. The resistor 47 constitutes a buffer 7 amplifier, the FETs 50, 61, the resistor 62, and the capacitor 61.54 constitute the first sample-and-hold circuit, and the FET 53°64, the resistor 66, and the capacitor 62.67 constitute the second sample-and-hold circuit. In addition, a resistor 48 and a capacitor 49 constitute an integrating circuit.

Next, the operation of this circuit will be explained using FIGS. 9 and 10.

FIG. 10 shows the waveform at the emitter of transistor 46. VD at l is its average DC potential,
The potential VD is equal to the potential obtained by integrating the signal components with an integrating circuit consisting of a resistor 48 and a capacitor 49. It is equal to the voltage at the connection point between trench capacitor 49 and resistor 48.

Figure 10 m and n are FET50. It shows the waveform and potential of the sampling pulse supplied to the gate of ts3. The maximum value of the sampling pulse supplied from the sampling pulse supply terminals 44 and 46 is held by capacitors 54 and 57 and diodes 53 and 56 at a potential vT higher than the above-mentioned VD by the forward voltage of the diode. A high frequency diode is used as this diode. Further, the FETs 50 and 53 are turned off when the gate-source voltage is about 12V, and turned on when the voltage is 07 or more. Therefore, the sampling pulse is 3
If the amplitude is sufficient, turn on FET50゜53 sufficiently.
It can be turned OFF.

In this way, by sampling pulses (1) and (2), a part of the period tN of the output signal of the solid-state image sensor is transferred to the FET50.
, capacitor e1. Sample and hold is performed using FET 51, and part of the 1B period is performed using FET 53 and capacitor 62.
Sample and hold is performed by FET54. F at this time
The waveform of the source terminal of ET51.64! Figure 10't
Shown in P. The 00 waveform shows a change in the waveform during the tN period, and this waveform is due to reset noise.

The waveform of p shows the change in the waveform during the t8 period,
This waveform change becomes a waveform in which reset noise and changes in the subject image are superimposed.

Therefore, by subtracting these waveforms using the differential amplifier 6o, a signal from which series reset noise has been removed can be obtained.

In this embodiment, the maximum value of the sampling pulse is maintained at the average value of the emitter potential of the transistor 4622 using a capacitor and a diode, so the amplitude of the sampling pulse only needs to be about 300 m. The output signal of a general TTL logic IC can be used as it is with an amplitude of about 30 degrees.

If the maximum value of the sampling pulse is held at the average value of the emitter potential as described above, in order to sufficiently turn on and off the FETs 50 and 53, the amplitude of the sampling pulse must be made up to the emitter potential of the transistor 46. No. In order to increase the amplitude of the sampling pulse in this way, the TTL logic IC output signal must be amplified, which requires a new amplifier capable of high frequency and large amplitude, which is uneconomical.

As described in detail, according to the present invention, reset noise included in a solid-state image sensor output signal can be stably removed. Furthermore, since the sampling pulse operates satisfactorily even if the amplitude is relatively small, the TTL logic IC output signal can be used as the sampling pulse as it is.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing the configuration of IL-COD, Figure 2 is a detailed circuit diagram of the horizontal transfer stage and signal charge detection section, and Figure 3a is a state diagram showing the charge transfer state. Waveform diagrams of transfer pulses and reset pulses, Figure 4 is a signal waveform diagram showing the operation of the charge detection section, Figure 5 is a conventional reset noise removal circuit, and Figure 6 is a waveform diagram showing waveforms of each part in Figure 5. ,
FIG. 7 is a circuit diagram showing a noise removal circuit according to an embodiment of the present invention, FIG. 8 is a waveform diagram showing waveforms of each part of FIG. 7, and FIG. 9 is a circuit diagram showing a specific circuit example according to the present invention. The circuit diagram shown in FIG. 1o is a waveform diagram showing waveforms of various parts in FIG.・ 28, 37.38...Buffer amplifier, 39...Differential amplifier, 40.42...
Analog switch, 41.43...capacitor.

Claims (2)

[Claims] (1) The output signal of the stray diffusion type charge detection section of a solid-state image sensor in which a scanning section consisting of a photoelectric conversion section and a charge-coupled device, and a stray diffusion type charge detection section equipped with a reset MOSFET are formed on the same chip. 1 and a second sample hold circuit, the first sample hold circuit samples and holds the reference potential of the stray diffusion type charge detection section for each pixel, and the second sample hold circuit samples and holds the reference potential of the stray diffusion type charge detection section. A solid-state imaging device characterized in that a video signal component of a signal output from a charge detection section is sampled and held for each pixel, and output signals from the first and second sample and hold circuits are subtracted and output. (2) Claims characterized in that the maximum value of the sampling pulses supplied to the first and second sample and hold circuits is fixed to the DC potential of the average value of the stray diffusion type charge detection unit output signal. The solid-state imaging device according to item 1.