CA1161548A - Signal pick-up circuit - Google Patents
Signal pick-up circuitInfo
- Publication number
- CA1161548A CA1161548A CA000370198A CA370198A CA1161548A CA 1161548 A CA1161548 A CA 1161548A CA 000370198 A CA000370198 A CA 000370198A CA 370198 A CA370198 A CA 370198A CA 1161548 A CA1161548 A CA 1161548A
- Authority
- CA
- Canada
- Prior art keywords
- charge
- output
- signal
- circuit
- pick
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
Abstract
ABSTRACT OF THE DISCLOSURE
A signal pick-up circuit is disclosed which has the base on the fact that the noise level in an output from an image picking-up device is constant during one bit interval and no signal component exists during pre-charge period or interval thereof and eliminates the noise upon the pre-charge operation by using the difference between the levels of the output during the pre-charge and signal level intervals.
The signal pick-up circuit includes an image picking-up device having a charge transfer element and pro-ducing an output charge corresponding to an object to be picked up, a circuit for receiving the output charge from the image pick-up device and producing a charge detecting signal including a reference level portion and a signal por-tion provided by charge or discharge in response to the output charge, the reference level portion and the signal portion being repeated at every one bit of the ouput charge, and a circuit for providing difference output between the reference level portion and the signal portion.
A signal pick-up circuit is disclosed which has the base on the fact that the noise level in an output from an image picking-up device is constant during one bit interval and no signal component exists during pre-charge period or interval thereof and eliminates the noise upon the pre-charge operation by using the difference between the levels of the output during the pre-charge and signal level intervals.
The signal pick-up circuit includes an image picking-up device having a charge transfer element and pro-ducing an output charge corresponding to an object to be picked up, a circuit for receiving the output charge from the image pick-up device and producing a charge detecting signal including a reference level portion and a signal por-tion provided by charge or discharge in response to the output charge, the reference level portion and the signal portion being repeated at every one bit of the ouput charge, and a circuit for providing difference output between the reference level portion and the signal portion.
Description
BACKGROUND OF THE INVENTION
Field of the Inventio_ The present invention relates generally to a signal pick-up circuit, and is directed more particularly to a signal pick-up circuit for use with an image picking-up de-vice which can eliminate a noise upon pre-charge operation.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a circuit diagram showing a prior art charge detecting circuit which is used as an output deriving circuit of a CCD solid state image pick-up de~ice;
Figs. 2A to 2C are respectively waveform diagrams used to explain the operation of the prior art . ~.
.
~ j L~
example shown in Fig. l;
Fig. 3 is a systematic diagram showing ths essential part of an example of the signal pick-up circuit according to the present invention;
Figs. 4A to 4C are respectively waveform dia-grams used to explain the operation of the example of the invention shown in Fig. 3;
Fig. 5 is a systematic diagram showing the essential part of another example of the invention; and Figs. 6A to 6G are respectively waveform dia-gr~ms used to explain the operation of the example of the invention ~hown in Fig. 5.
Description of the Prior Art A prior art measure to detect a signal charge which is provided by the photo-electric conversion in a solid state image picking-up device or image sensor using, for ex-ample a CCD (charge coupled device) and to derive it as an output signal is as follows.
Fig. 1 is a connection diagram showing an ex-ample of the prior art output or signal picking-up circuit for a CCD image sensor. In this example, the operation sys-tem of the CCD image sensor is the case of frame transfer system, and the minority carxier stored as information is an electronO In the example of Fig. 1, the left side portion from a dotted line P is the CCD image sensor device which is formed on one IC (integrated circuit) chip and the right side portion from the dotted line P is a sampling and hold circuit serving as a wave shaping circuit.
In Fig. 1, 1 generally designates an image pick-up device and la designates an output terminal of the output deriving or picking-up circuit. The image pick-up de-vice 1 comprises a photo-sensitive area 2, a storage area 3 for the photo-sensitive area 2, a read-out register 4 for the storage area 3, and an output gate and output diode portion 5 which is reversely biased.
The signal charge produced in the photo-sensitive area 2 is transferred to the storage area 3, and in the photo-sensitive area 2 such a photo-electric conversion is carried out that the signal charge temporarily stored in the storage area 3 is transferred tothe read-out register 4 at every one line in the horizontal direction and delivered in time series through the output gate and output diode portion 5.
The output terminal of the output gate and output diode por-tion 5 is grounded through a capacitor 6 and also connected to the source of an FET (field effect transistor) 7 which has the drain supplied with a DC voltage ER and the gate suppliPd with a pre-charge pulse Pa (refer to Fig. 2A) which is syn-chronized with the transfer clock for the read-out register 4.
The connection poLnt between the portion 5 and capacitor 6 is connected to the gate of an FET 8 which has the drain supplied with a DC voltage E and the source connected to the output terminal la.
Thus, in the above output deriving circuit, during a time interval Tp within which the pulse Pa i5 in a high level as shown in Fig. 2A, the FET 7 turns ON and hence the capacitor 6 is pre-charged up to the voltage ER. When a time interval TS within which the pulse Pa is in a low level arrives, the FET 7 turns OFF and hence the voltage across the capacitor 6 becomes low in response to the output signal charge. Therefore, when the ~oltage ER is taken as a reference s~
level, the voltage across the capacitor 6 in the interval TS
becomes the signal level~
In this case, since the pulse Pa is synchron-ized with the transfer clock for the read-out register 4 as set forth above, a charge detected output voltage VO, in which the pre-charge level and signal level will repeat at every one stage portion of the read-out register 4 i.e. one bit portion thereof, appears across the capacitor 6 and such a voltage VO
is delivered to the output terminal la through the FET 8 which forms a buffer amplifier (refer to Fig. 2B).
In this example, in practice, the pulse Pa is jumped into the signal path through the stray capacity between the gate and source of the FET 7, so that a voltage component Ep caused by the jumping of pulse Pa is superimposed on the output voltage VO appearing at the output terminal la as shown in Flg. 2B. Since the jumped-in voltage component Ep, however, is approximately constant, there will occur no trouble even if the signal higher than the level ER by the voltage Ep is taken as the reference level for the signal level. Therefore, in fact there occurs no trouble even if the voltage ER ~ Ep higher than the normal pre-charge level by Ep is taken as the pre-çharge level.
The output voltage VO thus delivered to the output terminal la is supplied to a sampling and hold circuit 10 or to the drain of an FET 11 therein for the sampling. This FET 11 is supplied at its gate with a sampling pulse Pb which becomes a high level in the signal level interval TS of the out-put voltage VO as shown in Fig. 2C, so that the FET 11 turns ON
within the high level interval of the pulse Pb and hence the signal level of the output voltage VO is sampled. Then, a capacitor 12 for the holding in the circuit 10 is charged to L5~
the signal level of the ampled signal or discharged, and hence the signal level is held in the capacitor 12. A held voltage VH across the capacitor 12 is derived through an FET 13 forming a buffer amplifier to an output terminal lb. In Fig.
1, 9 and 14 are respectively load resistors for the FETs 8 and 13.
When the charge stored in the CCD image sensor device is derived after being converted into a volta~e as des-cribed above, it is necessary that when the minority carrier is the electron as set forth above, the capacitor 6 is pre-charged at every one bit. Upon the pre-charge operation, however, such noises as the internal noise in the FET 7, power source noise for the FET 7 and so on are generated, and the reference pre-charge level is fluctuated by the noises. And, a level N of the noises produced in the pre-charge interval is held by the capacitor 6 in one-bit interval T~ = Tp ~ TS or the noise is output in the form of the sample-held. As a result, the output voltage VO becomes fluctuated as shown by the dotted line in Fig. 2B by the noise and hence the signal level in the inter-val TS is also fluctuated. Accordingly if the signal level portion of the output voltage VO is merely sampled and held as in the prior art example of Fig. 1, the noise component is mixed into a signal component S and then delivered as the Outputa OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a signal pick-up circuit free from the defects encountered in the prior art.
Another object of the invention is to provide a signal pick-up circuit for use with an image picking-up device which can effectively reduce or remove noises upon pre-charge operation.
S~8 According to an aspect of the present invention there is provided a signal pick-up circuit which comprises:
a) an image pick-up device including a charge transfer ele-ment and producing an output charge corresponding to an object to be picked up;
b~ means for receiving said output charge from said image pick-up device and producing a charge detecting siganl in-cluding a reference level portion and a signal portion pro-vided by charge or discharge in response to said output charge, said reference level portion and said signal portion being repeated at every one bit of said output charge; and c) means for providing a difference output between said reference level portion and said signal portion.
The additional, and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accom-panying drawings through which the like references designate the same elements and parts.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention has the base on the fact that the noise level is constant in one-bit interval T B and no signal component is presented in the pre-charge interval Tp and eliminates the noise by obtaining the leve~ difference between the levels of the pre-charge interval Tp and the signal level interval Ts.
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5 ~8 An example of -the siclnal ~icl~--up circuit accorclincJ to the present invention wi]] he descri.hed wi.-th reference. to Fic3. 3 which shows the essential part of thc invention.since the other portion oE the invention is sub-stantia].ly the same as that of ~ . 1 or the part ]eft sicle from the dotted li.ne ~ in ricr. 1.
In the example of the inventi.on shown in Fi~. 3, the output voltacJe VO (refer to Ficr. 4~) clerived at the output terminal la i.s fed to a dela5~ cireui.t or ].ine 15 ancl delayed therei.n hy Td ( c Td c ~ as a si~rnal Vod (refer to,FicJ. 4~). This delavecl sic~nal Vod is applied to the inverted input terminal of a cliE~Eerential amplifi.er 16 wllich is also supplied a-t its non-i.nvertecl input'terminal with the sicJnal VO as it is. Thus, the cli.fferential amplifier 16 produces a difference ou-tput het~een both sicJnals VO and Vod.
The output from -the di:Eferent;,al amplifier 16 is fed to the samplin~ and ho]d circuit 10 similar to that of Ficr. 1. In this e~ample, the samplincr and hold circuit 10 is supplied with a sampling pulse SPO (refer to Fig. 4C)'whose period is T~ and which becomes the level "1" in a pre-charcre interval Tp' of the siqnal Vod~ and hence the value of the output from the differential ampli-fier 16.i~n the period Tp' is sample-held.
In this case, durincr the pre-charcre period Tp' of the sicJnal V~d, one input sicJnal VO to the dif~erential amplifier 16 is the sicJnal component plus the noise eom-ponent and the other input siqnal Vod thereto is only tl-e noise component, so that the output from the differential amplifier 16 in this period Tp' becomes such one that the noise component is subtrac-tecl or removed from the original output signal V~. Accordinq]y, the sicJnal ].evel, fro~
which the noise i.s removed, is sample-lle].cl in the samnllng and hold circ~lit 1~ and -then clelivered as the outr!~lt to thc-outnut termi.n,~l lb. In ~igs. ~A and ~, thc clottecl lincs show the detec-tcd si~Jna].s con-tai.ninq no;sos, resr-ectively.
In the e~ample of the invention shown in Fig. 3, in orcler to effectively carry out -the operation of suhtracting the noise component from the si~na]. component with the noise component in the differential. ampli.i.er 16, it lS desired that the above operation i.s carriecl out at the last portion of the si.gnal level per;.ocl TS w]lere the signal level ~ecomes correct. Therefore, as the delay time Td of the delay line 15, ~d~ TS ~ (length of Tp) is opti.mum.
It is needless to say -thcat if the pulse width of the sampling pulse SPO is within the per;.od Tp', ~ ~ the pulse width of the pulse SPO coulcl be shorter -tban T~
: ~ ~ Another example of the invention is shown 20~ i.n Fig. 5. : In this example, in place oE the clelay line 15 used-in the exa~ple of .ig. 3, a samplin~ and hold circuit is employed to delay the signal VO.
: ~
In detail, the output si~nal VO trefer to ~ Fig. 6~ appearing at the output terminal ]a is fed to a : 25 ~ :sampllng and hold cir~cuit 17 which is also supplied with : a samplin$ pulse SPl (refer to Fig. 6B) which has the period of ~, the risinq-up or;front edge clelayed from that o .
:~ ~ the pre-c;harqe interval Tp of the output siqnal vn by ~d = ~B - '.p and the pulse widtll eaual to the period Tp.
Thus, the siqnal level portion of the ou-tput si~nal VO is 9 ~
.
:~
Si~8 sample-held i.n the s~mpling holcl eircuit 17 as a he]d output lls as shown in Fig. 6D. This held ou-tput H~
therefrom is fed to the inverted input termina]. o~ a diEferential amp].iEier 20.
Tl-e outnut signal V~ i.s a1.so .~pplicd to a sampli.nc.J and ho].d circuit ~ which is a]so suppli.cd wi.th a sampling pulse SP2 (reEer to Flq, 6C) which becomes 1~],!1 durin~3 the pre-charge interval T~ of the si~nal VO.
Thus, the level of the signal VO in the interval Tp is sample-he1.cl in tho sampling ancl hold circuit ].8. ~ held ; output IINl (reEer to Fig. 6~) therefrom is fed to a further :~ sampling and hold ci.reuit 19 whieh is also supplied with the sampling pulse S~l. Thus, the held output l-lNl is sample-lleld in the .samplinq and hold eireui.t 19. ~. held ~ ~ 15 output JIN2 (refer to Fig. 6F) therefrom is appli.ed to the :~ ~ non-inverted input terminal of the diEferential amplifier : 20.
Pu].sating voltages ~p' in the respeetive held OUtp~ltS Hs, HNl and HN2 shown in Fi,gs. 6D, 6~ and 6F
are~ jumped-in:pulse eomponents whieh are ~enerated by the faet that the~ samplincJ pulses SPl ancl S~2 respeetively ump into the~output signal through the eapaeity between .
~ the gate souree of FET 11 (refer to Fig. 1) in the sampling~
.
~ : and hold~eireuit 10. ~ ~
:
~:; 25 ~ ~ In thi~s case, sinee the held output EJS from ; ; ~ the sampling and hold cireuit l7 is the sampled value of ;~ ~; the outpu~-t VO in i-ts .signal interva]. Ts, the output HS
: ineludes the si~Jnal eomponent and the noise eomnonent.
~Yhi1e~ sinee the held output HNl from the sampling and ~ hold eireuit .l8 i5 the samp].ed ~alue of the output VO
,o-: ~
6~15 ~ 8 in its pre~charcJe i.nterval Tp, the output 11Nl includes no sicJnal component and only -the noise component. ~ccord-in~ly, the noise component can be rernoved by subtractin~
the output 111~l from the output 1IS. Ilo~ever, since both outputs 11;5 and 1IN] arc sample-hclcl outputs of output ~lo at different times, -thcre is a phase difference between the jump-in pulses in the respective outputs as apparent from Fi~s. 6D and G~. Thercfore, if the difference betwcen the outputs 1-1S anc!11~l is obtained, the jump-in pulses appear as they are.
In the example of the invention shown in Fi~. S, however, the output MNl is further sample-held by the samplincJ pulse SPl, so that the jump-in pulse appearincJ
in the held outpu-t ~1N2 from the samplincJ and hold circuit 19 is same in phase as that appearing in the held output ; : 11S. In other words, the samplincJ and hold circuits l8 and 19 earry out the same operation as that of the delay line 15 ln the example of FicJ. 3. Thus, the differential amplifier 20 produces such an output SOUt to the output terminal lb which includes no noise component and in which .
the ~ump-in pulse upon the samplin~-hold operation is sup~
pressed sufficiently as shown in Fig. 6G.
:
~ s described above, according to the present .
: invention, the noise ~enerated upon the pre-ehar~e operation can be reduced or removed at the output stage of the char~e :
detecting circuit.
In the above examples of the invention, sinee the minority carrier, which is stored in the CCD as the information, i.s the eleetron, upon detectincJ the char~e, the :30 eapaeitor 6 is previously eharged to the reEerenee level and , then discharged in response to the charge. 11owever, 11~15i~3 when the minority carrier is a hole, the stored charge in the capacitor 6 is previously discharged to the reference level and the capacitor 6 is charged in response to the charge~ In the latter case, it is needless to say that the noise generated upon the discharge can be removed or reduced by the manner similar to the case where the minority carrier is the electron.
It would be apparent that the present inven-tion can he applied not only to the above CCD charge transfer element but also to other charge transfer elements such as a BBD tbucket brigade device) or the like with the same effect.
Further, the present invention can be applied to the CCD image pick-up device of a so-called interline type which is different from the CCD image pick-up device shown in Fig. 1 which is the frame transfer type.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel con-cepts of the present invention, so that the spirits or scope of the invention should be determined by the appended claims only.
.~ ~
Field of the Inventio_ The present invention relates generally to a signal pick-up circuit, and is directed more particularly to a signal pick-up circuit for use with an image picking-up de-vice which can eliminate a noise upon pre-charge operation.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a circuit diagram showing a prior art charge detecting circuit which is used as an output deriving circuit of a CCD solid state image pick-up de~ice;
Figs. 2A to 2C are respectively waveform diagrams used to explain the operation of the prior art . ~.
.
~ j L~
example shown in Fig. l;
Fig. 3 is a systematic diagram showing ths essential part of an example of the signal pick-up circuit according to the present invention;
Figs. 4A to 4C are respectively waveform dia-grams used to explain the operation of the example of the invention shown in Fig. 3;
Fig. 5 is a systematic diagram showing the essential part of another example of the invention; and Figs. 6A to 6G are respectively waveform dia-gr~ms used to explain the operation of the example of the invention ~hown in Fig. 5.
Description of the Prior Art A prior art measure to detect a signal charge which is provided by the photo-electric conversion in a solid state image picking-up device or image sensor using, for ex-ample a CCD (charge coupled device) and to derive it as an output signal is as follows.
Fig. 1 is a connection diagram showing an ex-ample of the prior art output or signal picking-up circuit for a CCD image sensor. In this example, the operation sys-tem of the CCD image sensor is the case of frame transfer system, and the minority carxier stored as information is an electronO In the example of Fig. 1, the left side portion from a dotted line P is the CCD image sensor device which is formed on one IC (integrated circuit) chip and the right side portion from the dotted line P is a sampling and hold circuit serving as a wave shaping circuit.
In Fig. 1, 1 generally designates an image pick-up device and la designates an output terminal of the output deriving or picking-up circuit. The image pick-up de-vice 1 comprises a photo-sensitive area 2, a storage area 3 for the photo-sensitive area 2, a read-out register 4 for the storage area 3, and an output gate and output diode portion 5 which is reversely biased.
The signal charge produced in the photo-sensitive area 2 is transferred to the storage area 3, and in the photo-sensitive area 2 such a photo-electric conversion is carried out that the signal charge temporarily stored in the storage area 3 is transferred tothe read-out register 4 at every one line in the horizontal direction and delivered in time series through the output gate and output diode portion 5.
The output terminal of the output gate and output diode por-tion 5 is grounded through a capacitor 6 and also connected to the source of an FET (field effect transistor) 7 which has the drain supplied with a DC voltage ER and the gate suppliPd with a pre-charge pulse Pa (refer to Fig. 2A) which is syn-chronized with the transfer clock for the read-out register 4.
The connection poLnt between the portion 5 and capacitor 6 is connected to the gate of an FET 8 which has the drain supplied with a DC voltage E and the source connected to the output terminal la.
Thus, in the above output deriving circuit, during a time interval Tp within which the pulse Pa i5 in a high level as shown in Fig. 2A, the FET 7 turns ON and hence the capacitor 6 is pre-charged up to the voltage ER. When a time interval TS within which the pulse Pa is in a low level arrives, the FET 7 turns OFF and hence the voltage across the capacitor 6 becomes low in response to the output signal charge. Therefore, when the ~oltage ER is taken as a reference s~
level, the voltage across the capacitor 6 in the interval TS
becomes the signal level~
In this case, since the pulse Pa is synchron-ized with the transfer clock for the read-out register 4 as set forth above, a charge detected output voltage VO, in which the pre-charge level and signal level will repeat at every one stage portion of the read-out register 4 i.e. one bit portion thereof, appears across the capacitor 6 and such a voltage VO
is delivered to the output terminal la through the FET 8 which forms a buffer amplifier (refer to Fig. 2B).
In this example, in practice, the pulse Pa is jumped into the signal path through the stray capacity between the gate and source of the FET 7, so that a voltage component Ep caused by the jumping of pulse Pa is superimposed on the output voltage VO appearing at the output terminal la as shown in Flg. 2B. Since the jumped-in voltage component Ep, however, is approximately constant, there will occur no trouble even if the signal higher than the level ER by the voltage Ep is taken as the reference level for the signal level. Therefore, in fact there occurs no trouble even if the voltage ER ~ Ep higher than the normal pre-charge level by Ep is taken as the pre-çharge level.
The output voltage VO thus delivered to the output terminal la is supplied to a sampling and hold circuit 10 or to the drain of an FET 11 therein for the sampling. This FET 11 is supplied at its gate with a sampling pulse Pb which becomes a high level in the signal level interval TS of the out-put voltage VO as shown in Fig. 2C, so that the FET 11 turns ON
within the high level interval of the pulse Pb and hence the signal level of the output voltage VO is sampled. Then, a capacitor 12 for the holding in the circuit 10 is charged to L5~
the signal level of the ampled signal or discharged, and hence the signal level is held in the capacitor 12. A held voltage VH across the capacitor 12 is derived through an FET 13 forming a buffer amplifier to an output terminal lb. In Fig.
1, 9 and 14 are respectively load resistors for the FETs 8 and 13.
When the charge stored in the CCD image sensor device is derived after being converted into a volta~e as des-cribed above, it is necessary that when the minority carrier is the electron as set forth above, the capacitor 6 is pre-charged at every one bit. Upon the pre-charge operation, however, such noises as the internal noise in the FET 7, power source noise for the FET 7 and so on are generated, and the reference pre-charge level is fluctuated by the noises. And, a level N of the noises produced in the pre-charge interval is held by the capacitor 6 in one-bit interval T~ = Tp ~ TS or the noise is output in the form of the sample-held. As a result, the output voltage VO becomes fluctuated as shown by the dotted line in Fig. 2B by the noise and hence the signal level in the inter-val TS is also fluctuated. Accordingly if the signal level portion of the output voltage VO is merely sampled and held as in the prior art example of Fig. 1, the noise component is mixed into a signal component S and then delivered as the Outputa OBJECTS AND SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a signal pick-up circuit free from the defects encountered in the prior art.
Another object of the invention is to provide a signal pick-up circuit for use with an image picking-up device which can effectively reduce or remove noises upon pre-charge operation.
S~8 According to an aspect of the present invention there is provided a signal pick-up circuit which comprises:
a) an image pick-up device including a charge transfer ele-ment and producing an output charge corresponding to an object to be picked up;
b~ means for receiving said output charge from said image pick-up device and producing a charge detecting siganl in-cluding a reference level portion and a signal portion pro-vided by charge or discharge in response to said output charge, said reference level portion and said signal portion being repeated at every one bit of said output charge; and c) means for providing a difference output between said reference level portion and said signal portion.
The additional, and other objects, features and advantages of the present invention will become apparent from the following description taken in conjunction with the accom-panying drawings through which the like references designate the same elements and parts.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
The present invention has the base on the fact that the noise level is constant in one-bit interval T B and no signal component is presented in the pre-charge interval Tp and eliminates the noise by obtaining the leve~ difference between the levels of the pre-charge interval Tp and the signal level interval Ts.
r J' ~
5 ~8 An example of -the siclnal ~icl~--up circuit accorclincJ to the present invention wi]] he descri.hed wi.-th reference. to Fic3. 3 which shows the essential part of thc invention.since the other portion oE the invention is sub-stantia].ly the same as that of ~ . 1 or the part ]eft sicle from the dotted li.ne ~ in ricr. 1.
In the example of the inventi.on shown in Fi~. 3, the output voltacJe VO (refer to Ficr. 4~) clerived at the output terminal la i.s fed to a dela5~ cireui.t or ].ine 15 ancl delayed therei.n hy Td ( c Td c ~ as a si~rnal Vod (refer to,FicJ. 4~). This delavecl sic~nal Vod is applied to the inverted input terminal of a cliE~Eerential amplifi.er 16 wllich is also supplied a-t its non-i.nvertecl input'terminal with the sicJnal VO as it is. Thus, the cli.fferential amplifier 16 produces a difference ou-tput het~een both sicJnals VO and Vod.
The output from -the di:Eferent;,al amplifier 16 is fed to the samplin~ and ho]d circuit 10 similar to that of Ficr. 1. In this e~ample, the samplincr and hold circuit 10 is supplied with a sampling pulse SPO (refer to Fig. 4C)'whose period is T~ and which becomes the level "1" in a pre-charcre interval Tp' of the siqnal Vod~ and hence the value of the output from the differential ampli-fier 16.i~n the period Tp' is sample-held.
In this case, durincr the pre-charcre period Tp' of the sicJnal V~d, one input sicJnal VO to the dif~erential amplifier 16 is the sicJnal component plus the noise eom-ponent and the other input siqnal Vod thereto is only tl-e noise component, so that the output from the differential amplifier 16 in this period Tp' becomes such one that the noise component is subtrac-tecl or removed from the original output signal V~. Accordinq]y, the sicJnal ].evel, fro~
which the noise i.s removed, is sample-lle].cl in the samnllng and hold circ~lit 1~ and -then clelivered as the outr!~lt to thc-outnut termi.n,~l lb. In ~igs. ~A and ~, thc clottecl lincs show the detec-tcd si~Jna].s con-tai.ninq no;sos, resr-ectively.
In the e~ample of the invention shown in Fig. 3, in orcler to effectively carry out -the operation of suhtracting the noise component from the si~na]. component with the noise component in the differential. ampli.i.er 16, it lS desired that the above operation i.s carriecl out at the last portion of the si.gnal level per;.ocl TS w]lere the signal level ~ecomes correct. Therefore, as the delay time Td of the delay line 15, ~d~ TS ~ (length of Tp) is opti.mum.
It is needless to say -thcat if the pulse width of the sampling pulse SPO is within the per;.od Tp', ~ ~ the pulse width of the pulse SPO coulcl be shorter -tban T~
: ~ ~ Another example of the invention is shown 20~ i.n Fig. 5. : In this example, in place oE the clelay line 15 used-in the exa~ple of .ig. 3, a samplin~ and hold circuit is employed to delay the signal VO.
: ~
In detail, the output si~nal VO trefer to ~ Fig. 6~ appearing at the output terminal ]a is fed to a : 25 ~ :sampllng and hold cir~cuit 17 which is also supplied with : a samplin$ pulse SPl (refer to Fig. 6B) which has the period of ~, the risinq-up or;front edge clelayed from that o .
:~ ~ the pre-c;harqe interval Tp of the output siqnal vn by ~d = ~B - '.p and the pulse widtll eaual to the period Tp.
Thus, the siqnal level portion of the ou-tput si~nal VO is 9 ~
.
:~
Si~8 sample-held i.n the s~mpling holcl eircuit 17 as a he]d output lls as shown in Fig. 6D. This held ou-tput H~
therefrom is fed to the inverted input termina]. o~ a diEferential amp].iEier 20.
Tl-e outnut signal V~ i.s a1.so .~pplicd to a sampli.nc.J and ho].d circuit ~ which is a]so suppli.cd wi.th a sampling pulse SP2 (reEer to Flq, 6C) which becomes 1~],!1 durin~3 the pre-charge interval T~ of the si~nal VO.
Thus, the level of the signal VO in the interval Tp is sample-he1.cl in tho sampling ancl hold circuit ].8. ~ held ; output IINl (reEer to Fig. 6~) therefrom is fed to a further :~ sampling and hold ci.reuit 19 whieh is also supplied with the sampling pulse S~l. Thus, the held output l-lNl is sample-lleld in the .samplinq and hold eireui.t 19. ~. held ~ ~ 15 output JIN2 (refer to Fig. 6F) therefrom is appli.ed to the :~ ~ non-inverted input terminal of the diEferential amplifier : 20.
Pu].sating voltages ~p' in the respeetive held OUtp~ltS Hs, HNl and HN2 shown in Fi,gs. 6D, 6~ and 6F
are~ jumped-in:pulse eomponents whieh are ~enerated by the faet that the~ samplincJ pulses SPl ancl S~2 respeetively ump into the~output signal through the eapaeity between .
~ the gate souree of FET 11 (refer to Fig. 1) in the sampling~
.
~ : and hold~eireuit 10. ~ ~
:
~:; 25 ~ ~ In thi~s case, sinee the held output EJS from ; ; ~ the sampling and hold cireuit l7 is the sampled value of ;~ ~; the outpu~-t VO in i-ts .signal interva]. Ts, the output HS
: ineludes the si~Jnal eomponent and the noise eomnonent.
~Yhi1e~ sinee the held output HNl from the sampling and ~ hold eireuit .l8 i5 the samp].ed ~alue of the output VO
,o-: ~
6~15 ~ 8 in its pre~charcJe i.nterval Tp, the output 11Nl includes no sicJnal component and only -the noise component. ~ccord-in~ly, the noise component can be rernoved by subtractin~
the output 111~l from the output 1IS. Ilo~ever, since both outputs 11;5 and 1IN] arc sample-hclcl outputs of output ~lo at different times, -thcre is a phase difference between the jump-in pulses in the respective outputs as apparent from Fi~s. 6D and G~. Thercfore, if the difference betwcen the outputs 1-1S anc!11~l is obtained, the jump-in pulses appear as they are.
In the example of the invention shown in Fi~. S, however, the output MNl is further sample-held by the samplincJ pulse SPl, so that the jump-in pulse appearincJ
in the held outpu-t ~1N2 from the samplincJ and hold circuit 19 is same in phase as that appearing in the held output ; : 11S. In other words, the samplincJ and hold circuits l8 and 19 earry out the same operation as that of the delay line 15 ln the example of FicJ. 3. Thus, the differential amplifier 20 produces such an output SOUt to the output terminal lb which includes no noise component and in which .
the ~ump-in pulse upon the samplin~-hold operation is sup~
pressed sufficiently as shown in Fig. 6G.
:
~ s described above, according to the present .
: invention, the noise ~enerated upon the pre-ehar~e operation can be reduced or removed at the output stage of the char~e :
detecting circuit.
In the above examples of the invention, sinee the minority carrier, which is stored in the CCD as the information, i.s the eleetron, upon detectincJ the char~e, the :30 eapaeitor 6 is previously eharged to the reEerenee level and , then discharged in response to the charge. 11owever, 11~15i~3 when the minority carrier is a hole, the stored charge in the capacitor 6 is previously discharged to the reference level and the capacitor 6 is charged in response to the charge~ In the latter case, it is needless to say that the noise generated upon the discharge can be removed or reduced by the manner similar to the case where the minority carrier is the electron.
It would be apparent that the present inven-tion can he applied not only to the above CCD charge transfer element but also to other charge transfer elements such as a BBD tbucket brigade device) or the like with the same effect.
Further, the present invention can be applied to the CCD image pick-up device of a so-called interline type which is different from the CCD image pick-up device shown in Fig. 1 which is the frame transfer type.
It will be apparent that many modifications and variations could be effected by one skilled in the art without departing from the spirits or scope of the novel con-cepts of the present invention, so that the spirits or scope of the invention should be determined by the appended claims only.
.~ ~
Claims
OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A signal pick-up circuit comprising, an image pick-up device including a charge transfer element which produces an output charge corresponding to an image of an object which is scanned, means for receiving said output charge from said image pick-up device and producing a charge detecting signal which includes a reference level signal portion and an intelli-gence signal portion provided by charge or discharge of said output charge, said reference level signal portion and said intelligence signal portion repeating each bit of said output charge; and means for providing an output signal equal to the difference between said reference level signal portion and said intelligence signal portion, wherein said last-mentioned means includes a delay circuit for delaying said charge detecting signal, and a differential amplifier for producing a difference signal between said charge detecting signal and said delayed charge detecting signal and a sample-hold circuit receiving the output of said differential amplifier.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19857/80 | 1980-02-20 | ||
| JP1985780A JPS56116374A (en) | 1980-02-20 | 1980-02-20 | Charge detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1161548A true CA1161548A (en) | 1984-01-31 |
Family
ID=12010894
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000370198A Expired CA1161548A (en) | 1980-02-20 | 1981-02-05 | Signal pick-up circuit |
| CA000427684A Expired CA1165434A (en) | 1980-02-20 | 1983-05-06 | Signal pick-up circuit |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000427684A Expired CA1165434A (en) | 1980-02-20 | 1983-05-06 | Signal pick-up circuit |
Country Status (6)
| Country | Link |
|---|---|
| JP (1) | JPS56116374A (en) |
| AT (1) | AT381425B (en) |
| CA (2) | CA1161548A (en) |
| DE (1) | DE3106359A1 (en) |
| GB (1) | GB2071959B (en) |
| NL (1) | NL192485C (en) |
Families Citing this family (22)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3049043A1 (en) * | 1980-12-24 | 1982-07-15 | Robert Bosch Gmbh, 7000 Stuttgart | METHOD AND ARRANGEMENT FOR SUPPRESSING LOW-FREQUENCY NOISE ON OUTPUT SIGNALS FROM SEMICONDUCTOR SENSORS |
| DE3049130A1 (en) * | 1980-12-24 | 1982-07-15 | Robert Bosch Gmbh, 7000 Stuttgart | Read circuit for solid-state imaging array - eliminates noise by reading each line twice and then subtracting |
| JPS5986379A (en) * | 1982-11-08 | 1984-05-18 | Toshiba Corp | Photoelectric converter |
| JPS59143479A (en) * | 1983-02-04 | 1984-08-17 | Hitachi Ltd | Signal reader of solid state image pickup device |
| JPS59160374A (en) * | 1983-03-02 | 1984-09-11 | Canon Inc | Photoelectric converter |
| JPS6178284A (en) * | 1984-09-25 | 1986-04-21 | Matsushita Electric Ind Co Ltd | Solid-state image pickup device |
| US5737016A (en) * | 1985-11-15 | 1998-04-07 | Canon Kabushiki Kaisha | Solid state image pickup apparatus for reducing noise |
| JPH084127B2 (en) * | 1986-09-30 | 1996-01-17 | キヤノン株式会社 | Photoelectric conversion device |
| US5771070A (en) * | 1985-11-15 | 1998-06-23 | Canon Kabushiki Kaisha | Solid state image pickup apparatus removing noise from the photoelectric converted signal |
| US4914519A (en) * | 1986-09-19 | 1990-04-03 | Canon Kabushiki Kaisha | Apparatus for eliminating noise in a solid-state image pickup device |
| JPS62122468A (en) * | 1985-11-22 | 1987-06-03 | Fuji Photo Film Co Ltd | Signal read circuit for ccd |
| JPS62155575U (en) * | 1986-03-24 | 1987-10-02 | ||
| JP2705054B2 (en) * | 1986-08-02 | 1998-01-26 | ソニー株式会社 | Solid-state imaging device |
| JPS63233693A (en) * | 1987-03-23 | 1988-09-29 | Hitachi Ltd | Signal processing device for solid-state color camera |
| JPS6442990A (en) * | 1987-08-08 | 1989-02-15 | Fujitsu Ltd | Signal sampling system for image pickup device |
| JP2557727B2 (en) * | 1990-07-27 | 1996-11-27 | 三洋電機株式会社 | Noise removal circuit for solid-state image sensor |
| EP0553544A1 (en) * | 1992-01-31 | 1993-08-04 | Matsushita Electric Industrial Co., Ltd. | Multiplexed noise suppression signal recovery for multiphase readout of charge coupled device arrays |
| US5515103A (en) * | 1993-09-30 | 1996-05-07 | Sanyo Electric Co. | Image signal processing apparatus integrated on single semiconductor substrate |
| EP0725535B1 (en) * | 1995-02-01 | 2003-04-23 | Canon Kabushiki Kaisha | Solid-state image pickup device and method of operating the same |
| JP3774499B2 (en) | 1996-01-24 | 2006-05-17 | キヤノン株式会社 | Photoelectric conversion device |
| FR2757336A1 (en) * | 1996-12-13 | 1998-06-19 | Philips Electronics Nv | INTERFACE CIRCUIT FOR VIDEO CAMERA |
| JP2005154133A (en) * | 2003-11-28 | 2005-06-16 | Mitsubishi Electric Corp | Elevator control device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USB299480I5 (en) * | 1972-10-20 | |||
| DE2543083C3 (en) * | 1975-09-26 | 1979-01-11 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Image sensor and method for operating such an image sensor |
| US4079423A (en) * | 1976-10-14 | 1978-03-14 | General Electric Company | Solid state imaging system providing pattern noise cancellation |
| JPS5822900B2 (en) * | 1978-09-25 | 1983-05-12 | 株式会社日立製作所 | solid-state imaging device |
-
1980
- 1980-02-20 JP JP1985780A patent/JPS56116374A/en active Granted
-
1981
- 1981-02-05 CA CA000370198A patent/CA1161548A/en not_active Expired
- 1981-02-16 NL NL8100741A patent/NL192485C/en not_active IP Right Cessation
- 1981-02-17 GB GB8104862A patent/GB2071959B/en not_active Expired
- 1981-02-19 AT AT0076581A patent/AT381425B/en not_active IP Right Cessation
- 1981-02-20 DE DE19813106359 patent/DE3106359A1/en active Granted
-
1983
- 1983-05-06 CA CA000427684A patent/CA1165434A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56116374A (en) | 1981-09-12 |
| GB2071959A (en) | 1981-09-23 |
| CA1165434A (en) | 1984-04-10 |
| JPS6255349B2 (en) | 1987-11-19 |
| DE3106359C2 (en) | 1989-03-16 |
| ATA76581A (en) | 1986-02-15 |
| NL192485B (en) | 1997-04-01 |
| DE3106359A1 (en) | 1982-02-11 |
| GB2071959B (en) | 1984-02-29 |
| NL192485C (en) | 1997-08-04 |
| AT381425B (en) | 1986-10-10 |
| NL8100741A (en) | 1981-09-16 |
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Legal Events
| Date | Code | Title | Description |
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| MKEX | Expiry | ||
| MKEX | Expiry |
Effective date: 20010131 |