DE3106359A1 - SIGNAL RECEIVER CIRCUIT - Google Patents

Description

The invention relates generally to a Signa pickup circuit, and in particular a signal pickup circuit for use with an image pickup device capable of eliminating noise in the precharge operation.

A conventional measure for detecting a signal charge, that by photoelectric conversion in a solid-state image pickup device or an image sensor using, for example, a charge controlled device (CCJ), is reached, and its derivation as an output signal is explained below.

Fig. 1 shows a circuit diagram of an example of the conventional signal output or. a signal pickup circuit for a CCD image sensor. In this example, the operating system for the CCD image sensor is a frame transport syst em, and the minority carriers stored as information are formed by an electron. In which

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Example according to FIG. 1 forms the section to the left of a dashed line P the CCD image sensing device formed on the integrated circuit (IC) chip, and the The portion to the right of the broken line B forms a sample memory circuit which serves as a waveform shaping circuit.

Fig. 1 shows generally a Bildaufnahme_einrichtung 1 and an output terminal la, the or the output signal deriving. the receiving circuit. The image pickup device 1 has a light or photosensitive surface 2, a storage area 3 of the photosensitive surface 2, ¹ ^ a Ausleseregiater k for the storage area 3 and an output gate-to output ^ diode section 5, which is biased in the reverse direction.

The signal line generated in the photosensitive surface 2 is transmitted to the memory area, with such a photoelectric conversion taking place in the photosensitive surface 2 that the signal charge temporarily stored in the memory area 3 is transferred to the readout register 4 for each line in the horizontal direction and over time output gate and output diode section 5 is output. The output terminal> of the output gate and output diode section 5 is connected to ground or grounded via a capacitor 6 and is also connected to the source oinea FET (field effect transistor) 7, the drain of _{which is supplied with a DC voltage E} i} , and its gate to a precharge pulse P (cf.

egg

2A), which is synchronized with the transmission clock for the readout register 4. The connection point between the section 5 and the capacitor 6 is connected to the gate of an FET 8, the drain of which is supplied with a DC voltage E, and the source of which is connected to the Output terminal la is connected.

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Therefore, in the above output signal cutoff circuit, during a time interval T _p during which the pulse Pa is high, as shown in FIG. 2A, the FET 7 turns on and therefore the capacitor 6 is precharged to the voltage E n. When a time interval T _g begins, during which the pulse Pa is at the low level, the FET 7 blocks t, which is why the voltage across the capacitor 6 becomes low depending on the output signal charge. Therefore, if the voltage] "is taken as the reference level, the voltage across the capacitor 6 in the interval T" becomes the signal level.

In this case, since the pulse Pa jmit <em transmission clock for the readout register 4 is synchronized, as mentioned, a charge detection output voltage V _{0 occurs} in which the precharge level and the signal level are repeated for each single-stage section of the readout register k , that is, in the case of a one-bit section, via the capacitor 6, and such a voltage V_ is supplied to the output terminal 1a via the FET 8, which forms a buffer amplifier (cf. FIG. 2B).

In this exemplary embodiment, the pulse, Pa jumps into the signal path via the stray capacitance between aem gate and the source of the FET 7 »so that a voltage component E _p due to the jump of the pulse Pa is _{superimposed on the output voltage V n} which is present at the output terminal la occurs as shown in Fig. 2B. However, since the jump-in voltage component E _p is approximately constant, no deterioration occurs even if a signal which is _{higher than the level E by the voltage E D} is taken as the reference level for the signal level. Therefore, no deterioration actually occurs even if the voltage E + E which is around E ₁ -. higher than normal subpoena

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- 6 level is taken as the precharge level.

The output voltage Vq thus supplied to the output terminal la is supplied to a scan memory circuit 10 or the drain of a PET 11 therein for scanning. This FET 11 is supplied at its gate with a sampling pulse Pb which assumes a high level in the signal _{level interval T g of} the output signal voltage V _n , as shown in Fig. 2C, so that the FET 11 turns on within the high level interval of the pulse Pb, therefore the signal level of the output voltage V is sampled. Then, a capacitor 12 for holding or storing in the circuit 10 is charged or discharged to the signal level of the sampled signal, for which reason the signal level is held or stored in the capacitor 12. A held or stored voltage V n across the capacitor 12 is fed to an output terminal Ib via an FET 13 which forms a buffer amplifier. Also shown in Fig. 1 are charging resistors 9 and I ^ for the FET 8 and 8, respectively.

If the charge stored in the CCD image sensing device is diverted after being converted into a voltage in the manner mentioned, it is necessary that if the minority is the electron, as has been mentioned, the capacitor is precharged at every bit. During the precharge operation, noise signals such as the internal noise of the FET 7, the power source noise for the FET 7 and the like are generated, and the reference precharge level fluctuates by the noise signals. Furthermore, a level V of the noise signals generated in the precharge interval is held or stored by the capacitor 6 in a one-bit interval Y − Tp + T ", or the noise is output in the form of the sampled-stored signal. As a result, the output voltage fluctuates

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V, as shown by the broken line in Fig. 2B, is due to the noise, and therefore the signal level also fluctuates in the interval Tg. As a result, if the signal level portion of the output voltage V _{Q is} merely sampled and stored as in the conventional embodiment of FIG. 1, the noise component is mixed into a signal component S and then output as the output signal.

It is therefore the object of the invention to provide a Si, t nalaufnahmerschaltung, Specify in particular for an image recording device in which while avoiding the disadvantages mentioned Noise due to the precharge operation can be effectively reduced or is removable.

According to one feature of the invention, a signal pickup circuit specified, which has:

a) An image recording device including a charge transport element, which generates an output charge that corresponds to an object or object to be picked up,

b) a device for receiving the initial charge from the Image pickup device and for generating a charge detection signal including a Bizugspegelabschnittes and a signal section, diis through the Charge or discharge achieved depending on the initial charge wherein the reference level portion and the signal portion are repeated at each bit of the output charge be, and

c) a device for achieving a differential output signal between the reference level section and the signal level section.

The invention is further developed by the features of the subclaims.

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The invention is explained in more detail with reference to the exemplary embodiments shown in the drawing; Show it Fig. 1 is a circuit diagram of a conventional charge detection circuit, as an output signal deriving circuit in a solid-state CCD image pickup device is used

2A-2C signal curves for explaining the mode of operation the conventional circuit according to FIG. 1,

Fig. 3 is a systematic representation of the essential Parts of an embodiment of the signal recording circuit according to the invention,

Fig. 4A-4C signal curves to explain the mode of operation of the .Example of the invention according to FIG. 3i

Fig. 5 is a systematic circuit diagram of the essential parts another embodiment of the invention,

Fig. 6A-6G signal curves to explain the mode of operation of the embodiment of the invention shown in FIG.

A conventional circuit has already been explained with reference to FIGS.

The invention is based essentially on the fact that the noise level in an iCinbit interval t is constant and there is no signal component in the _{precharge interval T p} , and eliminates the noise by obtaining the level difference between the levels of the _{precharge interval T p} and the signal level _{interval T g} .

An example of the signal pickup circuit according to the invention will now be explained in more detail with reference to Fig. 3, which shows the essential part of the invention, since the rest parts used in the invention are essentially the same as in Fig. 1 or the part to the left of the dashed line

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- 9 line P in Fig. 1.

In the embodiment of the invention shown in FIG. J , the output voltage V (cf. , ^ i,) »resulting in a ί ignal V _Q. results (Fig. kB). This delayed signal Y 1 is fed to the inverting input terminal of a differential amplifier 16, which is also supplied with the signal V as it is at its non-inverting input terminal. Therefore, the differential amplifier 16 generates a differential output signal between both signals V _Q and V ^.

The output signal from the differential amplifier 16 is fed to the sample storage circuit 10 in a manner similar to that shown in FIG. In this embodiment, the sample storage circuit 10 is _{supplied with a sample pulse SP Q} (Fig. KC) , the period of which is t _R , and the level "1" in the _{precharge interval T p} * of the signal \. assumes, which is why the value of the output signal from the · differential amplifier 16 is sampled ^{in the period Tp 1.}

In this case, during the precharge Pt period tJ of the signal V, an input signal V to the differential amplifier 16 is the signal component plus the noise component and the other input signal V is. only the noise component there, so that the output signal from the differential amplifier 16 in this period T _p 'becomes such an output signal in which the noise component is subtracted or removed _{from the original output signal V 0.} As a result, the signal level from which the noise has been removed is sampled in the sample storage circuit 10 and then sent as an output signal to the output

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connection Ib supplied. In Figs. 4A and ^ B show the Dashed lines each contain noise-containing detection signals.

In the embodiment shown in Fig. 3 dax The invention is for effectively performing the subtracting operation of the flat component from the signal component with the noise component in the differential amplifier 16 it is desirable that the above operation be performed on the last portion of the signal level period T "at which the

Signal level becomes correct. Therefore, as the delay time ¹ ^ X j for the delay line 15, a value of ¹ C, AES T - optimal (length Tp).

Of course, when the pulse width of the sampling pulses SP _{0 is} within the period T _p ^J , the pulse width of the pulses SjP _{0 can be} shorter than T _p *.

Another embodiment of the invention is shown in FIG. shown. In this embodiment, instead of the delay line 15 of FIG. 3 is a sample memory circuit used to delay the signal V_.

ν, In particular, the output signal V _Q (see. Fig. 6A), which occurs at the output terminal la, a sampling memory switch

^v device I7, which is also supplied with a sampling pulse SP ^ (Fig. 6b), which has the period t ", the rising or leading edge compared to that of the precharge interval T _{p of} the output signal V by ■ f = 1" - Tp is delayed, and where the pulse width is equal to the period T _p . Therefore, the signal level _{portion of the output signal f V 0 is} sampled in the sample storage circuit I7 as the latched cder output signal HL · sample, as shown in Fig. 6D. This ge

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The stored output signal Η _ς is fed from there to the inverting input terminal of a differential amplifier 20.

The output signal V _n is also fed to a sampling memory circuit l8 which is also supplied with an Al sampling pulse SP ₂ (FIG. 6C) which becomes "1" during the precharge interval Tp of the signal V_. Therefore, the level of the signal V in the interval T _p in the old memory circuit 18 is sampled. A stored output signal tL ... (FIG. 6E) is fed from there to a further sampling memory circuit 19, which is also supplied with the sampling pulse SP. Therefore, the stored output signal H is sampled in the sample storage circuit I9. A saved output. ' The signal H (cf. FIG. 6F) is fed from there to the non-inverting input terminal of the differential amplifier 20.

Pulsating voltages E 'in the respective stored output signals H _g , H ^. and KL · «, which are shown in FIGS. ÖD, 6E and OF, respectively, are" jumped in "or introduced pulse components which are generated by the fact that the sampling pulses SP ₁ and SP _{3 are} each in the output signal via the capacitance between gate and Source of the FET 11 (Fig. 1) in the sample memory circuit 10 are introduced.

In this case, since the stored output signal Hg from the sample storage circuit 17 contains the sampled

Value of the output signal V _n in its aigna: interval τ

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is, the output signal Hg the signal components and the noise component. On the other hand, since the stored output signal H _N1 from the sample storage circuit l8 contains the sampled value of the output signal V_ in its precharge

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- 12 -

Interval T _p is the output signal EL ·., No signal coraponent and only the noise component. Consequently, the noise component can be removed by subtracting the output signal EL · i from the output signal H _5. However, since both the output signals EL · and EL ·., Are sampled output signals of the output signal V ^ at different times, there is a phase difference between the introduced pulses in the respective output signals as shown in Figs. 6D and 6E. Consequently, if the difference between the output signals Hg and EL ·, is maintained, the pulses introduced appear as they are.

In the exemplary embodiment shown in FIG. 5, however, the output signal H _{N1 is} further increased by means of the sampling pulses SP. sampled so that the introduced pulses appearing in the stored output signal HL * from the sample storage circuit are in phase with those appearing in the stored output signal H. That is, the sample latch circuits 18 and 19 perform the same operation as the delay line 15 in the embodiment of FIG pulses introduced in the scan memory operation are sufficiently suppressed as shown in Fig. 6G.

As explained, according to the invention, the noise generated during the precharge in the output stage of the charge detection circuit be reduced or removed.

In the illustrated embodiments of the invention because the minority carrier, which is in the CCD as information

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mation is stored, the electron is, b <lm capture the charge of the capacitor to the reference level previously charged and then discharged depending on the charge. However, if the minority carrier is a 'hole', the stored charge in the capacitor 6 is previously discharged to the reference level and the capacitor 6 becomes dependent charged by the charge. In the latter case! the noise generated during discharge can of course advertise removed or diminished in a manner as in the case where the minority carrier is the lectron.

Of course, the invention is not limited to the above CCD charge transport element applies, but also to other charge transport elements, such as a bucket chain device (BBD) or the like, m: i t equivalent effect.

The invention is also applicable to a so-called interline CCDJ image pickup device which differs from the frame transport CCD image pickup device shown in FIG 1. differs.

Of course, other embodiments of the invention are also possible.

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Claims (1)

Claims : /1. Signal pickup circuit, with a) an image recording device including a Charge transport element that has an initial charge generated according to an object to be recorded, marked by b) means for receiving the output charge from the imaging means and generating one Charge detection signal including a reference level portion and a signal section that is generated by charging or discharging depending on the initial charge is generated, the reference level portion and the signal portion at each bit of the output charge be repeated, and c) a device (10.15 »16.17-20) for achieving a Difference output signal between the reference level section and the signal section. 130066/061 1 2. Signal pickup circuit according to claim 1, characterized, that the latter device achieves a difference between a signal obtained by delaying the charge detection signal and the original charge detection signal and samples a reference level portion of the delayed signal. 3. Signal pickup circuit according to claim 2, characterized, that the latter means a delay circuit (15) for delaying the charge detection signal and a Differential amplifier (l6) for forming a difference between the charge detection signal and the delayed charge detection signal contains. k. Signal pickup circuit according to Claim 1, characterized in that that the latter set up a difference between one sampled output signal of the signal section of the charge detection signal and a sample stored Section of the reference level section of the charge detection signal forms. 5. Signal pickup circuit according to claim k, characterized in that that the latter device includes a sample memory (17) for sample storage of the signal level portion of the charge requirement as sungssi u; nal β and two sample storage rather (18,19) to the Sampling apoicJns rn a subpoena pog «Labsclmi tts des Contains charge detection signal and its delay. 130066/061 1