DE2837877C2 - Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers - Google Patents

Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers

Info

Publication number
DE2837877C2
DE2837877C2 DE2837877A DE2837877A DE2837877C2 DE 2837877 C2 DE2837877 C2 DE 2837877C2 DE 2837877 A DE2837877 A DE 2837877A DE 2837877 A DE2837877 A DE 2837877A DE 2837877 C2 DE2837877 C2 DE 2837877C2
Authority
DE
Germany
Prior art keywords
memory cells
layer
bit lines
polycrystalline silicon
transistor memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2837877A
Other languages
German (de)
English (en)
Other versions
DE2837877A1 (de
Inventor
Kurt Dr. 8021 Taufkirchen Hoffmann
Heinrich Dipl.-Phys. 8000 München Schulte
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Original Assignee
Siemens AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to DE2837877A priority Critical patent/DE2837877C2/de
Priority to US06/067,926 priority patent/US4334236A/en
Priority to GB7929716A priority patent/GB2029103B/en
Priority to JP11015479A priority patent/JPS5534500A/ja
Priority to FR7921664A priority patent/FR2435106A1/fr
Publication of DE2837877A1 publication Critical patent/DE2837877A1/de
Application granted granted Critical
Publication of DE2837877C2 publication Critical patent/DE2837877C2/de
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/35Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Local Oxidation Of Silicon (AREA)
DE2837877A 1978-08-30 1978-08-30 Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers Expired DE2837877C2 (de)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE2837877A DE2837877C2 (de) 1978-08-30 1978-08-30 Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers
US06/067,926 US4334236A (en) 1978-08-30 1979-08-20 One-transistor dynamic ram with poly bit lines
GB7929716A GB2029103B (en) 1978-08-30 1979-08-28 Mos-integrated semiconductor store
JP11015479A JPS5534500A (en) 1978-08-30 1979-08-29 Integrated mos semiconductor memory and method of manufacturing same
FR7921664A FR2435106A1 (fr) 1978-08-30 1979-08-29 Memoire a semi-conducteurs integree selon la technique mos et procede pour sa fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2837877A DE2837877C2 (de) 1978-08-30 1978-08-30 Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers

Publications (2)

Publication Number Publication Date
DE2837877A1 DE2837877A1 (de) 1980-03-06
DE2837877C2 true DE2837877C2 (de) 1987-04-23

Family

ID=6048279

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2837877A Expired DE2837877C2 (de) 1978-08-30 1978-08-30 Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers

Country Status (5)

Country Link
US (1) US4334236A (US07488766-20090210-C00029.png)
JP (1) JPS5534500A (US07488766-20090210-C00029.png)
DE (1) DE2837877C2 (US07488766-20090210-C00029.png)
FR (1) FR2435106A1 (US07488766-20090210-C00029.png)
GB (1) GB2029103B (US07488766-20090210-C00029.png)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4240195A (en) * 1978-09-15 1980-12-23 Bell Telephone Laboratories, Incorporated Dynamic random access memory
EP0033130B1 (en) * 1980-01-25 1986-01-08 Kabushiki Kaisha Toshiba Semiconductor memory device
US4536941A (en) * 1980-03-21 1985-08-27 Kuo Chang Kiang Method of making high density dynamic memory cell
US4883543A (en) * 1980-06-05 1989-11-28 Texas Instruments Incroporated Shielding for implant in manufacture of dynamic memory
JPS5718356A (en) * 1980-07-07 1982-01-30 Mitsubishi Electric Corp Semiconductor memory storage
JPS5793572A (en) * 1980-12-03 1982-06-10 Nec Corp Manufacture of semiconductor device
DE3046218C2 (de) * 1980-12-08 1982-09-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zur Erzeugung einer Eintransistor-Speicherzelle in Doppelsilizium-Technik
US4403394A (en) * 1980-12-17 1983-09-13 International Business Machines Corporation Formation of bit lines for ram device
JPS5831568A (ja) * 1981-08-18 1983-02-24 Nec Corp 半導体メモリ
US4453176A (en) * 1981-12-31 1984-06-05 International Business Machines Corporation LSI Chip carrier with buried repairable capacitor with low inductance leads
US4887135A (en) * 1982-02-09 1989-12-12 American Telephone And Telegraph Company, At&T Bell Laboratories Dual level polysilicon single transistor-capacitor memory array
US4574465A (en) * 1982-04-13 1986-03-11 Texas Instruments Incorporated Differing field oxide thicknesses in dynamic memory device
US4652898A (en) * 1984-07-19 1987-03-24 International Business Machines Corporation High speed merged charge memory
US4774203A (en) * 1985-10-25 1988-09-27 Hitachi, Ltd. Method for making static random-access memory device
JPH0831565B2 (ja) * 1986-08-05 1996-03-27 三菱電機株式会社 ランダムアクセスメモリ
US5087951A (en) * 1988-05-02 1992-02-11 Micron Technology Semiconductor memory device transistor and cell structure
US10707296B2 (en) * 2018-10-10 2020-07-07 Texas Instruments Incorporated LOCOS with sidewall spacer for different capacitance density capacitors

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2431079C3 (de) * 1974-06-28 1979-12-13 Ibm Deutschland Gmbh, 7000 Stuttgart Dynamischer Halbleiterspeicher mit Zwei-Transistor-Speicherelementen
US4012757A (en) * 1975-05-05 1977-03-15 Intel Corporation Contactless random-access memory cell and cell pair
JPS5853512B2 (ja) * 1976-02-13 1983-11-29 株式会社東芝 半導体記憶装置の製造方法
US4164751A (en) * 1976-11-10 1979-08-14 Texas Instruments Incorporated High capacity dynamic ram cell
US4112575A (en) * 1976-12-20 1978-09-12 Texas Instruments Incorporated Fabrication methods for the high capacity ram cell
JPS5390888A (en) 1977-01-21 1978-08-10 Nec Corp Integrated circuit device
US4240195A (en) * 1978-09-15 1980-12-23 Bell Telephone Laboratories, Incorporated Dynamic random access memory

Also Published As

Publication number Publication date
GB2029103A (en) 1980-03-12
FR2435106A1 (fr) 1980-03-28
DE2837877A1 (de) 1980-03-06
FR2435106B1 (US07488766-20090210-C00029.png) 1984-05-04
US4334236A (en) 1982-06-08
JPS5534500A (en) 1980-03-11
GB2029103B (en) 1983-03-09

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Legal Events

Date Code Title Description
OAP Request for examination filed
OD Request for examination
D2 Grant after examination
8364 No opposition during term of opposition