DE2837877C2 - Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers - Google Patents
Verfahren zur Herstellung eines MOS-integrierten HalbleiterspeichersInfo
- Publication number
- DE2837877C2 DE2837877C2 DE2837877A DE2837877A DE2837877C2 DE 2837877 C2 DE2837877 C2 DE 2837877C2 DE 2837877 A DE2837877 A DE 2837877A DE 2837877 A DE2837877 A DE 2837877A DE 2837877 C2 DE2837877 C2 DE 2837877C2
- Authority
- DE
- Germany
- Prior art keywords
- memory cells
- layer
- bit lines
- polycrystalline silicon
- transistor memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 230000015654 memory Effects 0.000 claims abstract description 63
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 45
- 238000003860 storage Methods 0.000 claims abstract description 17
- 239000003990 capacitor Substances 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 229920005591 polysilicon Polymers 0.000 claims abstract description 6
- 238000009413 insulation Methods 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 19
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000012212 insulator Substances 0.000 claims 3
- 239000002019 doping agent Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/35—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices with charge storage in a depletion layer, e.g. charge coupled devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Local Oxidation Of Silicon (AREA)
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2837877A DE2837877C2 (de) | 1978-08-30 | 1978-08-30 | Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers |
US06/067,926 US4334236A (en) | 1978-08-30 | 1979-08-20 | One-transistor dynamic ram with poly bit lines |
GB7929716A GB2029103B (en) | 1978-08-30 | 1979-08-28 | Mos-integrated semiconductor store |
JP11015479A JPS5534500A (en) | 1978-08-30 | 1979-08-29 | Integrated mos semiconductor memory and method of manufacturing same |
FR7921664A FR2435106A1 (fr) | 1978-08-30 | 1979-08-29 | Memoire a semi-conducteurs integree selon la technique mos et procede pour sa fabrication |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2837877A DE2837877C2 (de) | 1978-08-30 | 1978-08-30 | Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers |
Publications (2)
Publication Number | Publication Date |
---|---|
DE2837877A1 DE2837877A1 (de) | 1980-03-06 |
DE2837877C2 true DE2837877C2 (de) | 1987-04-23 |
Family
ID=6048279
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE2837877A Expired DE2837877C2 (de) | 1978-08-30 | 1978-08-30 | Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers |
Country Status (5)
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4240195A (en) * | 1978-09-15 | 1980-12-23 | Bell Telephone Laboratories, Incorporated | Dynamic random access memory |
EP0033130B1 (en) * | 1980-01-25 | 1986-01-08 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US4536941A (en) * | 1980-03-21 | 1985-08-27 | Kuo Chang Kiang | Method of making high density dynamic memory cell |
US4883543A (en) * | 1980-06-05 | 1989-11-28 | Texas Instruments Incroporated | Shielding for implant in manufacture of dynamic memory |
JPS5718356A (en) * | 1980-07-07 | 1982-01-30 | Mitsubishi Electric Corp | Semiconductor memory storage |
JPS5793572A (en) * | 1980-12-03 | 1982-06-10 | Nec Corp | Manufacture of semiconductor device |
DE3046218C2 (de) * | 1980-12-08 | 1982-09-02 | Siemens AG, 1000 Berlin und 8000 München | Verfahren zur Erzeugung einer Eintransistor-Speicherzelle in Doppelsilizium-Technik |
US4403394A (en) * | 1980-12-17 | 1983-09-13 | International Business Machines Corporation | Formation of bit lines for ram device |
JPS5831568A (ja) * | 1981-08-18 | 1983-02-24 | Nec Corp | 半導体メモリ |
US4453176A (en) * | 1981-12-31 | 1984-06-05 | International Business Machines Corporation | LSI Chip carrier with buried repairable capacitor with low inductance leads |
US4887135A (en) * | 1982-02-09 | 1989-12-12 | American Telephone And Telegraph Company, At&T Bell Laboratories | Dual level polysilicon single transistor-capacitor memory array |
US4574465A (en) * | 1982-04-13 | 1986-03-11 | Texas Instruments Incorporated | Differing field oxide thicknesses in dynamic memory device |
US4652898A (en) * | 1984-07-19 | 1987-03-24 | International Business Machines Corporation | High speed merged charge memory |
US4774203A (en) * | 1985-10-25 | 1988-09-27 | Hitachi, Ltd. | Method for making static random-access memory device |
JPH0831565B2 (ja) * | 1986-08-05 | 1996-03-27 | 三菱電機株式会社 | ランダムアクセスメモリ |
US5087951A (en) * | 1988-05-02 | 1992-02-11 | Micron Technology | Semiconductor memory device transistor and cell structure |
US10707296B2 (en) * | 2018-10-10 | 2020-07-07 | Texas Instruments Incorporated | LOCOS with sidewall spacer for different capacitance density capacitors |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2431079C3 (de) * | 1974-06-28 | 1979-12-13 | Ibm Deutschland Gmbh, 7000 Stuttgart | Dynamischer Halbleiterspeicher mit Zwei-Transistor-Speicherelementen |
US4012757A (en) * | 1975-05-05 | 1977-03-15 | Intel Corporation | Contactless random-access memory cell and cell pair |
JPS5853512B2 (ja) * | 1976-02-13 | 1983-11-29 | 株式会社東芝 | 半導体記憶装置の製造方法 |
US4164751A (en) * | 1976-11-10 | 1979-08-14 | Texas Instruments Incorporated | High capacity dynamic ram cell |
US4112575A (en) * | 1976-12-20 | 1978-09-12 | Texas Instruments Incorporated | Fabrication methods for the high capacity ram cell |
JPS5390888A (en) | 1977-01-21 | 1978-08-10 | Nec Corp | Integrated circuit device |
US4240195A (en) * | 1978-09-15 | 1980-12-23 | Bell Telephone Laboratories, Incorporated | Dynamic random access memory |
-
1978
- 1978-08-30 DE DE2837877A patent/DE2837877C2/de not_active Expired
-
1979
- 1979-08-20 US US06/067,926 patent/US4334236A/en not_active Expired - Lifetime
- 1979-08-28 GB GB7929716A patent/GB2029103B/en not_active Expired
- 1979-08-29 FR FR7921664A patent/FR2435106A1/fr active Granted
- 1979-08-29 JP JP11015479A patent/JPS5534500A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
GB2029103A (en) | 1980-03-12 |
FR2435106A1 (fr) | 1980-03-28 |
DE2837877A1 (de) | 1980-03-06 |
FR2435106B1 (US07488766-20090210-C00029.png) | 1984-05-04 |
US4334236A (en) | 1982-06-08 |
JPS5534500A (en) | 1980-03-11 |
GB2029103B (en) | 1983-03-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
DE3788499T2 (de) | Halbleiter-Grabenkondensator-Struktur. | |
DE3844388C2 (US07488766-20090210-C00029.png) | ||
DE2837877C2 (de) | Verfahren zur Herstellung eines MOS-integrierten Halbleiterspeichers | |
DE3916228C2 (de) | Halbleiterspeichervorrichtung mit Stapelkondensatorzellenstruktur und Verfahren zu ihrer Herstellung | |
DE3037431C2 (US07488766-20090210-C00029.png) | ||
DE4028488C2 (de) | Verfahren zur Herstellung einer Halbleiterspeichervorrichtung | |
DE3844120C2 (de) | Halbleitereinrichtung mit grabenförmiger Struktur | |
DE3910033C2 (de) | Halbleiterspeicher und Verfahren zu dessen Herstellung | |
DE2741152A1 (de) | Speicherzelle fuer einen silizium- gate-n-kanal-mos-direktzugriffspeicher und verfahren zu ihrer herstellung | |
DE3525418A1 (de) | Halbleiterspeichereinrichtung und verfahren zu ihrer herstellung | |
DE2705503C3 (de) | Halbleiterspeicheranordnung | |
DE4016686A1 (de) | Halbleiterspeicher und verfahren zu seiner herstellung | |
DE4029256C2 (de) | Halbleiterspeichervorrichtung mit wenigstens einer DRAM-Speicherzelle und Verfahren zu deren Herstellung | |
DE4038114C2 (de) | Verfahren zum Herstellen eines Halbleiterspeichers | |
DE4007582C2 (de) | Verfahren zum Herstellen von mindestens zwei Kontakten in einem Halbleiterbauelement | |
DE4018412A1 (de) | Verfahren zur herstellung von faltkondensatoren in einem halbleiter und dadurch gefertigte faltkondensatoren | |
DE2705757C2 (de) | Dynamischer Schreib-Lese-Speicher | |
DE4109299C2 (de) | Halbleiterspeichereinrichtung und Herstellungsverfahren hierfür | |
DE4203565C2 (de) | Verfahren zur Herstellung einer Halbleitervorrichtung | |
DE3543937C2 (US07488766-20090210-C00029.png) | ||
DE4034995C2 (de) | Hochintegriertes Halbleiterspeicherbauelement und Verfahren zu seiner Herstellung | |
DE3840559C2 (US07488766-20090210-C00029.png) | ||
DE3140268A1 (de) | Halbleiteranordnung mit mindestens einem feldeffekttransistor und verfahren zu ihrer herstellung | |
DE3927176C2 (US07488766-20090210-C00029.png) | ||
DE4129130C2 (de) | Halbleiter-Speicherbauelement mit einem gestapelten Kondensator |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
OAP | Request for examination filed | ||
OD | Request for examination | ||
D2 | Grant after examination | ||
8364 | No opposition during term of opposition |