DE2707451C2 - Paralleladdierwerk mit durchlaufendem Übertrag zum Addieren von wenigstens zwei aus mehreren Bits bestehenden Summanden - Google Patents

Paralleladdierwerk mit durchlaufendem Übertrag zum Addieren von wenigstens zwei aus mehreren Bits bestehenden Summanden

Info

Publication number
DE2707451C2
DE2707451C2 DE2707451A DE2707451A DE2707451C2 DE 2707451 C2 DE2707451 C2 DE 2707451C2 DE 2707451 A DE2707451 A DE 2707451A DE 2707451 A DE2707451 A DE 2707451A DE 2707451 C2 DE2707451 C2 DE 2707451C2
Authority
DE
Germany
Prior art keywords
circuit
adder
output
carry
exclusive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2707451A
Other languages
German (de)
English (en)
Other versions
DE2707451A1 (de
Inventor
Samuel Saratoga Calif. Schwartz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of DE2707451A1 publication Critical patent/DE2707451A1/de
Application granted granted Critical
Publication of DE2707451C2 publication Critical patent/DE2707451C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/503—Half or full adders, i.e. basic adder cells for one denomination using carry switching, i.e. the incoming carry being connected directly, or only via an inverter, to the carry output under control of a carry propagate signal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/3804—Details
    • G06F2207/386—Special constructional features
    • G06F2207/3872—Precharge of output to prevent leakage

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Logic Circuits (AREA)
DE2707451A 1976-02-23 1977-02-21 Paralleladdierwerk mit durchlaufendem Übertrag zum Addieren von wenigstens zwei aus mehreren Bits bestehenden Summanden Expired DE2707451C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/660,693 US4031379A (en) 1976-02-23 1976-02-23 Propagation line adder and method for binary addition

Publications (2)

Publication Number Publication Date
DE2707451A1 DE2707451A1 (de) 1977-09-01
DE2707451C2 true DE2707451C2 (de) 1984-01-12

Family

ID=24650586

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2707451A Expired DE2707451C2 (de) 1976-02-23 1977-02-21 Paralleladdierwerk mit durchlaufendem Übertrag zum Addieren von wenigstens zwei aus mehreren Bits bestehenden Summanden

Country Status (6)

Country Link
US (1) US4031379A (US20100223739A1-20100909-C00025.png)
JP (1) JPS52116034A (US20100223739A1-20100909-C00025.png)
DE (1) DE2707451C2 (US20100223739A1-20100909-C00025.png)
FR (1) FR2341897A1 (US20100223739A1-20100909-C00025.png)
GB (1) GB1570931A (US20100223739A1-20100909-C00025.png)
HK (1) HK13785A (US20100223739A1-20100909-C00025.png)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5360129A (en) * 1976-11-10 1978-05-30 Nippon Telegr & Teleph Corp <Ntt> Full adder circuit
US4152775A (en) * 1977-07-20 1979-05-01 Intel Corporation Single line propagation adder and method for binary addition
US4369500A (en) * 1980-10-20 1983-01-18 Motorola Inc. High speed NXM bit digital, repeated addition type multiplying circuit
US4439835A (en) * 1981-07-14 1984-03-27 Rockwell International Corporation Apparatus for and method of generation of ripple carry signals in conjunction with logical adding circuitry
US4471455A (en) * 1982-02-04 1984-09-11 Dshkhunian Valery Carry-forming unit
DE3204511A1 (de) * 1982-02-10 1983-08-18 Valerij Leonidovi&ccaron; D&zcaron;chunian Uebertragerzeugungseinheit
US4577282A (en) * 1982-02-22 1986-03-18 Texas Instruments Incorporated Microcomputer system for digital signal processing
JPS5992978U (ja) * 1982-12-13 1984-06-23 三洋電機株式会社 自動販売機の商品規制装置
US4559608A (en) * 1983-01-21 1985-12-17 Harris Corporation Arithmetic logic unit
US4646257A (en) * 1983-10-03 1987-02-24 Texas Instruments Incorporated Digital multiplication circuit for use in a microprocessor
US4763295A (en) * 1983-12-27 1988-08-09 Nec Corporation Carry circuit suitable for a high-speed arithmetic operation
US4680701A (en) * 1984-04-11 1987-07-14 Texas Instruments Incorporated Asynchronous high speed processor having high speed memories with domino circuits contained therein
US4625130A (en) * 1984-05-30 1986-11-25 Burroughs Corporation Mask signal generator
JPS60192075U (ja) * 1984-05-31 1985-12-20 東芝機器株式会社 物品供給装置
US4718034A (en) * 1984-11-08 1988-01-05 Data General Corporation Carry-save propagate adder
US4766565A (en) * 1986-11-14 1988-08-23 International Business Machines Corporation Arithmetic logic circuit having a carry generator
JPH04172011A (ja) * 1990-11-05 1992-06-19 Mitsubishi Electric Corp 半導体集積回路
US5146424A (en) * 1991-11-21 1992-09-08 Unisys Corporation Digital adder having a high-speed low-capacitance carry bypass signal path

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3717755A (en) * 1971-05-21 1973-02-20 Bell Telephone Labor Inc Parallel adder using a carry propagation bus
US3743824A (en) * 1971-06-16 1973-07-03 Rca Corp Carry ripple network for conditional sum adder
US3919536A (en) * 1973-09-13 1975-11-11 Texas Instruments Inc Precharged digital adder and carry circuit
US3843876A (en) * 1973-09-20 1974-10-22 Motorola Inc Electronic digital adder having a high speed carry propagation line
JPS51147933A (en) * 1975-06-13 1976-12-18 Nippon Telegr & Teleph Corp <Ntt> Binary full adder circuit
US3970833A (en) * 1975-06-18 1976-07-20 The United States Of America As Represented By The Secretary Of The Navy High-speed adder

Also Published As

Publication number Publication date
FR2341897B1 (US20100223739A1-20100909-C00025.png) 1983-06-24
GB1570931A (en) 1980-07-09
FR2341897A1 (fr) 1977-09-16
HK13785A (en) 1985-03-08
JPS5522823B2 (US20100223739A1-20100909-C00025.png) 1980-06-19
JPS52116034A (en) 1977-09-29
US4031379A (en) 1977-06-21
DE2707451A1 (de) 1977-09-01

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Legal Events

Date Code Title Description
D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee