DE2547447A1 - Verfahren zum anbringen eines leiterschichtmusters mit in geringem gegenseitigen abstand liegenden teilen, insbesondere bei der herstellung von halbleiteranordnungen - Google Patents

Verfahren zum anbringen eines leiterschichtmusters mit in geringem gegenseitigen abstand liegenden teilen, insbesondere bei der herstellung von halbleiteranordnungen

Info

Publication number
DE2547447A1
DE2547447A1 DE19752547447 DE2547447A DE2547447A1 DE 2547447 A1 DE2547447 A1 DE 2547447A1 DE 19752547447 DE19752547447 DE 19752547447 DE 2547447 A DE2547447 A DE 2547447A DE 2547447 A1 DE2547447 A1 DE 2547447A1
Authority
DE
Germany
Prior art keywords
mask
parts
conductor layer
openings
substrate surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19752547447
Other languages
German (de)
English (en)
Inventor
Hermanus Leonardus Peek
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of DE2547447A1 publication Critical patent/DE2547447A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H10P95/00—
    • H10W20/40—
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
DE19752547447 1974-10-25 1975-10-23 Verfahren zum anbringen eines leiterschichtmusters mit in geringem gegenseitigen abstand liegenden teilen, insbesondere bei der herstellung von halbleiteranordnungen Withdrawn DE2547447A1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7413977A NL7413977A (nl) 1974-10-25 1974-10-25 Aanbrengen van een geleiderlaagpatroon met op een geringe onderlinge afstand gelegen delen, in het bijzonder bij de vervaardiging van half- geleiderinrichtingen.

Publications (1)

Publication Number Publication Date
DE2547447A1 true DE2547447A1 (de) 1976-04-29

Family

ID=19822335

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752547447 Withdrawn DE2547447A1 (de) 1974-10-25 1975-10-23 Verfahren zum anbringen eines leiterschichtmusters mit in geringem gegenseitigen abstand liegenden teilen, insbesondere bei der herstellung von halbleiteranordnungen

Country Status (12)

Country Link
US (1) US4301191A (enExample)
JP (1) JPS5165876A (enExample)
AU (1) AU503144B2 (enExample)
CA (1) CA1043471A (enExample)
CH (1) CH595699A5 (enExample)
DE (1) DE2547447A1 (enExample)
ES (1) ES442026A1 (enExample)
FR (1) FR2290032A1 (enExample)
GB (1) GB1524870A (enExample)
IT (1) IT1043587B (enExample)
NL (1) NL7413977A (enExample)
SE (1) SE7511837L (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD136670A1 (de) * 1976-02-04 1979-07-18 Rudolf Sacher Verfahren und vorrichtung zur herstellung von halbleiterstrukturen
US4469719A (en) * 1981-12-21 1984-09-04 Applied Magnetics-Magnetic Head Divison Corporation Method for controlling the edge gradient of a layer of deposition material
US4691434A (en) * 1982-02-19 1987-09-08 Lasarray Holding Ag Method of making electrically conductive regions in monolithic semiconductor devices as applied to a semiconductor device
GB2131624B (en) * 1982-12-09 1986-07-09 Standard Telephones Cables Ltd Thick film circuits
PH23907A (en) * 1983-09-28 1989-12-18 Rohm & Haas Catalytic process and systems
US6667215B2 (en) * 2002-05-02 2003-12-23 3M Innovative Properties Method of making transistors
KR100950133B1 (ko) * 2002-12-27 2010-03-30 엘지디스플레이 주식회사 인쇄방식에 의한 패턴형성방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL294779A (enExample) * 1962-07-20
US3700510A (en) * 1970-03-09 1972-10-24 Hughes Aircraft Co Masking techniques for use in fabricating microelectronic components
GB1447866A (en) * 1972-11-10 1976-09-02 Nat Res Dev Charge coupled devices and methods of fabricating them

Also Published As

Publication number Publication date
NL7413977A (nl) 1976-04-27
CH595699A5 (enExample) 1978-02-28
FR2290032B1 (enExample) 1980-12-12
GB1524870A (en) 1978-09-13
AU8594575A (en) 1977-04-28
SE7511837L (sv) 1976-04-26
CA1043471A (en) 1978-11-28
AU503144B2 (en) 1979-08-23
ES442026A1 (es) 1977-06-16
US4301191A (en) 1981-11-17
IT1043587B (it) 1980-02-29
FR2290032A1 (fr) 1976-05-28
JPS5165876A (enExample) 1976-06-07

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Legal Events

Date Code Title Description
OD Request for examination
8139 Disposal/non-payment of the annual fee