IT1043587B - Metodo per la formazione di un disegno in uno strato conduttore presentante parti disposte ad una piccola distanza reciproca in particolare nella fabbricazione di ticolare nella fabbricazione di dispositivi semiconduttori - Google Patents

Metodo per la formazione di un disegno in uno strato conduttore presentante parti disposte ad una piccola distanza reciproca in particolare nella fabbricazione di ticolare nella fabbricazione di dispositivi semiconduttori

Info

Publication number
IT1043587B
IT1043587B IT7528575A IT2857575A IT1043587B IT 1043587 B IT1043587 B IT 1043587B IT 7528575 A IT7528575 A IT 7528575A IT 2857575 A IT2857575 A IT 2857575A IT 1043587 B IT1043587 B IT 1043587B
Authority
IT
Italy
Prior art keywords
manufacture
ticolare
formation
conductive layer
mutual distance
Prior art date
Application number
IT7528575A
Other languages
English (en)
Italian (it)
Original Assignee
Philips Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Nv filed Critical Philips Nv
Application granted granted Critical
Publication of IT1043587B publication Critical patent/IT1043587B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D44/00—Charge transfer devices
    • H10D44/40—Charge-coupled devices [CCD]
    • H10D44/45—Charge-coupled devices [CCD] having field effect produced by insulated gate electrodes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/02—Contacts, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/143—Shadow masking
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/944—Shadow
IT7528575A 1974-10-25 1975-10-22 Metodo per la formazione di un disegno in uno strato conduttore presentante parti disposte ad una piccola distanza reciproca in particolare nella fabbricazione di ticolare nella fabbricazione di dispositivi semiconduttori IT1043587B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7413977A NL7413977A (nl) 1974-10-25 1974-10-25 Aanbrengen van een geleiderlaagpatroon met op een geringe onderlinge afstand gelegen delen, in het bijzonder bij de vervaardiging van half- geleiderinrichtingen.

Publications (1)

Publication Number Publication Date
IT1043587B true IT1043587B (it) 1980-02-29

Family

ID=19822335

Family Applications (1)

Application Number Title Priority Date Filing Date
IT7528575A IT1043587B (it) 1974-10-25 1975-10-22 Metodo per la formazione di un disegno in uno strato conduttore presentante parti disposte ad una piccola distanza reciproca in particolare nella fabbricazione di ticolare nella fabbricazione di dispositivi semiconduttori

Country Status (12)

Country Link
US (1) US4301191A (enExample)
JP (1) JPS5165876A (enExample)
AU (1) AU503144B2 (enExample)
CA (1) CA1043471A (enExample)
CH (1) CH595699A5 (enExample)
DE (1) DE2547447A1 (enExample)
ES (1) ES442026A1 (enExample)
FR (1) FR2290032A1 (enExample)
GB (1) GB1524870A (enExample)
IT (1) IT1043587B (enExample)
NL (1) NL7413977A (enExample)
SE (1) SE7511837L (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD136670A1 (de) * 1976-02-04 1979-07-18 Rudolf Sacher Verfahren und vorrichtung zur herstellung von halbleiterstrukturen
US4469719A (en) * 1981-12-21 1984-09-04 Applied Magnetics-Magnetic Head Divison Corporation Method for controlling the edge gradient of a layer of deposition material
US4691434A (en) * 1982-02-19 1987-09-08 Lasarray Holding Ag Method of making electrically conductive regions in monolithic semiconductor devices as applied to a semiconductor device
GB2131624B (en) * 1982-12-09 1986-07-09 Standard Telephones Cables Ltd Thick film circuits
PH23907A (en) * 1983-09-28 1989-12-18 Rohm & Haas Catalytic process and systems
US6667215B2 (en) * 2002-05-02 2003-12-23 3M Innovative Properties Method of making transistors
KR100950133B1 (ko) * 2002-12-27 2010-03-30 엘지디스플레이 주식회사 인쇄방식에 의한 패턴형성방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL294779A (enExample) * 1962-07-20
US3700510A (en) * 1970-03-09 1972-10-24 Hughes Aircraft Co Masking techniques for use in fabricating microelectronic components
GB1447866A (en) * 1972-11-10 1976-09-02 Nat Res Dev Charge coupled devices and methods of fabricating them

Also Published As

Publication number Publication date
SE7511837L (sv) 1976-04-26
GB1524870A (en) 1978-09-13
CH595699A5 (enExample) 1978-02-28
CA1043471A (en) 1978-11-28
NL7413977A (nl) 1976-04-27
ES442026A1 (es) 1977-06-16
AU503144B2 (en) 1979-08-23
AU8594575A (en) 1977-04-28
FR2290032A1 (fr) 1976-05-28
DE2547447A1 (de) 1976-04-29
US4301191A (en) 1981-11-17
JPS5165876A (enExample) 1976-06-07
FR2290032B1 (enExample) 1980-12-12

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