DE2527911A1 - Schaltungsanordnung zur durchfuehrung logischer operationen - Google Patents

Schaltungsanordnung zur durchfuehrung logischer operationen

Info

Publication number
DE2527911A1
DE2527911A1 DE19752527911 DE2527911A DE2527911A1 DE 2527911 A1 DE2527911 A1 DE 2527911A1 DE 19752527911 DE19752527911 DE 19752527911 DE 2527911 A DE2527911 A DE 2527911A DE 2527911 A1 DE2527911 A1 DE 2527911A1
Authority
DE
Germany
Prior art keywords
shift register
group
output
feedback
logic circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
DE19752527911
Other languages
German (de)
English (en)
Inventor
William Francis Beausoleil
Richard Hiller
Gerald Howard Ottaway
Vaughn Donald Winkler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/482,816 external-priority patent/US3987410A/en
Priority claimed from US05/482,824 external-priority patent/US3990045A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2527911A1 publication Critical patent/DE2527911A1/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
    • G06V30/10—Character recognition
    • G06V30/18—Extraction of features or characteristics of the image
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
    • G06V30/10—Character recognition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Logic Circuits (AREA)
  • Character Input (AREA)
DE19752527911 1974-06-24 1975-06-23 Schaltungsanordnung zur durchfuehrung logischer operationen Withdrawn DE2527911A1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/482,816 US3987410A (en) 1974-06-24 1974-06-24 Array logic fabrication for use in pattern recognition equipments and the like
US05/482,824 US3990045A (en) 1974-06-24 1974-06-24 Array logic fabrication for use in pattern recognition equipments and the like

Publications (1)

Publication Number Publication Date
DE2527911A1 true DE2527911A1 (de) 1976-01-08

Family

ID=27047421

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19752527911 Withdrawn DE2527911A1 (de) 1974-06-24 1975-06-23 Schaltungsanordnung zur durchfuehrung logischer operationen

Country Status (4)

Country Link
DE (1) DE2527911A1 (enExample)
FR (1) FR2276738A1 (enExample)
GB (1) GB1476880A (enExample)
IT (1) IT1038696B (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB0525234D0 (en) 2005-12-12 2006-01-18 Qinetiq Ltd Correlation apparatus

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1959073B2 (de) * 1968-11-29 1972-05-04 International Business Machines Corp., Armonk, N.Y. (V.StA.) Verfahren zur zeichenerkennung und vorrichtung zur durchfuehrung des verfahrens
DE2333202A1 (de) * 1972-06-30 1974-01-24 Honeywell Bull Sa Zeichenerkennungsanordnung

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1959073B2 (de) * 1968-11-29 1972-05-04 International Business Machines Corp., Armonk, N.Y. (V.StA.) Verfahren zur zeichenerkennung und vorrichtung zur durchfuehrung des verfahrens
DE2333202A1 (de) * 1972-06-30 1974-01-24 Honeywell Bull Sa Zeichenerkennungsanordnung

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
MOS/LSI Design and Application, Mc Graw-Hill Book Company, 1972, S. 229-235 *

Also Published As

Publication number Publication date
GB1476880A (en) 1977-06-16
IT1038696B (it) 1979-11-30
FR2276738A1 (fr) 1976-01-23
FR2276738B1 (enExample) 1977-12-09

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Legal Events

Date Code Title Description
OD Request for examination
8130 Withdrawal