GB1476880A - Data processing apparatus - Google Patents

Data processing apparatus

Info

Publication number
GB1476880A
GB1476880A GB1577075A GB1577075A GB1476880A GB 1476880 A GB1476880 A GB 1476880A GB 1577075 A GB1577075 A GB 1577075A GB 1577075 A GB1577075 A GB 1577075A GB 1476880 A GB1476880 A GB 1476880A
Authority
GB
United Kingdom
Prior art keywords
circuits
latches
shift register
gate
feed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB1577075A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/482,816 external-priority patent/US3987410A/en
Priority claimed from US05/482,824 external-priority patent/US3990045A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB1476880A publication Critical patent/GB1476880A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
    • G06V30/10—Character recognition
    • G06V30/18—Extraction of features or characteristics of the image
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V30/00—Character recognition; Recognising digital ink; Document-oriented image-based pattern recognition
    • G06V30/10—Character recognition

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Logic Circuits (AREA)
  • Character Input (AREA)

Abstract

1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).
GB1577075A 1974-06-24 1975-04-17 Data processing apparatus Expired GB1476880A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/482,816 US3987410A (en) 1974-06-24 1974-06-24 Array logic fabrication for use in pattern recognition equipments and the like
US05/482,824 US3990045A (en) 1974-06-24 1974-06-24 Array logic fabrication for use in pattern recognition equipments and the like

Publications (1)

Publication Number Publication Date
GB1476880A true GB1476880A (en) 1977-06-16

Family

ID=27047421

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1577075A Expired GB1476880A (en) 1974-06-24 1975-04-17 Data processing apparatus

Country Status (4)

Country Link
DE (1) DE2527911A1 (en)
FR (1) FR2276738A1 (en)
GB (1) GB1476880A (en)
IT (1) IT1038696B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8145011B2 (en) 2005-12-12 2012-03-27 Qinetiq Limited Correlation apparatus

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USB618016I5 (en) * 1968-11-29
FR2191788A5 (en) * 1972-06-30 1974-02-01 Honeywell Bull

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8145011B2 (en) 2005-12-12 2012-03-27 Qinetiq Limited Correlation apparatus

Also Published As

Publication number Publication date
FR2276738A1 (en) 1976-01-23
IT1038696B (en) 1979-11-30
DE2527911A1 (en) 1976-01-08
FR2276738B1 (en) 1977-12-09

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee