DE2443850C3 - Hybrid-Mikroschaltung und Verfahren zum Anbringen von Markierungen auf deren Substrat - Google Patents

Hybrid-Mikroschaltung und Verfahren zum Anbringen von Markierungen auf deren Substrat

Info

Publication number
DE2443850C3
DE2443850C3 DE2443850A DE2443850A DE2443850C3 DE 2443850 C3 DE2443850 C3 DE 2443850C3 DE 2443850 A DE2443850 A DE 2443850A DE 2443850 A DE2443850 A DE 2443850A DE 2443850 C3 DE2443850 C3 DE 2443850C3
Authority
DE
Germany
Prior art keywords
substrate
markings
photoresist
photoresist layer
microcircuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2443850A
Other languages
German (de)
English (en)
Other versions
DE2443850A1 (de
DE2443850B2 (de
Inventor
Frank Z. Culver City Keister
Robert Y. Los Angeles Scapple
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Raytheon Co
Original Assignee
Hughes Aircraft Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hughes Aircraft Co filed Critical Hughes Aircraft Co
Publication of DE2443850A1 publication Critical patent/DE2443850A1/de
Publication of DE2443850B2 publication Critical patent/DE2443850B2/de
Application granted granted Critical
Publication of DE2443850C3 publication Critical patent/DE2443850C3/de
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03CPHOTOSENSITIVE MATERIALS FOR PHOTOGRAPHIC PURPOSES; PHOTOGRAPHIC PROCESSES, e.g. CINE, X-RAY, COLOUR, STEREO-PHOTOGRAPHIC PROCESSES; AUXILIARY PROCESSES IN PHOTOGRAPHY
    • G03C11/00Auxiliary processes in photography
    • G03C11/02Marking or applying text
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26Processing photosensitive materials; Apparatus therefor
    • G03F7/40Treatment after imagewise removal, e.g. baking
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10NELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N97/00Electric solid-state thin-film or thick-film devices, not otherwise provided for
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05552Shape in top view
    • H01L2224/05554Shape in top view being square
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49171Fan-out arrangements
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0502Patterning and lithography
    • H05K2203/0514Photodevelopable thick film, e.g. conductive or insulating paste
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1105Heating or thermal processing not related to soldering, firing, curing or laminating, e.g. for shaping the substrate or during finish plating
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12Using specific substances
    • H05K2203/122Organic non-polymeric compounds, e.g. oil, wax or thiol
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/161Using chemical substances, e.g. colored or fluorescent, for facilitating optical or visual inspection

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Apparatuses And Processes For Manufacturing Resistors (AREA)
DE2443850A 1973-10-09 1974-09-13 Hybrid-Mikroschaltung und Verfahren zum Anbringen von Markierungen auf deren Substrat Expired DE2443850C3 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US40452573A 1973-10-09 1973-10-09

Publications (3)

Publication Number Publication Date
DE2443850A1 DE2443850A1 (de) 1975-04-17
DE2443850B2 DE2443850B2 (de) 1977-09-22
DE2443850C3 true DE2443850C3 (de) 1980-04-03

Family

ID=23599946

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2443850A Expired DE2443850C3 (de) 1973-10-09 1974-09-13 Hybrid-Mikroschaltung und Verfahren zum Anbringen von Markierungen auf deren Substrat

Country Status (6)

Country Link
JP (1) JPS5837719B2 (cg-RX-API-DMAC7.html)
DE (1) DE2443850C3 (cg-RX-API-DMAC7.html)
FR (1) FR2247049B1 (cg-RX-API-DMAC7.html)
GB (1) GB1471163A (cg-RX-API-DMAC7.html)
IL (1) IL45626A (cg-RX-API-DMAC7.html)
IT (1) IT1019493B (cg-RX-API-DMAC7.html)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5930545Y2 (ja) * 1976-09-28 1984-08-31 日本電気株式会社 印刷配線板
FR2381627B1 (fr) * 1978-01-20 1983-06-10 Ibm Procede de formation de caracteres sur des touches de clavier et touches de clavier portant des caracteres formes selon ce procede
GB2182207B (en) * 1985-10-29 1988-12-14 Marconi Instruments Ltd Electrical circuit identification
US4668603A (en) * 1986-06-26 1987-05-26 E. I. Du Pont De Nemours And Company Method of making raised relief circuit board with soldered connections having nomenclature applied thereto
GB2211667A (en) * 1986-12-29 1989-07-05 Motorola Inc Method for inspecting printed circuit boards for missing or misplaced components
CN1025460C (zh) * 1988-06-17 1994-07-13 精工爱普生株式会社 多功能电子表
JPH05308176A (ja) * 1992-04-30 1993-11-19 Nec Corp 印刷配線基板
JP2833521B2 (ja) * 1995-05-18 1998-12-09 日本電気株式会社 配線基板

Also Published As

Publication number Publication date
JPS5837719B2 (ja) 1983-08-18
FR2247049A1 (cg-RX-API-DMAC7.html) 1975-05-02
DE2443850A1 (de) 1975-04-17
JPS5065872A (cg-RX-API-DMAC7.html) 1975-06-03
DE2443850B2 (de) 1977-09-22
FR2247049B1 (cg-RX-API-DMAC7.html) 1978-05-05
IL45626A (en) 1976-10-31
GB1471163A (en) 1977-04-21
IT1019493B (it) 1977-11-10
IL45626A0 (en) 1974-11-29

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee