DE2363466C3 - Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung - Google Patents

Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung

Info

Publication number
DE2363466C3
DE2363466C3 DE2363466A DE2363466A DE2363466C3 DE 2363466 C3 DE2363466 C3 DE 2363466C3 DE 2363466 A DE2363466 A DE 2363466A DE 2363466 A DE2363466 A DE 2363466A DE 2363466 C3 DE2363466 C3 DE 2363466C3
Authority
DE
Germany
Prior art keywords
layer
substrate
conductive
insulating layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2363466A
Other languages
German (de)
English (en)
Other versions
DE2363466A1 (de
DE2363466B2 (de
Inventor
Richard Raymond So. Burlington Garnache
William Michael Williston Smith Jun.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US00320394A external-priority patent/US3841926A/en
Priority claimed from US00320395A external-priority patent/US3811076A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2363466A1 publication Critical patent/DE2363466A1/de
Publication of DE2363466B2 publication Critical patent/DE2363466B2/de
Application granted granted Critical
Publication of DE2363466C3 publication Critical patent/DE2363466C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
    • H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
DE2363466A 1973-01-02 1973-12-20 Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung Expired DE2363466C3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US00320394A US3841926A (en) 1973-01-02 1973-01-02 Integrated circuit fabrication process
US00320395A US3811076A (en) 1973-01-02 1973-01-02 Field effect transistor integrated circuit and memory

Publications (3)

Publication Number Publication Date
DE2363466A1 DE2363466A1 (de) 1974-07-04
DE2363466B2 DE2363466B2 (de) 1980-01-24
DE2363466C3 true DE2363466C3 (de) 1980-10-02

Family

ID=26982472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2363466A Expired DE2363466C3 (de) 1973-01-02 1973-12-20 Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung

Country Status (3)

Country Link
CH (1) CH573661A5 (enExample)
DE (1) DE2363466C3 (enExample)
NL (1) NL181471C (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0096096A1 (de) * 1982-06-14 1983-12-21 Ibm Deutschland Gmbh Verfahren zur Einstellung des Kantenwinkels in Polysilicium

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL176415C (nl) * 1976-07-05 1985-04-01 Hitachi Ltd Halfgeleidergeheugeninrichting omvattende een matrix van halfgeleidergeheugencellen, die bestaan uit een veldeffekttransistor en een opslagcapaciteit.
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4222816A (en) * 1978-12-26 1980-09-16 International Business Machines Corporation Method for reducing parasitic capacitance in integrated circuit structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0096096A1 (de) * 1982-06-14 1983-12-21 Ibm Deutschland Gmbh Verfahren zur Einstellung des Kantenwinkels in Polysilicium

Also Published As

Publication number Publication date
CH573661A5 (enExample) 1976-03-15
NL181471B (nl) 1987-03-16
DE2363466A1 (de) 1974-07-04
AU6351973A (en) 1975-06-12
NL181471C (nl) 1987-08-17
DE2363466B2 (de) 1980-01-24
NL7317292A (enExample) 1974-07-04

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Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee