DE2363466C3 - Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung - Google Patents

Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung

Info

Publication number
DE2363466C3
DE2363466C3 DE2363466A DE2363466A DE2363466C3 DE 2363466 C3 DE2363466 C3 DE 2363466C3 DE 2363466 A DE2363466 A DE 2363466A DE 2363466 A DE2363466 A DE 2363466A DE 2363466 C3 DE2363466 C3 DE 2363466C3
Authority
DE
Germany
Prior art keywords
layer
substrate
conductive
insulating layer
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2363466A
Other languages
German (de)
English (en)
Other versions
DE2363466A1 (de
DE2363466B2 (de
Inventor
Richard Raymond So. Burlington Garnache
William Michael Williston Smith Jun.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US00320394A external-priority patent/US3841926A/en
Priority claimed from US00320395A external-priority patent/US3811076A/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of DE2363466A1 publication Critical patent/DE2363466A1/de
Publication of DE2363466B2 publication Critical patent/DE2363466B2/de
Application granted granted Critical
Publication of DE2363466C3 publication Critical patent/DE2363466C3/de
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H10P32/141—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers the applied layer comprising oxides only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/811—Combinations of field-effect devices and one or more diodes, capacitors or resistors
    • H10D84/813—Combinations of field-effect devices and capacitor only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Landscapes

  • Semiconductor Memories (AREA)
DE2363466A 1973-01-02 1973-12-20 Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung Expired DE2363466C3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US00320394A US3841926A (en) 1973-01-02 1973-01-02 Integrated circuit fabrication process
US00320395A US3811076A (en) 1973-01-02 1973-01-02 Field effect transistor integrated circuit and memory

Publications (3)

Publication Number Publication Date
DE2363466A1 DE2363466A1 (de) 1974-07-04
DE2363466B2 DE2363466B2 (de) 1980-01-24
DE2363466C3 true DE2363466C3 (de) 1980-10-02

Family

ID=26982472

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2363466A Expired DE2363466C3 (de) 1973-01-02 1973-12-20 Integrierte Speicheranordnung und Verfahren zur ihrer Herstellung

Country Status (3)

Country Link
CH (1) CH573661A5 (enExample)
DE (1) DE2363466C3 (enExample)
NL (1) NL181471C (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0096096A1 (de) * 1982-06-14 1983-12-21 Ibm Deutschland Gmbh Verfahren zur Einstellung des Kantenwinkels in Polysilicium

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL176415C (nl) * 1976-07-05 1985-04-01 Hitachi Ltd Halfgeleidergeheugeninrichting omvattende een matrix van halfgeleidergeheugencellen, die bestaan uit een veldeffekttransistor en een opslagcapaciteit.
US4190466A (en) * 1977-12-22 1980-02-26 International Business Machines Corporation Method for making a bipolar transistor structure utilizing self-passivating diffusion sources
US4222816A (en) * 1978-12-26 1980-09-16 International Business Machines Corporation Method for reducing parasitic capacitance in integrated circuit structures

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0096096A1 (de) * 1982-06-14 1983-12-21 Ibm Deutschland Gmbh Verfahren zur Einstellung des Kantenwinkels in Polysilicium

Also Published As

Publication number Publication date
DE2363466A1 (de) 1974-07-04
DE2363466B2 (de) 1980-01-24
AU6351973A (en) 1975-06-12
CH573661A5 (enExample) 1976-03-15
NL7317292A (enExample) 1974-07-04
NL181471C (nl) 1987-08-17
NL181471B (nl) 1987-03-16

Similar Documents

Publication Publication Date Title
DE69100789T2 (de) Verfahren zur Herstellung einer Mesatransistor-Grabenkondensator-Speicherzellenstruktur.
DE3884698T2 (de) Verfahren zum Herstellen einer Speicherzelle.
DE3788172T2 (de) MIS integrierte Schaltung, wie eine EPROM-Speicherzelle, und Verfahren zu deren Herstellung.
EP0018501B1 (de) Verfahren zur Herstellung von hochverdichteten vertikalen FETs und eine daraus gebildete Matrixanordnung
DE3841588C2 (enExample)
DE4434040C2 (de) Halbleiterspeichervorrichtung mit einer SOI-Struktur und Verfahren zur Herstellung derselben
DE69122992T2 (de) Verfahren zum Herstellen elektrischer Kontakte an Gatestrukturen auf integrierten Schaltungen
DE2642303A1 (de) Verfahren zur herstellung eines fet- speicherelements und hiernach gebildetes speicherelement einer speicheranordnung
DE3916228A1 (de) Halbleiterspeichervorrichtung mit stapelkondensatorzellenstruktur und verfahren zu ihrer herstellung
EP0744772A1 (de) DRAM-Speicherzelle mit vertikalem Transistor und Verfahren zur Herstellung derselben
DE3844388A1 (de) Dynamische direktzugriffspeichereinrichtung
DE2741152A1 (de) Speicherzelle fuer einen silizium- gate-n-kanal-mos-direktzugriffspeicher und verfahren zu ihrer herstellung
DE2916098A1 (de) Verfahren zur herstellung einer halbleitervorrichtung
DE2716691A1 (de) Feldeffekttransistor und verfahren zu dessen herstellung
DE3787687T2 (de) Halbleiterspeicher.
WO1996033513A1 (de) Festwertspeicherzellenanordnung und verfahren zu deren herstellung
DE69027953T2 (de) Halbleiterspeichervorrichtung
EP0282629B1 (de) Dreidimensionale 1-Transistorzellenanordung für dynamische Halbleiterspeicher mit Grabenkondensator und Verfahren zur Herstellung des Bitleitungskontaktes
DE3224287C2 (enExample)
DE2815605A1 (de) Halbleiterspeicherzelle mit ansteuerleitungen hoher leitfaehigkeit
DE2926334C2 (enExample)
DE3840559C2 (enExample)
DE2837877A1 (de) Mos-integrierter halbleiterspeicher sowie verfahren zu seiner herstellung
DE3543937C2 (enExample)
EP0183138A1 (de) Verfahren zum Herstellen von Hochintegrierten MOS-Transistorschaltungen

Legal Events

Date Code Title Description
C3 Grant after two publication steps (3rd publication)
8339 Ceased/non-payment of the annual fee