DE2357168C2 - Schaltungsanordnung für einen Speichermodul - Google Patents

Schaltungsanordnung für einen Speichermodul

Info

Publication number
DE2357168C2
DE2357168C2 DE2357168A DE2357168A DE2357168C2 DE 2357168 C2 DE2357168 C2 DE 2357168C2 DE 2357168 A DE2357168 A DE 2357168A DE 2357168 A DE2357168 A DE 2357168A DE 2357168 C2 DE2357168 C2 DE 2357168C2
Authority
DE
Germany
Prior art keywords
signal
memory
signals
error
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
DE2357168A
Other languages
German (de)
English (en)
Other versions
DE2357168A1 (de
Inventor
Jahn L. Sudbury Mass. Curley
Benjamin S. Boston Mass. Franklin
John C. Marlboro Mass. Manton
Clester M. Billerica Mass. Nibby jun.
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Bull HN Information Systems Inc
Original Assignee
Honeywell Information Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Honeywell Information Systems Inc filed Critical Honeywell Information Systems Inc
Publication of DE2357168A1 publication Critical patent/DE2357168A1/de
Application granted granted Critical
Publication of DE2357168C2 publication Critical patent/DE2357168C2/de
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
    • G06F11/1056—Updating check bits on partial write, i.e. read/modify/write
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Memory System (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
DE2357168A 1972-11-15 1973-11-15 Schaltungsanordnung für einen Speichermodul Expired DE2357168C2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00306757A US3809884A (en) 1972-11-15 1972-11-15 Apparatus and method for a variable memory cycle in a data processing unit

Publications (2)

Publication Number Publication Date
DE2357168A1 DE2357168A1 (de) 1974-05-22
DE2357168C2 true DE2357168C2 (de) 1984-05-17

Family

ID=23186703

Family Applications (1)

Application Number Title Priority Date Filing Date
DE2357168A Expired DE2357168C2 (de) 1972-11-15 1973-11-15 Schaltungsanordnung für einen Speichermodul

Country Status (7)

Country Link
US (1) US3809884A (enExample)
JP (1) JPS5612959B2 (enExample)
AU (1) AU471749B2 (enExample)
CA (1) CA994917A (enExample)
DE (1) DE2357168C2 (enExample)
FR (1) FR2209471A5 (enExample)
GB (1) GB1428570A (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE30331E (en) * 1973-08-10 1980-07-08 Data General Corporation Data processing system having a unique CPU and memory timing relationship and data path configuration
US4014006A (en) * 1973-08-10 1977-03-22 Data General Corporation Data processing system having a unique cpu and memory tuning relationship and data path configuration
US3924243A (en) * 1974-08-06 1975-12-02 Ibm Cross-field-partitioning in array logic modules
US4060794A (en) * 1976-03-31 1977-11-29 Honeywell Information Systems Inc. Apparatus and method for generating timing signals for latched type memories
US4153941A (en) * 1976-11-11 1979-05-08 Kearney & Trecker Corporation Timing circuit and method for controlling the operation of cyclical devices
US4110842A (en) * 1976-11-15 1978-08-29 Advanced Micro Devices, Inc. Random access memory with memory status for improved access and cycle times
GB1561961A (en) * 1977-04-20 1980-03-05 Int Computers Ltd Data processing units
US4172281A (en) * 1977-08-30 1979-10-23 Hewlett-Packard Company Microprogrammable control processor for a minicomputer or the like
IT1089225B (it) * 1977-12-23 1985-06-18 Honeywell Inf Systems Memoria con dispositivo rivelatore e correttore a intervento selettivo
US4200928A (en) * 1978-01-23 1980-04-29 Sperry Rand Corporation Method and apparatus for weighting the priority of access to variable length data blocks in a multiple-disk drive data storage system having an auxiliary processing device
DE2811318C2 (de) * 1978-03-16 1983-02-17 Ibm Deutschland Gmbh, 7000 Stuttgart Einrichtung zur Übertragung und Speicherung eines Teilwortes
US4225959A (en) * 1978-08-04 1980-09-30 Honeywell Information Systems Inc. Tri-state bussing system
US4319356A (en) * 1979-12-19 1982-03-09 Ncr Corporation Self-correcting memory system
EP0139743A1 (en) * 1983-04-14 1985-05-08 Convergent Technologies Inc. Clock stretching circuitry
US5047967A (en) * 1989-07-19 1991-09-10 Apple Computer, Inc. Digital front end for time measurement and generation of electrical signals
FR2666424B1 (fr) * 1990-08-30 1992-11-06 Bull Sa Procede et dispositif de reglage des signaux d'horloge dans un systeme synchrone.
US5239639A (en) * 1990-11-09 1993-08-24 Intel Corporation Efficient memory controller with an independent clock
US5313475A (en) * 1991-10-31 1994-05-17 International Business Machines Corporation ECC function with self-contained high performance partial write or read/modify/write and parity look-ahead interface scheme
US8139399B2 (en) 2009-10-13 2012-03-20 Mosys, Inc. Multiple cycle memory write completion
JP6072449B2 (ja) * 2012-07-09 2017-02-01 ルネサスエレクトロニクス株式会社 半導体記憶回路及びその動作方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3426328A (en) * 1965-01-18 1969-02-04 Ncr Co Electronic data processing system
US3548177A (en) * 1968-01-18 1970-12-15 Ibm Computer error anticipator and cycle extender
US3573728A (en) * 1969-01-09 1971-04-06 Ibm Memory with error correction for partial store operation
US3623017A (en) * 1969-10-22 1971-11-23 Sperry Rand Corp Dual clocking arrangement for a digital computer
US3610800A (en) * 1969-10-30 1971-10-05 North American Rockwell Digital electronic keyboard instrument with automatic transposition
US3656123A (en) * 1970-04-16 1972-04-11 Ibm Microprogrammed processor with variable basic machine cycle lengths
US3703707A (en) * 1971-04-28 1972-11-21 Burroughs Corp Dual clock memory access control

Also Published As

Publication number Publication date
AU5751873A (en) 1975-01-09
AU471749B2 (en) 1976-04-29
JPS4979736A (enExample) 1974-08-01
JPS5612959B2 (enExample) 1981-03-25
US3809884A (en) 1974-05-07
FR2209471A5 (enExample) 1974-06-28
DE2357168A1 (de) 1974-05-22
GB1428570A (en) 1976-03-17
CA994917A (en) 1976-08-10

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Legal Events

Date Code Title Description
OD Request for examination
8125 Change of the main classification

Ipc: G06F 11/08

D2 Grant after examination
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee