DE2353999A1 - Verfahren zur gleichzeitigen herstellung integrierter schaltungen - Google Patents
Verfahren zur gleichzeitigen herstellung integrierter schaltungenInfo
- Publication number
- DE2353999A1 DE2353999A1 DE19732353999 DE2353999A DE2353999A1 DE 2353999 A1 DE2353999 A1 DE 2353999A1 DE 19732353999 DE19732353999 DE 19732353999 DE 2353999 A DE2353999 A DE 2353999A DE 2353999 A1 DE2353999 A1 DE 2353999A1
- Authority
- DE
- Germany
- Prior art keywords
- wafer
- circuits
- yield
- type
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 20
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 235000012431 wafers Nutrition 0.000 claims description 44
- 238000012360 testing method Methods 0.000 claims description 15
- 239000000203 mixture Substances 0.000 claims description 4
- 230000002950 deficient Effects 0.000 description 6
- 238000009826 distribution Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008030 elimination Effects 0.000 description 1
- 238000003379 elimination reaction Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- General Engineering & Computer Science (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dicing (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US00313366A US3842491A (en) | 1972-12-08 | 1972-12-08 | Manufacture of assorted types of lsi devices on same wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| DE2353999A1 true DE2353999A1 (de) | 1974-06-12 |
Family
ID=23215433
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| DE19732353999 Pending DE2353999A1 (de) | 1972-12-08 | 1973-10-27 | Verfahren zur gleichzeitigen herstellung integrierter schaltungen |
Country Status (5)
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3048362A1 (de) * | 1980-12-20 | 1982-07-29 | Deutsche Itt Industries Gmbh, 7800 Freiburg | "verfahren zur herstellung von halbleiterbauelementen" |
Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4796194A (en) * | 1986-08-20 | 1989-01-03 | Atherton Robert W | Real world modeling and control process |
| JP3309478B2 (ja) * | 1993-02-26 | 2002-07-29 | ソニー株式会社 | チップ管理システムおよびその入力処理方法とロット処理方法およびチップ管理システムによるチップ製造方法 |
| TW248612B (US06244707-20010612-C00011.png) * | 1993-03-31 | 1995-06-01 | Siemens Ag | |
| US5773315A (en) * | 1996-10-28 | 1998-06-30 | Advanced Micro Devices, Inc. | Product wafer yield prediction method employing a unit cell approach |
| US5719605A (en) * | 1996-11-20 | 1998-02-17 | Lexmark International, Inc. | Large array heater chips for thermal ink jet printheads |
| US5916715A (en) * | 1997-09-08 | 1999-06-29 | Advanced Micro Devices, Inc. | Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements |
| US6118137A (en) * | 1997-09-08 | 2000-09-12 | Advanced Micro Devices, Inc. | Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias |
| US6070004A (en) * | 1997-09-25 | 2000-05-30 | Siemens Aktiengesellschaft | Method of maximizing chip yield for semiconductor wafers |
| US6359461B1 (en) | 1998-02-10 | 2002-03-19 | Advanced Micro Devices, Inc. | Test structure for determining the properties of densely packed transistors |
| US5986283A (en) * | 1998-02-25 | 1999-11-16 | Advanced Micro Devices | Test structure for determining how lithographic patterning of a gate conductor affects transistor properties |
| US6380554B1 (en) | 1998-06-08 | 2002-04-30 | Advanced Micro Devices, Inc. | Test structure for electrically measuring the degree of misalignment between successive layers of conductors |
| US6226781B1 (en) | 1998-08-12 | 2001-05-01 | Advanced Micro Devices, Inc. | Modifying a design layer of an integrated circuit using overlying and underlying design layers |
| US6294397B1 (en) | 1999-03-04 | 2001-09-25 | Advanced Micro Devices, Inc. | Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment |
| US6452412B1 (en) | 1999-03-04 | 2002-09-17 | Advanced Micro Devices, Inc. | Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography |
| US6268717B1 (en) | 1999-03-04 | 2001-07-31 | Advanced Micro Devices, Inc. | Semiconductor test structure with intentional partial defects and method of use |
| US6297644B1 (en) | 1999-03-04 | 2001-10-02 | Advanced Micro Devices, Inc. | Multipurpose defect test structure with switchable voltage contrast capability and method of use |
| US6258437B1 (en) | 1999-03-31 | 2001-07-10 | Advanced Micro Devices, Inc. | Test structure and methodology for characterizing etching in an integrated circuit fabrication process |
| US6834262B1 (en) | 1999-07-02 | 2004-12-21 | Cypress Semiconductor Corporation | Scheme for improving the simulation accuracy of integrated circuit patterns by simulation of the mask |
| US6429452B1 (en) | 1999-08-17 | 2002-08-06 | Advanced Micro Devices, Inc. | Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process |
| US6681376B1 (en) * | 2001-10-17 | 2004-01-20 | Cypress Semiconductor Corporation | Integrated scheme for semiconductor device verification |
| JP4137471B2 (ja) * | 2002-03-04 | 2008-08-20 | 東京エレクトロン株式会社 | ダイシング方法、集積回路チップの検査方法及び基板保持装置 |
| US20040219443A1 (en) * | 2003-05-01 | 2004-11-04 | Spears Kurt E. | Method for wafer dicing |
| US7861203B2 (en) * | 2006-12-29 | 2010-12-28 | Cadence Design Systems, Inc. | Method and system for model-based routing of an integrated circuit |
| US7698666B2 (en) * | 2006-12-29 | 2010-04-13 | Cadence Design Systems, Inc. | Method and system for model-based design and layout of an integrated circuit |
| US8234597B2 (en) * | 2008-01-14 | 2012-07-31 | International Business Machines Corporation | Tool and method to graphically correlate process and test data with specific chips on a wafer |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB1001908A (en) * | 1962-08-31 | 1965-08-18 | Texas Instruments Inc | Semiconductor devices |
| US3385702A (en) * | 1962-10-03 | 1968-05-28 | Ibm | Photomechanical method of making metallic patterns |
| US3702025A (en) * | 1969-05-12 | 1972-11-07 | Honeywell Inc | Discretionary interconnection process |
| US3762037A (en) * | 1971-03-30 | 1973-10-02 | Ibm | Method of testing for the operability of integrated semiconductor circuits having a plurality of separable circuits |
| US3720309A (en) * | 1971-12-07 | 1973-03-13 | Teledyne Inc | Method and apparatus for sorting semiconductor dice |
-
1972
- 1972-12-08 US US00313366A patent/US3842491A/en not_active Expired - Lifetime
-
1973
- 1973-10-04 GB GB4630773A patent/GB1400315A/en not_active Expired
- 1973-10-23 FR FR7338739A patent/FR2210016B1/fr not_active Expired
- 1973-10-27 DE DE19732353999 patent/DE2353999A1/de active Pending
- 1973-11-06 JP JP12410473A patent/JPS5615577B2/ja not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3048362A1 (de) * | 1980-12-20 | 1982-07-29 | Deutsche Itt Industries Gmbh, 7800 Freiburg | "verfahren zur herstellung von halbleiterbauelementen" |
Also Published As
| Publication number | Publication date |
|---|---|
| FR2210016A1 (US06244707-20010612-C00011.png) | 1974-07-05 |
| JPS5615577B2 (US06244707-20010612-C00011.png) | 1981-04-10 |
| FR2210016B1 (US06244707-20010612-C00011.png) | 1976-10-01 |
| US3842491A (en) | 1974-10-22 |
| GB1400315A (en) | 1975-07-16 |
| JPS4990085A (US06244707-20010612-C00011.png) | 1974-08-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| OHJ | Non-payment of the annual fee |