DE2352033B2 - Verfahren zur bearbeitung von halbleiterplaettchen - Google Patents

Verfahren zur bearbeitung von halbleiterplaettchen

Info

Publication number
DE2352033B2
DE2352033B2 DE19732352033 DE2352033A DE2352033B2 DE 2352033 B2 DE2352033 B2 DE 2352033B2 DE 19732352033 DE19732352033 DE 19732352033 DE 2352033 A DE2352033 A DE 2352033A DE 2352033 B2 DE2352033 B2 DE 2352033B2
Authority
DE
Germany
Prior art keywords
temperature
furnace
value
emitter
dislocations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
DE19732352033
Other languages
German (de)
English (en)
Other versions
DE2352033A1 (de
Inventor
David F. Los Altos; Schweizer jun. John E. San Jose; Calif. Allison (V.StA.)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Scientific Micro Systems Inc
Original Assignee
Scientific Micro Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Scientific Micro Systems Inc filed Critical Scientific Micro Systems Inc
Publication of DE2352033A1 publication Critical patent/DE2352033A1/de
Publication of DE2352033B2 publication Critical patent/DE2352033B2/de
Ceased legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30604Chemical etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0112Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00Subject matter not provided for in other groups of this subclass
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/003Anneal
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/097Lattice strain and defects
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/938Lattice strain control or utilization

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Weting (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Bipolar Transistors (AREA)
DE19732352033 1972-10-20 1973-10-17 Verfahren zur bearbeitung von halbleiterplaettchen Ceased DE2352033B2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00299606A US3829335A (en) 1972-10-20 1972-10-20 Method for processing semiconductor wafers

Publications (2)

Publication Number Publication Date
DE2352033A1 DE2352033A1 (de) 1974-05-09
DE2352033B2 true DE2352033B2 (de) 1976-02-19

Family

ID=23155513

Family Applications (1)

Application Number Title Priority Date Filing Date
DE19732352033 Ceased DE2352033B2 (de) 1972-10-20 1973-10-17 Verfahren zur bearbeitung von halbleiterplaettchen

Country Status (7)

Country Link
US (1) US3829335A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JPS4995587A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CA (1) CA987792A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE2352033B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
FR (1) FR2204046B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB1436197A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
NL (1) NL7314438A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3914138A (en) * 1974-08-16 1975-10-21 Westinghouse Electric Corp Method of making semiconductor devices by single step diffusion
US4026740A (en) * 1975-10-29 1977-05-31 Intel Corporation Process for fabricating narrow polycrystalline silicon members
FR2435818A1 (fr) * 1978-09-08 1980-04-04 Ibm France Procede pour accroitre l'effet de piegeage interne des corps semi-conducteurs
EP0060676B1 (en) * 1981-03-11 1990-07-25 Fujitsu Limited A method for the production of a semiconductor device comprising annealing a silicon wafer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3723053A (en) * 1971-10-26 1973-03-27 Myers Platter S Heat treating process for semiconductor fabrication

Also Published As

Publication number Publication date
FR2204046B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1978-02-10
CA987792A (en) 1976-04-20
GB1436197A (en) 1976-05-19
JPS4995587A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-09-10
DE2352033A1 (de) 1974-05-09
NL7314438A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-04-23
US3829335A (en) 1974-08-13
FR2204046A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1974-05-17

Similar Documents

Publication Publication Date Title
DE2544736C2 (de) Verfahren zum Entfernen von schnelldiffundierenden metallischen Verunreinigungen aus monokristallinem Silicium
DE4229574C2 (de) Feldeffekttransistor und Verfahren zu dessen Herstellung
DE3787874T2 (de) Verfahren zur Herstellung eines Bauelementes mit einer tiefen Schicht aus Si02.
DE1614540C3 (de) Halbleiteranordnung sowie Verfahren zu ihrer Herstellung
DE69004201T2 (de) Verfahren zur Herstellung einer SOI-Halbleiteranordnung.
DE1163981B (de) Verfahren zur Herstellung von Halbleiteranordnungen mit pn-UEbergang und einer epitaktischen Schicht auf dem Halbleiterkoerper
DE2917455A1 (de) Verfahren zur vollstaendigen ausheilung von gitterdefekten in durch ionenimplantation von phosphor erzeugten n-leitenden zonen einer siliciumhalbleitervorrichtung und zugehoerige siliciumhalbleitervorrichtung
DE1489258B1 (de) Verfahren zum Herstellen einer duennen leitenden Zone unter der Oberflaeche eines Siliciumkoerpers
DE2203123A1 (de) Verfahren und einrichtung zum gettern von halbleitern
DE2052221B2 (de) Verfahren zum erzeugen einer siliciumoxidschicht auf einem siliciumsubstrat und vorrichtung zur durchfuehrung dieses verfahrens
DE2837762C2 (de) Verfahren zur Herstellung von Triacs
DE2352033B2 (de) Verfahren zur bearbeitung von halbleiterplaettchen
DE2931432A1 (de) Eindiffundieren von aluminium in einem offenen rohr
DE2755418A1 (de) Verfahren zur herstellung eines halbleiter-bauelements
DE69122815T2 (de) Verfahren zur Bor-Diffusion in Halbleiterwafern
DE2230749C3 (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE1644045B2 (de) Verfahren zur Herstellung dotierter Galliumphosphideinkristalle zur Verwendung als Halbleiterkörper in elektrolumineszenten Bauelementen mit pnÜbergang
DE2653311A1 (de) Verfahren zum herstellen eines halbleiterelementes
DE2114566A1 (de) Verfahren zum Stabilisieren der elektrischen Eigenschaften von Halbleitereinrichtungen
DE1182750B (de) Verfahren zum Herstellen von Halbleiterbauelementen
DE1564170B2 (de) Halbleiterbauelement hoher schaltgeschwindigkeit und ver fahren zu seiner herstellung
DE2208083A1 (de) Verfahren zur herstellung von p-kanalfeldeffekt-transistoren
DE19924649A1 (de) Halbleiterscheibe mit Kristallgitter-Defekten und Verfahren zur Herstellung derselben
EP0041263B1 (de) Verfahren zur Stabilisierung der Stromverstärkung von NPN-Siliciumtransistoren
DE1282204B (de) Solarzelle und Verfahren zu ihrer Herstellung

Legal Events

Date Code Title Description
8235 Patent refused